drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs_next;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 /*
  34  * Driver configurations
  35  */
  36 struct omap_nand_info {
  37         struct bch_control *control;
  38         enum omap_ecc ecc_scheme;
  39         int cs;
  40 };
  41
  42 /* We are wasting a bit of memory but al least we are safe */
  43 static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
  44
  45 /*
  46  * omap_nand_hwcontrol - Set the address pointers corretly for the
  47  *                      following address/data/command operation
  48  */
  49 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  50                                 uint32_t ctrl)
  51 {
  52         register struct nand_chip *this = mtd->priv;
  53         struct omap_nand_info *info = this->priv;
  54         int cs = info->cs;
  55
  56         /*
  57          * Point the IO_ADDR to DATA and ADDRESS registers instead
  58          * of chip address
  59          */
  60         switch (ctrl) {
  61         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  62                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  63                 break;
  64         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  65                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  66                 break;
  67         case NAND_CTRL_CHANGE | NAND_NCE:
  68                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  69                 break;
  70         }
  71
  72         if (cmd != NAND_CMD_NONE)
  73                 writeb(cmd, this->IO_ADDR_W);
  74 }
  75
  76 /* Check wait pin as dev ready indicator */
  77 static int omap_dev_ready(struct mtd_info *mtd)
  78 {
  79         return gpmc_cfg->status & (1 << 8);
  80 }
  81
  82 /*
  83  * gen_true_ecc - This function will generate true ECC value, which
  84  * can be used when correcting data read from NAND flash memory core
  85  *
  86  * @ecc_buf:    buffer to store ecc code
  87  *
  88  * @return:     re-formatted ECC value
  89  */
  90 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
  91 {
  92         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
  93                 ((ecc_buf[2] & 0x0F) << 8);
  94 }
  95
  96 /*
  97  * omap_correct_data - Compares the ecc read from nand spare area with ECC
  98  * registers values and corrects one bit error if it has occured
  99  * Further details can be had from OMAP TRM and the following selected links:
 100  * http://en.wikipedia.org/wiki/Hamming_code
 101  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
 102  *
 103  * @mtd:                 MTD device structure
 104  * @dat:                 page data
 105  * @read_ecc:            ecc read from nand flash
 106  * @calc_ecc:            ecc read from ECC registers
 107  *
 108  * @return 0 if data is OK or corrected, else returns -1
 109  */
 110 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 111                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 112 {
 113         uint32_t orig_ecc, new_ecc, res, hm;
 114         uint16_t parity_bits, byte;
 115         uint8_t bit;
 116
 117         /* Regenerate the orginal ECC */
 118         orig_ecc = gen_true_ecc(read_ecc);
 119         new_ecc = gen_true_ecc(calc_ecc);
 120         /* Get the XOR of real ecc */
 121         res = orig_ecc ^ new_ecc;
 122         if (res) {
 123                 /* Get the hamming width */
 124                 hm = hweight32(res);
 125                 /* Single bit errors can be corrected! */
 126                 if (hm == 12) {
 127                         /* Correctable data! */
 128                         parity_bits = res >> 16;
 129                         bit = (parity_bits & 0x7);
 130                         byte = (parity_bits >> 3) & 0x1FF;
 131                         /* Flip the bit to correct */
 132                         dat[byte] ^= (0x1 << bit);
 133                 } else if (hm == 1) {
 134                         printf("Error: Ecc is wrong\n");
 135                         /* ECC itself is corrupted */
 136                         return 2;
 137                 } else {
 138                         /*
 139                          * hm distance != parity pairs OR one, could mean 2 bit
 140                          * error OR potentially be on a blank page..
 141                          * orig_ecc: contains spare area data from nand flash.
 142                          * new_ecc: generated ecc while reading data area.
 143                          * Note: if the ecc = 0, all data bits from which it was
 144                          * generated are 0xFF.
 145                          * The 3 byte(24 bits) ecc is generated per 512byte
 146                          * chunk of a page. If orig_ecc(from spare area)
 147                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 148                          * this means that data area is 0xFF and spare area is
 149                          * 0xFF. A sure sign of a erased page!
 150                          */
 151                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 152                                 return 0;
 153                         printf("Error: Bad compare! failed\n");
 154                         /* detected 2 bit error */
 155                         return -1;
 156                 }
 157         }
 158         return 0;
 159 }
 160
 161 /*
 162  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 163  * @mtd:        MTD device structure
 164  * @mode:       Read/Write mode
 165  */
 166 __maybe_unused
 167 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 168 {
 169         struct nand_chip        *nand   = mtd->priv;
 170         struct omap_nand_info   *info   = nand->priv;
 171         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 172         unsigned int ecc_algo = 0;
 173         unsigned int bch_type = 0;
 174         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 175         u32 ecc_size_config_val = 0;
 176         u32 ecc_config_val = 0;
 177         int cs = info->cs;
 178
 179         /* configure GPMC for specific ecc-scheme */
 180         switch (info->ecc_scheme) {
 181         case OMAP_ECC_HAM1_CODE_SW:
 182                 return;
 183         case OMAP_ECC_HAM1_CODE_HW:
 184                 ecc_algo = 0x0;
 185                 bch_type = 0x0;
 186                 bch_wrapmode = 0x00;
 187                 eccsize0 = 0xFF;
 188                 eccsize1 = 0xFF;
 189                 break;
 190         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 191         case OMAP_ECC_BCH8_CODE_HW:
 192                 ecc_algo = 0x1;
 193                 bch_type = 0x1;
 194                 if (mode == NAND_ECC_WRITE) {
 195                         bch_wrapmode = 0x01;
 196                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 197                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 198                 } else {
 199                         bch_wrapmode = 0x01;
 200                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 201                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 202                 }
 203                 break;
 204         case OMAP_ECC_BCH16_CODE_HW:
 205                 ecc_algo = 0x1;
 206                 bch_type = 0x2;
 207                 if (mode == NAND_ECC_WRITE) {
 208                         bch_wrapmode = 0x01;
 209                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 210                         eccsize1 = 52; /* OOB bits in nibbles per sector */
 211                 } else {
 212                         bch_wrapmode = 0x01;
 213                         eccsize0 = 52; /* ECC bits in nibbles per sector */
 214                         eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
 215                 }
 216                 break;
 217         default:
 218                 return;
 219         }
 220         /* Clear ecc and enable bits */
 221         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 222         /* Configure ecc size for BCH */
 223         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 224         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 225
 226         /* Configure device details for BCH engine */
 227         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 228                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 229                         (bch_wrapmode << 8)     | /* wrap mode */
 230                         (dev_width << 7)        | /* bus width */
 231                         (0x0 << 4)              | /* number of sectors */
 232                         (cs <<  1)              | /* ECC CS */
 233                         (0x1));                   /* enable ECC */
 234         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 235 }
 236
 237 /*
 238  *  omap_calculate_ecc - Read ECC result
 239  *  @mtd:       MTD structure
 240  *  @dat:       unused
 241  *  @ecc_code:  ecc_code buffer
 242  *  Using noninverted ECC can be considered ugly since writing a blank
 243  *  page ie. padding will clear the ECC bytes. This is no problem as
 244  *  long nobody is trying to write data on the seemingly unused page.
 245  *  Reading an erased page will produce an ECC mismatch between
 246  *  generated and read ECC bytes that has to be dealt with separately.
 247  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 248  *  is used, the result of read will be 0x0 while the ECC offsets of the
 249  *  spare area will be 0xFF which will result in an ECC mismatch.
 250  */
 251 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 252                                 uint8_t *ecc_code)
 253 {
 254         struct nand_chip *chip = mtd->priv;
 255         struct omap_nand_info *info = chip->priv;
 256         uint32_t *ptr, val = 0;
 257         int8_t i = 0, j;
 258
 259         switch (info->ecc_scheme) {
 260         case OMAP_ECC_HAM1_CODE_HW:
 261                 val = readl(&gpmc_cfg->ecc1_result);
 262                 ecc_code[0] = val & 0xFF;
 263                 ecc_code[1] = (val >> 16) & 0xFF;
 264                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 265                 break;
 266 #ifdef CONFIG_BCH
 267         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 268 #endif
 269         case OMAP_ECC_BCH8_CODE_HW:
 270                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 271                 val = readl(ptr);
 272                 ecc_code[i++] = (val >>  0) & 0xFF;
 273                 ptr--;
 274                 for (j = 0; j < 3; j++) {
 275                         val = readl(ptr);
 276                         ecc_code[i++] = (val >> 24) & 0xFF;
 277                         ecc_code[i++] = (val >> 16) & 0xFF;
 278                         ecc_code[i++] = (val >>  8) & 0xFF;
 279                         ecc_code[i++] = (val >>  0) & 0xFF;
 280                         ptr--;
 281                 }
 282                 break;
 283         case OMAP_ECC_BCH16_CODE_HW:
 284                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
 285                 ecc_code[i++] = (val >>  8) & 0xFF;
 286                 ecc_code[i++] = (val >>  0) & 0xFF;
 287                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
 288                 ecc_code[i++] = (val >> 24) & 0xFF;
 289                 ecc_code[i++] = (val >> 16) & 0xFF;
 290                 ecc_code[i++] = (val >>  8) & 0xFF;
 291                 ecc_code[i++] = (val >>  0) & 0xFF;
 292                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
 293                 ecc_code[i++] = (val >> 24) & 0xFF;
 294                 ecc_code[i++] = (val >> 16) & 0xFF;
 295                 ecc_code[i++] = (val >>  8) & 0xFF;
 296                 ecc_code[i++] = (val >>  0) & 0xFF;
 297                 for (j = 3; j >= 0; j--) {
 298                         val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
 299                                                                         );
 300                         ecc_code[i++] = (val >> 24) & 0xFF;
 301                         ecc_code[i++] = (val >> 16) & 0xFF;
 302                         ecc_code[i++] = (val >>  8) & 0xFF;
 303                         ecc_code[i++] = (val >>  0) & 0xFF;
 304                 }
 305                 break;
 306         default:
 307                 return -EINVAL;
 308         }
 309         /* ECC scheme specific syndrome customizations */
 310         switch (info->ecc_scheme) {
 311         case OMAP_ECC_HAM1_CODE_HW:
 312                 break;
 313 #ifdef CONFIG_BCH
 314         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 315
 316                 for (i = 0; i < chip->ecc.bytes; i++)
 317                         *(ecc_code + i) = *(ecc_code + i) ^
 318                                                 bch8_polynomial[i];
 319                 break;
 320 #endif
 321         case OMAP_ECC_BCH8_CODE_HW:
 322                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 323                 break;
 324         case OMAP_ECC_BCH16_CODE_HW:
 325                 break;
 326         default:
 327                 return -EINVAL;
 328         }
 329         return 0;
 330 }
 331
 332 #ifdef CONFIG_NAND_OMAP_ELM
 333 /*
 334  * omap_reverse_list - re-orders list elements in reverse order [internal]
 335  * @list:       pointer to start of list
 336  * @length:     length of list
 337 */
 338 static void omap_reverse_list(u8 *list, unsigned int length)
 339 {
 340         unsigned int i, j;
 341         unsigned int half_length = length / 2;
 342         u8 tmp;
 343         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 344                 tmp = list[i];
 345                 list[i] = list[j];
 346                 list[j] = tmp;
 347         }
 348 }
 349
 350 /*
 351  * omap_correct_data_bch - Compares the ecc read from nand spare area
 352  * with ECC registers values and corrects one bit error if it has occured
 353  *
 354  * @mtd:        MTD device structure
 355  * @dat:        page data
 356  * @read_ecc:   ecc read from nand flash (ignored)
 357  * @calc_ecc:   ecc read from ECC registers
 358  *
 359  * @return 0 if data is OK or corrected, else returns -1
 360  */
 361 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 362                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 363 {
 364         struct nand_chip *chip = mtd->priv;
 365         struct omap_nand_info *info = chip->priv;
 366         struct nand_ecc_ctrl *ecc = &chip->ecc;
 367         uint32_t error_count = 0, error_max;
 368         uint32_t error_loc[ELM_MAX_ERROR_COUNT];
 369         enum bch_level bch_type;
 370         uint32_t i, ecc_flag = 0;
 371         uint8_t count, err = 0;
 372         uint32_t byte_pos, bit_pos;
 373
 374         /* check calculated ecc */
 375         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 376                 if (calc_ecc[i] != 0x00)
 377                         ecc_flag = 1;
 378         }
 379         if (!ecc_flag)
 380                 return 0;
 381
 382         /* check for whether its a erased-page */
 383         ecc_flag = 0;
 384         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 385                 if (read_ecc[i] != 0xff)
 386                         ecc_flag = 1;
 387         }
 388         if (!ecc_flag)
 389                 return 0;
 390
 391         /*
 392          * while reading ECC result we read it in big endian.
 393          * Hence while loading to ELM we have rotate to get the right endian.
 394          */
 395         switch (info->ecc_scheme) {
 396         case OMAP_ECC_BCH8_CODE_HW:
 397                 bch_type = BCH_8_BIT;
 398                 omap_reverse_list(calc_ecc, ecc->bytes - 1);
 399                 break;
 400         case OMAP_ECC_BCH16_CODE_HW:
 401                 bch_type = BCH_16_BIT;
 402                 omap_reverse_list(calc_ecc, ecc->bytes);
 403                 break;
 404         default:
 405                 return -EINVAL;
 406         }
 407         /* use elm module to check for errors */
 408         elm_config(bch_type);
 409         err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
 410         if (err)
 411                 return err;
 412
 413         /* correct bch error */
 414         for (count = 0; count < error_count; count++) {
 415                 switch (info->ecc_scheme) {
 416                 case OMAP_ECC_BCH8_CODE_HW:
 417                         /* 14th byte in ECC is reserved to match ROM layout */
 418                         error_max = SECTOR_BYTES + (ecc->bytes - 1);
 419                         break;
 420                 case OMAP_ECC_BCH16_CODE_HW:
 421                         error_max = SECTOR_BYTES + ecc->bytes;
 422                         break;
 423                 default:
 424                         return -EINVAL;
 425                 }
 426                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 427                 bit_pos  = error_loc[count] % 8;
 428                 if (byte_pos < SECTOR_BYTES) {
 429                         dat[byte_pos] ^= 1 << bit_pos;
 430                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 431                 } else if (byte_pos < error_max) {
 432                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 433                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 434                                                                 SECTOR_BYTES);
 435                 } else {
 436                         err = -EBADMSG;
 437                         printf("nand: error: invalid bit-flip location\n");
 438                 }
 439         }
 440         return (err) ? err : error_count;
 441 }
 442
 443 /**
 444  * omap_read_page_bch - hardware ecc based page read function
 445  * @mtd:        mtd info structure
 446  * @chip:       nand chip info structure
 447  * @buf:        buffer to store read data
 448  * @oob_required: caller expects OOB data read to chip->oob_poi
 449  * @page:       page number to read
 450  *
 451  */
 452 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 453                                 uint8_t *buf, int oob_required, int page)
 454 {
 455         int i, eccsize = chip->ecc.size;
 456         int eccbytes = chip->ecc.bytes;
 457         int eccsteps = chip->ecc.steps;
 458         uint8_t *p = buf;
 459         uint8_t *ecc_calc = chip->buffers->ecccalc;
 460         uint8_t *ecc_code = chip->buffers->ecccode;
 461         uint32_t *eccpos = chip->ecc.layout->eccpos;
 462         uint8_t *oob = chip->oob_poi;
 463         uint32_t data_pos;
 464         uint32_t oob_pos;
 465
 466         data_pos = 0;
 467         /* oob area start */
 468         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
 469         oob += chip->ecc.layout->eccpos[0];
 470
 471         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 472                                 oob += eccbytes) {
 473                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 474                 /* read data */
 475                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
 476                 chip->read_buf(mtd, p, eccsize);
 477
 478                 /* read respective ecc from oob area */
 479                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
 480                 chip->read_buf(mtd, oob, eccbytes);
 481                 /* read syndrome */
 482                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 483
 484                 data_pos += eccsize;
 485                 oob_pos += eccbytes;
 486         }
 487
 488         for (i = 0; i < chip->ecc.total; i++)
 489                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 490
 491         eccsteps = chip->ecc.steps;
 492         p = buf;
 493
 494         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 495                 int stat;
 496
 497                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 498                 if (stat < 0)
 499                         mtd->ecc_stats.failed++;
 500                 else
 501                         mtd->ecc_stats.corrected += stat;
 502         }
 503         return 0;
 504 }
 505 #endif /* CONFIG_NAND_OMAP_ELM */
 506
 507 /*
 508  * OMAP3 BCH8 support (with BCH library)
 509  */
 510 #ifdef CONFIG_BCH
 511 /**
 512  * omap_correct_data_bch_sw - Decode received data and correct errors
 513  * @mtd: MTD device structure
 514  * @data: page data
 515  * @read_ecc: ecc read from nand flash
 516  * @calc_ecc: ecc read from HW ECC registers
 517  */
 518 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 519                                  u_char *read_ecc, u_char *calc_ecc)
 520 {
 521         int i, count;
 522         /* cannot correct more than 8 errors */
 523         unsigned int errloc[8];
 524         struct nand_chip *chip = mtd->priv;
 525         struct omap_nand_info *info = chip->priv;
 526
 527         count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 528                                                         NULL, errloc);
 529         if (count > 0) {
 530                 /* correct errors */
 531                 for (i = 0; i < count; i++) {
 532                         /* correct data only, not ecc bytes */
 533                         if (errloc[i] < 8*512)
 534                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 535                         printf("corrected bitflip %u\n", errloc[i]);
 536 #ifdef DEBUG
 537                         puts("read_ecc: ");
 538                         /*
 539                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 540                          * here!
 541                          */
 542                         for (i = 0; i < 13; i++)
 543                                 printf("%02x ", read_ecc[i]);
 544                         puts("\n");
 545                         puts("calc_ecc: ");
 546                         for (i = 0; i < 13; i++)
 547                                 printf("%02x ", calc_ecc[i]);
 548                         puts("\n");
 549 #endif
 550                 }
 551         } else if (count < 0) {
 552                 puts("ecc unrecoverable error\n");
 553         }
 554         return count;
 555 }
 556
 557 /**
 558  * omap_free_bch - Release BCH ecc resources
 559  * @mtd: MTD device structure
 560  */
 561 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 562 {
 563         struct nand_chip *chip = mtd->priv;
 564         struct omap_nand_info *info = chip->priv;
 565
 566         if (info->control) {
 567                 free_bch(info->control);
 568                 info->control = NULL;
 569         }
 570 }
 571 #endif /* CONFIG_BCH */
 572
 573 /**
 574  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 575  * @nand: NAND chip device structure
 576  * @ecc_scheme: ecc scheme to configure
 577  * @pagesize: number of main-area bytes per page of NAND device
 578  * @oobsize: number of OOB/spare bytes per page of NAND device
 579  */
 580 static int omap_select_ecc_scheme(struct nand_chip *nand,
 581         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 582         struct omap_nand_info   *info           = nand->priv;
 583         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 584         int eccsteps = pagesize / SECTOR_BYTES;
 585         int i;
 586
 587         switch (ecc_scheme) {
 588         case OMAP_ECC_HAM1_CODE_SW:
 589                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 590                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 591                  * initialized in nand_scan_tail(), so just set ecc.mode */
 592                 info->control           = NULL;
 593                 nand->ecc.mode          = NAND_ECC_SOFT;
 594                 nand->ecc.layout        = NULL;
 595                 nand->ecc.size          = 0;
 596                 break;
 597
 598         case OMAP_ECC_HAM1_CODE_HW:
 599                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 600                 /* check ecc-scheme requirements before updating ecc info */
 601                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 602                         printf("nand: error: insufficient OOB: require=%d\n", (
 603                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 604                         return -EINVAL;
 605                 }
 606                 info->control           = NULL;
 607                 /* populate ecc specific fields */
 608                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 609                 nand->ecc.mode          = NAND_ECC_HW;
 610                 nand->ecc.strength      = 1;
 611                 nand->ecc.size          = SECTOR_BYTES;
 612                 nand->ecc.bytes         = 3;
 613                 nand->ecc.hwctl         = omap_enable_hwecc;
 614                 nand->ecc.correct       = omap_correct_data;
 615                 nand->ecc.calculate     = omap_calculate_ecc;
 616                 /* define ecc-layout */
 617                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 618                 for (i = 0; i < ecclayout->eccbytes; i++) {
 619                         if (nand->options & NAND_BUSWIDTH_16)
 620                                 ecclayout->eccpos[i] = i + 2;
 621                         else
 622                                 ecclayout->eccpos[i] = i + 1;
 623                 }
 624                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 625                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 626                                                 BADBLOCK_MARKER_LENGTH;
 627                 break;
 628
 629         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 630 #ifdef CONFIG_BCH
 631                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 632                 /* check ecc-scheme requirements before updating ecc info */
 633                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 634                         printf("nand: error: insufficient OOB: require=%d\n", (
 635                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 636                         return -EINVAL;
 637                 }
 638                 /* check if BCH S/W library can be used for error detection */
 639                 info->control = init_bch(13, 8, 0x201b);
 640                 if (!info->control) {
 641                         printf("nand: error: could not init_bch()\n");
 642                         return -ENODEV;
 643                 }
 644                 /* populate ecc specific fields */
 645                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 646                 nand->ecc.mode          = NAND_ECC_HW;
 647                 nand->ecc.strength      = 8;
 648                 nand->ecc.size          = SECTOR_BYTES;
 649                 nand->ecc.bytes         = 13;
 650                 nand->ecc.hwctl         = omap_enable_hwecc;
 651                 nand->ecc.correct       = omap_correct_data_bch_sw;
 652                 nand->ecc.calculate     = omap_calculate_ecc;
 653                 /* define ecc-layout */
 654                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 655                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 656                 for (i = 1; i < ecclayout->eccbytes; i++) {
 657                         if (i % nand->ecc.bytes)
 658                                 ecclayout->eccpos[i] =
 659                                                 ecclayout->eccpos[i - 1] + 1;
 660                         else
 661                                 ecclayout->eccpos[i] =
 662                                                 ecclayout->eccpos[i - 1] + 2;
 663                 }
 664                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 665                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 666                                                 BADBLOCK_MARKER_LENGTH;
 667                 break;
 668 #else
 669                 printf("nand: error: CONFIG_BCH required for ECC\n");
 670                 return -EINVAL;
 671 #endif
 672
 673         case OMAP_ECC_BCH8_CODE_HW:
 674 #ifdef CONFIG_NAND_OMAP_ELM
 675                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 676                 /* check ecc-scheme requirements before updating ecc info */
 677                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 678                         printf("nand: error: insufficient OOB: require=%d\n", (
 679                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 680                         return -EINVAL;
 681                 }
 682                 /* intialize ELM for ECC error detection */
 683                 elm_init();
 684                 info->control           = NULL;
 685                 /* populate ecc specific fields */
 686                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 687                 nand->ecc.mode          = NAND_ECC_HW;
 688                 nand->ecc.strength      = 8;
 689                 nand->ecc.size          = SECTOR_BYTES;
 690                 nand->ecc.bytes         = 14;
 691                 nand->ecc.hwctl         = omap_enable_hwecc;
 692                 nand->ecc.correct       = omap_correct_data_bch;
 693                 nand->ecc.calculate     = omap_calculate_ecc;
 694                 nand->ecc.read_page     = omap_read_page_bch;
 695                 /* define ecc-layout */
 696                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 697                 for (i = 0; i < ecclayout->eccbytes; i++)
 698                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 699                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 700                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 701                                                 BADBLOCK_MARKER_LENGTH;
 702                 break;
 703 #else
 704                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 705                 return -EINVAL;
 706 #endif
 707
 708         case OMAP_ECC_BCH16_CODE_HW:
 709 #ifdef CONFIG_NAND_OMAP_ELM
 710                 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
 711                 /* check ecc-scheme requirements before updating ecc info */
 712                 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 713                         printf("nand: error: insufficient OOB: require=%d\n", (
 714                                 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 715                         return -EINVAL;
 716                 }
 717                 /* intialize ELM for ECC error detection */
 718                 elm_init();
 719                 /* populate ecc specific fields */
 720                 nand->ecc.mode          = NAND_ECC_HW;
 721                 nand->ecc.size          = SECTOR_BYTES;
 722                 nand->ecc.bytes         = 26;
 723                 nand->ecc.strength      = 16;
 724                 nand->ecc.hwctl         = omap_enable_hwecc;
 725                 nand->ecc.correct       = omap_correct_data_bch;
 726                 nand->ecc.calculate     = omap_calculate_ecc;
 727                 nand->ecc.read_page     = omap_read_page_bch;
 728                 /* define ecc-layout */
 729                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 730                 for (i = 0; i < ecclayout->eccbytes; i++)
 731                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 732                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 733                 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
 734                                                 BADBLOCK_MARKER_LENGTH;
 735                 break;
 736 #else
 737                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 738                 return -EINVAL;
 739 #endif
 740         default:
 741                 debug("nand: error: ecc scheme not enabled or supported\n");
 742                 return -EINVAL;
 743         }
 744
 745         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
 746         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
 747                 nand->ecc.layout = ecclayout;
 748
 749         info->ecc_scheme = ecc_scheme;
 750         return 0;
 751 }
 752
 753 #ifndef CONFIG_SPL_BUILD
 754 /*
 755  * omap_nand_switch_ecc - switch the ECC operation between different engines
 756  * (h/w and s/w) and different algorithms (hamming and BCHx)
 757  *
 758  * @hardware            - true if one of the HW engines should be used
 759  * @eccstrength         - the number of bits that could be corrected
 760  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
 761  */
 762 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 763 {
 764         struct nand_chip *nand;
 765         struct mtd_info *mtd;
 766         int err = 0;
 767
 768         if (nand_curr_device < 0 ||
 769             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 770             !nand_info[nand_curr_device].name) {
 771                 printf("nand: error: no NAND devices found\n");
 772                 return -ENODEV;
 773         }
 774
 775         mtd = &nand_info[nand_curr_device];
 776         nand = mtd->priv;
 777         nand->options |= NAND_OWN_BUFFERS;
 778         nand->options &= ~NAND_SUBPAGE_READ;
 779         /* Setup the ecc configurations again */
 780         if (hardware) {
 781                 if (eccstrength == 1) {
 782                         err = omap_select_ecc_scheme(nand,
 783                                         OMAP_ECC_HAM1_CODE_HW,
 784                                         mtd->writesize, mtd->oobsize);
 785                 } else if (eccstrength == 8) {
 786                         err = omap_select_ecc_scheme(nand,
 787                                         OMAP_ECC_BCH8_CODE_HW,
 788                                         mtd->writesize, mtd->oobsize);
 789                 } else {
 790                         printf("nand: error: unsupported ECC scheme\n");
 791                         return -EINVAL;
 792                 }
 793         } else {
 794                 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 795                                         mtd->writesize, mtd->oobsize);
 796         }
 797
 798         /* Update NAND handling after ECC mode switch */
 799         if (!err)
 800                 err = nand_scan_tail(mtd);
 801         return err;
 802 }
 803 #endif /* CONFIG_SPL_BUILD */
 804
 805 /*
 806  * Board-specific NAND initialization. The following members of the
 807  * argument are board-specific:
 808  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 809  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
 810  * - cmd_ctrl: hardwarespecific function for accesing control-lines
 811  * - waitfunc: hardwarespecific function for accesing device ready/busy line
 812  * - ecc.hwctl: function to enable (reset) hardware ecc generator
 813  * - ecc.mode: mode of ecc, see defines
 814  * - chip_delay: chip dependent delay for transfering data from array to
 815  *   read regs (tR)
 816  * - options: various chip options. They can partly be set to inform
 817  *   nand_scan about special functionality. See the defines for further
 818  *   explanation
 819  */
 820 int board_nand_init(struct nand_chip *nand)
 821 {
 822         int32_t gpmc_config = 0;
 823         int cs = cs_next++;
 824         int err = 0;
 825         /*
 826          * xloader/Uboot's gpmc configuration would have configured GPMC for
 827          * nand type of memory. The following logic scans and latches on to the
 828          * first CS with NAND type memory.
 829          * TBD: need to make this logic generic to handle multiple CS NAND
 830          * devices.
 831          */
 832         while (cs < GPMC_MAX_CS) {
 833                 /* Check if NAND type is set */
 834                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 835                         /* Found it!! */
 836                         break;
 837                 }
 838                 cs++;
 839         }
 840         if (cs >= GPMC_MAX_CS) {
 841                 printf("nand: error: Unable to find NAND settings in "
 842                         "GPMC Configuration - quitting\n");
 843                 return -ENODEV;
 844         }
 845
 846         gpmc_config = readl(&gpmc_cfg->config);
 847         /* Disable Write protect */
 848         gpmc_config |= 0x10;
 849         writel(gpmc_config, &gpmc_cfg->config);
 850
 851         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 852         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 853         omap_nand_info[cs].control = NULL;
 854         omap_nand_info[cs].cs = cs;
 855         nand->priv      = &omap_nand_info[cs];
 856         nand->cmd_ctrl  = omap_nand_hwcontrol;
 857         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
 858         nand->chip_delay = 100;
 859         nand->ecc.layout = &omap_ecclayout;
 860
 861         /* configure driver and controller based on NAND device bus-width */
 862         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
 863 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
 864         nand->options |= NAND_BUSWIDTH_16;
 865         writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
 866 #else
 867         nand->options &= ~NAND_BUSWIDTH_16;
 868         writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
 869 #endif
 870         /* select ECC scheme */
 871 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
 872         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
 873                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
 874 #else
 875         /* pagesize and oobsize are not required to configure sw ecc-scheme */
 876         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
 877                         0, 0);
 878 #endif
 879         if (err)
 880                 return err;
 881
 882 #ifdef CONFIG_SPL_BUILD
 883         if (nand->options & NAND_BUSWIDTH_16)
 884                 nand->read_buf = nand_read_buf16;
 885         else
 886                 nand->read_buf = nand_read_buf;
 887 #endif
 888
 889         nand->dev_ready = omap_dev_ready;
 890
 891         return 0;
 892 }