drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs_next;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
  34 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
  35         { CONFIG_NAND_OMAP_GPMC_WSCFG };
  36 #else
  37 /* wscfg is preset to zero since its a static variable */
  38 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
  39 #endif
  40
  41 /*
  42  * Driver configurations
  43  */
  44 struct omap_nand_info {
  45         struct bch_control *control;
  46         enum omap_ecc ecc_scheme;
  47         uint8_t cs;
  48         uint8_t ws;             /* wait status pin (0,1) */
  49 };
  50
  51 /* We are wasting a bit of memory but al least we are safe */
  52 static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
  53
  54 static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE;
  55
  56 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  57 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
  58 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
  59
  60 static struct nand_bbt_descr bbt_main_descr = {
  61         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  62                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  63         .offs = 0, /* may be overwritten depending on ECC layout */
  64         .len = 4,
  65         .veroffs = 4, /* may be overwritten depending on ECC layout */
  66         .maxblocks = 4,
  67         .pattern = bbt_pattern,
  68 };
  69
  70 static struct nand_bbt_descr bbt_mirror_descr = {
  71         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  72                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  73         .offs = 0, /* may be overwritten depending on ECC layout */
  74         .len = 4,
  75         .veroffs = 4, /* may be overwritten depending on ECC layout */
  76         .maxblocks = 4,
  77         .pattern = mirror_pattern,
  78 };
  79 #endif
  80
  81 #define PREFETCH_FIFOTHRESHOLD_MAX              0x40
  82 #define PREFETCH_FIFOTHRESHOLD(val)             ((val) << 8)
  83
  84 #define PREFETCH_ENABLEOPTIMIZEDACCESS          (0x1 << 27)
  85
  86 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      (((val) >> 24) & 0x7F)
  87 #define GPMC_PREFETCH_STATUS_COUNT(val)         ((val) & 0x00003fff)
  88
  89 #define CS_NUM_SHIFT                            24
  90 #define ENABLE_PREFETCH                         (0x1 << 7)
  91 #define DMA_MPU_MODE                            2
  92
  93 #define OMAP_NAND_TIMEOUT_MS                    5000
  94
  95 #define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
  96
  97 #ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
  98 /**
  99  * gpmc_prefetch_enable - configures and starts prefetch transfer
 100  * @cs: cs (chip select) number
 101  * @fifo_th: fifo threshold to be used for read/ write
 102  * @count: number of bytes to be transferred
 103  * @is_write: prefetch read(0) or write post(1) mode
 104  */
 105 static inline void gpmc_prefetch_enable(int cs, int fifo_th,
 106                                         unsigned int count, int is_write)
 107 {
 108         writel(count, &gpmc_cfg->pref_config2);
 109
 110         /* Set the prefetch read / post write and enable the engine.
 111          * Set which cs is has requested for.
 112          */
 113         uint32_t val = (cs << CS_NUM_SHIFT) |
 114                 PREFETCH_ENABLEOPTIMIZEDACCESS |
 115                 PREFETCH_FIFOTHRESHOLD(fifo_th) |
 116                 ENABLE_PREFETCH |
 117                 !!is_write;
 118         writel(val, &gpmc_cfg->pref_config1);
 119
 120         /*  Start the prefetch engine */
 121         writel(0x1, &gpmc_cfg->pref_control);
 122 }
 123
 124 /**
 125  * gpmc_prefetch_reset - disables and stops the prefetch engine
 126  */
 127 static inline void gpmc_prefetch_reset(void)
 128 {
 129         /* Stop the PFPW engine */
 130         writel(0x0, &gpmc_cfg->pref_control);
 131
 132         /* Reset/disable the PFPW engine */
 133         writel(0x0, &gpmc_cfg->pref_config1);
 134 }
 135
 136 //#define FIFO_IOADDR           (nand->IO_ADDR_R)
 137 #define FIFO_IOADDR             PISMO1_NAND_BASE
 138
 139 /**
 140  * read_buf_pref - read data from NAND controller into buffer
 141  * @mtd: MTD device structure
 142  * @buf: buffer to store date
 143  * @len: number of bytes to read
 144  */
 145 static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 146 {
 147         gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 0);
 148         do {
 149                 // Get number of bytes waiting in the FIFO
 150                 uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
 151
 152                 if (read_bytes == 0)
 153                         continue;
 154                 // Alignment of Destination Buffer
 155                 while (read_bytes && ((unsigned int)buf & 3)) {
 156                         *buf++ = readb(FIFO_IOADDR);
 157                         read_bytes--;
 158                         len--;
 159                 }
 160                 // Use maximum word size (32bit) inside this loop, because speed is limited by
 161                 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
 162                 len -= read_bytes & ~3;
 163                 while (read_bytes >= 4) {
 164                         *((uint32_t*)buf) = readl(FIFO_IOADDR);
 165                         buf += 4;
 166                         read_bytes -= 4;
 167                 }
 168                 // Transfer the last (non-aligned) bytes only at the last iteration,
 169                 // to maintain full speed up to the end of the transfer.
 170                 if (read_bytes == len) {
 171                         while (read_bytes) {
 172                                 *buf++ = readb(FIFO_IOADDR);
 173                                 read_bytes--;
 174                         }
 175                         len = 0;
 176                 }
 177         } while (len > 0);
 178         gpmc_prefetch_reset();
 179 }
 180
 181 /*
 182  * write_buf_pref - write buffer to NAND controller
 183  * @mtd: MTD device structure
 184  * @buf: data buffer
 185  * @len: number of bytes to write
 186  */
 187 static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len)
 188 {
 189         /*  configure and start prefetch transfer */
 190         gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 1);
 191
 192         while (len) {
 193                 // Get number of free bytes in the FIFO
 194                 uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
 195
 196                 // don't write more bytes than requested
 197                 if (write_bytes > len)
 198                         write_bytes = len;
 199
 200                 // Alignment of Source Buffer
 201                 while (write_bytes && ((unsigned int)buf & 3)) {
 202                         writeb(*buf++, FIFO_IOADDR);
 203                         write_bytes--;
 204                         len--;
 205                 }
 206
 207                 // Use maximum word size (32bit) inside this loop, because speed is limited by
 208                 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
 209                 len -= write_bytes & ~3;
 210                 while (write_bytes >= 4) {
 211                         writel(*((uint32_t*)buf), FIFO_IOADDR);
 212                         buf += 4;
 213                         write_bytes -= 4;
 214                 }
 215
 216                 // Transfer the last (non-aligned) bytes only at the last iteration,
 217                 // to maintain full speed up to the end of the transfer.
 218                 if (write_bytes == len) {
 219                         while (write_bytes) {
 220                                 writeb(*buf++, FIFO_IOADDR);
 221                                 write_bytes--;
 222                         }
 223                         len = 0;
 224                 }
 225         }
 226
 227         /* wait for data to be flushed out before resetting the prefetch */
 228         while ((len = GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status)))) {
 229                 debug("%u bytes still in FIFO\n", PREFETCH_FIFOTHRESHOLD_MAX - len);
 230                 ndelay(1);
 231         }
 232
 233         /* disable and stop the PFPW engine */
 234         gpmc_prefetch_reset();
 235 }
 236 #endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */
 237
 238 /*
 239  * omap_nand_hwcontrol - Set the address pointers corretly for the
 240  *                      following address/data/command operation
 241  */
 242 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 243                                 uint32_t ctrl)
 244 {
 245         register struct nand_chip *this = mtd->priv;
 246         struct omap_nand_info *info = this->priv;
 247         int cs = info->cs;
 248
 249         /*
 250          * Point the IO_ADDR to DATA and ADDRESS registers instead
 251          * of chip address
 252          */
 253         switch (ctrl) {
 254         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
 255                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 256                 break;
 257         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
 258                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
 259                 break;
 260         case NAND_CTRL_CHANGE | NAND_NCE:
 261                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 262                 break;
 263         }
 264
 265         if (cmd != NAND_CMD_NONE)
 266                 writeb(cmd, this->IO_ADDR_W);
 267 }
 268
 269 /* Check wait pin as dev ready indicator */
 270 static int omap_dev_ready(struct mtd_info *mtd)
 271 {
 272         return !!(readl(&gpmc_cfg->status) & (1 << (8 + info->ws)));
 273 }
 274
 275 /*
 276  * gen_true_ecc - This function will generate true ECC value, which
 277  * can be used when correcting data read from NAND flash memory core
 278  *
 279  * @ecc_buf:    buffer to store ecc code
 280  *
 281  * @return:     re-formatted ECC value
 282  */
 283 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
 284 {
 285         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
 286                 ((ecc_buf[2] & 0x0F) << 8);
 287 }
 288
 289 /*
 290  * omap_correct_data - Compares the ecc read from nand spare area with ECC
 291  * registers values and corrects one bit error if it has occured
 292  * Further details can be had from OMAP TRM and the following selected links:
 293  * http://en.wikipedia.org/wiki/Hamming_code
 294  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
 295  *
 296  * @mtd:                 MTD device structure
 297  * @dat:                 page data
 298  * @read_ecc:            ecc read from nand flash
 299  * @calc_ecc:            ecc read from ECC registers
 300  *
 301  * @return 0 if data is OK or corrected, else returns -1
 302  */
 303 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 304                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 305 {
 306         uint32_t orig_ecc, new_ecc, res, hm;
 307         uint16_t parity_bits, byte;
 308         uint8_t bit;
 309
 310         /* Regenerate the orginal ECC */
 311         orig_ecc = gen_true_ecc(read_ecc);
 312         new_ecc = gen_true_ecc(calc_ecc);
 313         /* Get the XOR of real ecc */
 314         res = orig_ecc ^ new_ecc;
 315         if (res) {
 316                 /* Get the hamming width */
 317                 hm = hweight32(res);
 318                 /* Single bit errors can be corrected! */
 319                 if (hm == 12) {
 320                         /* Correctable data! */
 321                         parity_bits = res >> 16;
 322                         bit = (parity_bits & 0x7);
 323                         byte = (parity_bits >> 3) & 0x1FF;
 324                         /* Flip the bit to correct */
 325                         dat[byte] ^= (0x1 << bit);
 326                 } else if (hm == 1) {
 327                         printf("Error: Ecc is wrong\n");
 328                         /* ECC itself is corrupted */
 329                         return 2;
 330                 } else {
 331                         /*
 332                          * hm distance != parity pairs OR one, could mean 2 bit
 333                          * error OR potentially be on a blank page..
 334                          * orig_ecc: contains spare area data from nand flash.
 335                          * new_ecc: generated ecc while reading data area.
 336                          * Note: if the ecc = 0, all data bits from which it was
 337                          * generated are 0xFF.
 338                          * The 3 byte(24 bits) ecc is generated per 512byte
 339                          * chunk of a page. If orig_ecc(from spare area)
 340                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 341                          * this means that data area is 0xFF and spare area is
 342                          * 0xFF. A sure sign of a erased page!
 343                          */
 344                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 345                                 return 0;
 346                         printf("Error: Bad compare! failed\n");
 347                         /* detected 2 bit error */
 348                         return -1;
 349                 }
 350         }
 351         return 0;
 352 }
 353
 354 /*
 355  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 356  * @mtd:        MTD device structure
 357  * @mode:       Read/Write mode
 358  */
 359 __maybe_unused
 360 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 361 {
 362         struct nand_chip        *nand   = mtd->priv;
 363         struct omap_nand_info   *info   = nand->priv;
 364         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 365         unsigned int ecc_algo = 0;
 366         unsigned int bch_type = 0;
 367         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 368         u32 ecc_size_config_val = 0;
 369         u32 ecc_config_val = 0;
 370         int cs = info->cs;
 371
 372         /* configure GPMC for specific ecc-scheme */
 373         switch (info->ecc_scheme) {
 374         case OMAP_ECC_HAM1_CODE_SW:
 375                 return;
 376         case OMAP_ECC_HAM1_CODE_HW:
 377                 ecc_algo = 0x0;
 378                 bch_type = 0x0;
 379                 bch_wrapmode = 0x00;
 380                 eccsize0 = 0xFF;
 381                 eccsize1 = 0xFF;
 382                 break;
 383         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 384         case OMAP_ECC_BCH8_CODE_HW:
 385                 ecc_algo = 0x1;
 386                 bch_type = 0x1;
 387                 if (mode == NAND_ECC_WRITE) {
 388                         bch_wrapmode = 0x01;
 389                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 390                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 391                 } else {
 392                         bch_wrapmode = 0x01;
 393                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 394                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 395                 }
 396                 break;
 397         case OMAP_ECC_BCH16_CODE_HW:
 398                 ecc_algo = 0x1;
 399                 bch_type = 0x2;
 400                 if (mode == NAND_ECC_WRITE) {
 401                         bch_wrapmode = 0x01;
 402                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 403                         eccsize1 = 52; /* OOB bits in nibbles per sector */
 404                 } else {
 405                         bch_wrapmode = 0x01;
 406                         eccsize0 = 52; /* ECC bits in nibbles per sector */
 407                         eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
 408                 }
 409                 break;
 410         default:
 411                 return;
 412         }
 413         /* Clear ecc and enable bits */
 414         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 415         /* Configure ecc size for BCH */
 416         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 417         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 418
 419         /* Configure device details for BCH engine */
 420         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 421                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 422                         (bch_wrapmode << 8)     | /* wrap mode */
 423                         (dev_width << 7)        | /* bus width */
 424                         (0x0 << 4)              | /* number of sectors */
 425                         (cs <<  1)              | /* ECC CS */
 426                         (0x1));                   /* enable ECC */
 427         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 428 }
 429
 430 /*
 431  *  omap_calculate_ecc - Read ECC result
 432  *  @mtd:       MTD structure
 433  *  @dat:       unused
 434  *  @ecc_code:  ecc_code buffer
 435  *  Using noninverted ECC can be considered ugly since writing a blank
 436  *  page ie. padding will clear the ECC bytes. This is no problem as
 437  *  long nobody is trying to write data on the seemingly unused page.
 438  *  Reading an erased page will produce an ECC mismatch between
 439  *  generated and read ECC bytes that has to be dealt with separately.
 440  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 441  *  is used, the result of read will be 0x0 while the ECC offsets of the
 442  *  spare area will be 0xFF which will result in an ECC mismatch.
 443  */
 444 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 445                                 uint8_t *ecc_code)
 446 {
 447         struct nand_chip *chip = mtd->priv;
 448         struct omap_nand_info *info = chip->priv;
 449         uint32_t *ptr, val = 0;
 450         int8_t i = 0, j;
 451
 452         switch (info->ecc_scheme) {
 453         case OMAP_ECC_HAM1_CODE_HW:
 454                 val = readl(&gpmc_cfg->ecc1_result);
 455                 ecc_code[0] = val & 0xFF;
 456                 ecc_code[1] = (val >> 16) & 0xFF;
 457                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 458                 break;
 459 #ifdef CONFIG_BCH
 460         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 461 #endif
 462         case OMAP_ECC_BCH8_CODE_HW:
 463                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 464                 val = readl(ptr);
 465                 ecc_code[i++] = (val >>  0) & 0xFF;
 466                 ptr--;
 467                 for (j = 0; j < 3; j++) {
 468                         val = readl(ptr);
 469                         ecc_code[i++] = (val >> 24) & 0xFF;
 470                         ecc_code[i++] = (val >> 16) & 0xFF;
 471                         ecc_code[i++] = (val >>  8) & 0xFF;
 472                         ecc_code[i++] = (val >>  0) & 0xFF;
 473                         ptr--;
 474                 }
 475                 break;
 476         case OMAP_ECC_BCH16_CODE_HW:
 477                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
 478                 ecc_code[i++] = (val >>  8) & 0xFF;
 479                 ecc_code[i++] = (val >>  0) & 0xFF;
 480                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
 481                 ecc_code[i++] = (val >> 24) & 0xFF;
 482                 ecc_code[i++] = (val >> 16) & 0xFF;
 483                 ecc_code[i++] = (val >>  8) & 0xFF;
 484                 ecc_code[i++] = (val >>  0) & 0xFF;
 485                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
 486                 ecc_code[i++] = (val >> 24) & 0xFF;
 487                 ecc_code[i++] = (val >> 16) & 0xFF;
 488                 ecc_code[i++] = (val >>  8) & 0xFF;
 489                 ecc_code[i++] = (val >>  0) & 0xFF;
 490                 for (j = 3; j >= 0; j--) {
 491                         val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
 492                                                                         );
 493                         ecc_code[i++] = (val >> 24) & 0xFF;
 494                         ecc_code[i++] = (val >> 16) & 0xFF;
 495                         ecc_code[i++] = (val >>  8) & 0xFF;
 496                         ecc_code[i++] = (val >>  0) & 0xFF;
 497                 }
 498                 break;
 499         default:
 500                 return -EINVAL;
 501         }
 502         /* ECC scheme specific syndrome customizations */
 503         switch (info->ecc_scheme) {
 504         case OMAP_ECC_HAM1_CODE_HW:
 505                 break;
 506 #ifdef CONFIG_BCH
 507         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 508
 509                 for (i = 0; i < chip->ecc.bytes; i++)
 510                         *(ecc_code + i) = *(ecc_code + i) ^
 511                                                 bch8_polynomial[i];
 512                 break;
 513 #endif
 514         case OMAP_ECC_BCH8_CODE_HW:
 515                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 516                 break;
 517         case OMAP_ECC_BCH16_CODE_HW:
 518                 break;
 519         default:
 520                 return -EINVAL;
 521         }
 522         return 0;
 523 }
 524
 525 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
 526
 527 #define PREFETCH_CONFIG1_CS_SHIFT       24
 528 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 529 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 530 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 531 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 532 #define ENABLE_PREFETCH                 (1 << 7)
 533
 534 /**
 535  * omap_prefetch_enable - configures and starts prefetch transfer
 536  * @fifo_th: fifo threshold to be used for read/ write
 537  * @count: number of bytes to be transferred
 538  * @is_write: prefetch read(0) or write post(1) mode
 539  * @cs: chip select to use
 540  */
 541 static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
 542 {
 543         uint32_t val;
 544
 545         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 546                 return -EINVAL;
 547
 548         if (readl(&gpmc_cfg->prefetch_control))
 549                 return -EBUSY;
 550
 551         /* Set the amount of bytes to be prefetched */
 552         writel(count, &gpmc_cfg->prefetch_config2);
 553
 554         val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
 555                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
 556         writel(val, &gpmc_cfg->prefetch_config1);
 557
 558         /*  Start the prefetch engine */
 559         writel(1, &gpmc_cfg->prefetch_control);
 560
 561         return 0;
 562 }
 563
 564 /**
 565  * omap_prefetch_reset - disables and stops the prefetch engine
 566  */
 567 static void omap_prefetch_reset(void)
 568 {
 569         writel(0, &gpmc_cfg->prefetch_control);
 570         writel(0, &gpmc_cfg->prefetch_config1);
 571 }
 572
 573 static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
 574 {
 575         int ret;
 576         uint32_t cnt;
 577         struct omap_nand_info *info = chip->priv;
 578
 579         ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
 580         if (ret < 0)
 581                 return ret;
 582
 583         do {
 584                 int i;
 585
 586                 cnt = readl(&gpmc_cfg->prefetch_status);
 587                 cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
 588
 589                 for (i = 0; i < cnt / 4; i++) {
 590                         *buf++ = readl(CONFIG_SYS_NAND_BASE);
 591                         len -= 4;
 592                 }
 593         } while (len);
 594
 595         omap_prefetch_reset();
 596
 597         return 0;
 598 }
 599
 600 static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
 601 {
 602         struct nand_chip *chip = mtd->priv;
 603
 604         if (chip->options & NAND_BUSWIDTH_16)
 605                 nand_read_buf16(mtd, buf, len);
 606         else
 607                 nand_read_buf(mtd, buf, len);
 608 }
 609
 610 static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 611 {
 612         int ret;
 613         uint32_t head, tail;
 614         struct nand_chip *chip = mtd->priv;
 615
 616         /*
 617          * If the destination buffer is unaligned, start with reading
 618          * the overlap byte-wise.
 619          */
 620         head = ((uint32_t) buf) % 4;
 621         if (head) {
 622                 omap_nand_read(mtd, buf, head);
 623                 buf += head;
 624                 len -= head;
 625         }
 626
 627         /*
 628          * Only transfer multiples of 4 bytes in a pre-fetched fashion.
 629          * If there's a residue, care for it byte-wise afterwards.
 630          */
 631         tail = len % 4;
 632
 633         ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
 634         if (ret < 0) {
 635                 /* fallback in case the prefetch engine is busy */
 636                 omap_nand_read(mtd, buf, len);
 637         } else if (tail) {
 638                 buf += len - tail;
 639                 omap_nand_read(mtd, buf, tail);
 640         }
 641 }
 642 #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
 643
 644 #ifdef CONFIG_NAND_OMAP_ELM
 645 /*
 646  * omap_reverse_list - re-orders list elements in reverse order [internal]
 647  * @list:       pointer to start of list
 648  * @length:     length of list
 649 */
 650 static void omap_reverse_list(u8 *list, unsigned int length)
 651 {
 652         unsigned int i, j;
 653         unsigned int half_length = length / 2;
 654         u8 tmp;
 655         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 656                 tmp = list[i];
 657                 list[i] = list[j];
 658                 list[j] = tmp;
 659         }
 660 }
 661
 662 /*
 663  * omap_correct_data_bch - Compares the ecc read from nand spare area
 664  * with ECC registers values and corrects one bit error if it has occured
 665  *
 666  * @mtd:        MTD device structure
 667  * @dat:        page data
 668  * @read_ecc:   ecc read from nand flash (ignored)
 669  * @calc_ecc:   ecc read from ECC registers
 670  *
 671  * @return 0 if data is OK or corrected, else returns -1
 672  */
 673 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 674                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 675 {
 676         struct nand_chip *chip = mtd->priv;
 677         struct omap_nand_info *info = chip->priv;
 678         struct nand_ecc_ctrl *ecc = &chip->ecc;
 679         uint32_t error_count = 0, error_max;
 680         uint32_t error_loc[ELM_MAX_ERROR_COUNT];
 681         enum bch_level bch_type;
 682         uint32_t i, ecc_flag = 0;
 683         uint8_t count;
 684         uint32_t byte_pos, bit_pos;
 685         int err = 0;
 686
 687         /* check calculated ecc */
 688         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 689                 if (calc_ecc[i] != 0x00)
 690                         ecc_flag = 1;
 691         }
 692         if (!ecc_flag)
 693                 return 0;
 694
 695         /* check for whether its a erased-page */
 696         ecc_flag = 0;
 697         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 698                 if (read_ecc[i] != 0xff)
 699                         ecc_flag = 1;
 700         }
 701         if (!ecc_flag)
 702                 return 0;
 703
 704         /*
 705          * while reading ECC result we read it in big endian.
 706          * Hence while loading to ELM we have rotate to get the right endian.
 707          */
 708         switch (info->ecc_scheme) {
 709         case OMAP_ECC_BCH8_CODE_HW:
 710                 bch_type = BCH_8_BIT;
 711                 omap_reverse_list(calc_ecc, ecc->bytes - 1);
 712                 break;
 713         case OMAP_ECC_BCH16_CODE_HW:
 714                 bch_type = BCH_16_BIT;
 715                 omap_reverse_list(calc_ecc, ecc->bytes);
 716                 break;
 717         default:
 718                 return -EINVAL;
 719         }
 720         /* use elm module to check for errors */
 721         elm_config(bch_type);
 722         err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
 723         if (err)
 724                 return err;
 725
 726         /* correct bch error */
 727         for (count = 0; count < error_count; count++) {
 728                 switch (info->ecc_scheme) {
 729                 case OMAP_ECC_BCH8_CODE_HW:
 730                         /* 14th byte in ECC is reserved to match ROM layout */
 731                         error_max = SECTOR_BYTES + (ecc->bytes - 1);
 732                         break;
 733                 case OMAP_ECC_BCH16_CODE_HW:
 734                         error_max = SECTOR_BYTES + ecc->bytes;
 735                         break;
 736                 default:
 737                         return -EINVAL;
 738                 }
 739                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 740                 bit_pos  = error_loc[count] % 8;
 741                 if (byte_pos < SECTOR_BYTES) {
 742                         dat[byte_pos] ^= 1 << bit_pos;
 743                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 744                 } else if (byte_pos < error_max) {
 745                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 746                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 747                                                                 SECTOR_BYTES);
 748                 } else {
 749                         err = -EBADMSG;
 750                         printf("nand: error: invalid bit-flip location\n");
 751                 }
 752         }
 753         return (err) ? err : error_count;
 754 }
 755
 756 /**
 757  * omap_read_page_bch - hardware ecc based page read function
 758  * @mtd:        mtd info structure
 759  * @chip:       nand chip info structure
 760  * @buf:        buffer to store read data
 761  * @oob_required: caller expects OOB data read to chip->oob_poi
 762  * @page:       page number to read
 763  *
 764  */
 765 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 766                                 uint8_t *buf, int oob_required, int page)
 767 {
 768         int i, eccsize = chip->ecc.size;
 769         int eccbytes = chip->ecc.bytes;
 770         int eccsteps = chip->ecc.steps;
 771         uint8_t *p = buf;
 772         uint8_t *ecc_calc = chip->buffers->ecccalc;
 773         uint8_t *ecc_code = chip->buffers->ecccode;
 774         uint32_t *eccpos = chip->ecc.layout->eccpos;
 775         uint8_t *oob = &chip->oob_poi[eccpos[0]];
 776         uint32_t data_pos;
 777         uint32_t oob_pos;
 778
 779         data_pos = 0;
 780         /* oob area start */
 781         oob_pos = (eccsize * eccsteps) + eccpos[0];
 782
 783         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 784                                 oob += eccbytes) {
 785                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 786                 /* read data */
 787                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
 788                 chip->read_buf(mtd, p, eccsize);
 789
 790                 /* read respective ecc from oob area */
 791                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
 792                 chip->read_buf(mtd, oob, eccbytes);
 793                 /* read syndrome */
 794                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 795
 796                 if (oob_required) {
 797                         /* reread the OOB area to get the metadata */
 798                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, page);
 799                         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 800                 }
 801
 802                 data_pos += eccsize;
 803                 oob_pos += eccbytes;
 804         }
 805
 806         for (i = 0; i < chip->ecc.total; i++)
 807                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 808
 809         eccsteps = chip->ecc.steps;
 810         p = buf;
 811
 812         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 813                 int stat;
 814
 815                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 816                 if (stat < 0)
 817                         mtd->ecc_stats.failed++;
 818                 else
 819                         mtd->ecc_stats.corrected += stat;
 820         }
 821         return 0;
 822 }
 823 #endif /* CONFIG_NAND_OMAP_ELM */
 824
 825 /*
 826  * OMAP3 BCH8 support (with BCH library)
 827  */
 828 #ifdef CONFIG_BCH
 829 /**
 830  * omap_correct_data_bch_sw - Decode received data and correct errors
 831  * @mtd: MTD device structure
 832  * @data: page data
 833  * @read_ecc: ecc read from nand flash
 834  * @calc_ecc: ecc read from HW ECC registers
 835  */
 836 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 837                                  u_char *read_ecc, u_char *calc_ecc)
 838 {
 839         int i, count;
 840         /* cannot correct more than 8 errors */
 841         unsigned int errloc[8];
 842         struct nand_chip *chip = mtd->priv;
 843         struct omap_nand_info *info = chip->priv;
 844
 845         count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 846                                                         NULL, errloc);
 847         if (count > 0) {
 848                 /* correct errors */
 849                 for (i = 0; i < count; i++) {
 850                         /* correct data only, not ecc bytes */
 851                         if (errloc[i] < 8*512)
 852                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 853                         printf("corrected bitflip %u\n", errloc[i]);
 854 #ifdef DEBUG
 855                         printf("read_ecc: ");
 856                         /*
 857                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 858                          * here!
 859                          */
 860                         for (i = 0; i < 13; i++)
 861                                 printf("%02x ", read_ecc[i]);
 862                         printf("\n");
 863                         printf("calc_ecc: ");
 864                         for (i = 0; i < 13; i++)
 865                                 printf("%02x ", calc_ecc[i]);
 866                         printf("\n");
 867 #endif
 868                 }
 869         } else if (count < 0) {
 870                 printf("ecc unrecoverable error\n");
 871         }
 872         return count;
 873 }
 874
 875 /**
 876  * omap_free_bch - Release BCH ecc resources
 877  * @mtd: MTD device structure
 878  */
 879 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 880 {
 881         struct nand_chip *chip = mtd->priv;
 882         struct omap_nand_info *info = chip->priv;
 883
 884         if (info->control) {
 885                 free_bch(info->control);
 886                 info->control = NULL;
 887         }
 888 }
 889 #endif /* CONFIG_BCH */
 890
 891 /**
 892  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 893  * @nand: NAND chip device structure
 894  * @ecc_scheme: ecc scheme to configure
 895  * @pagesize: number of main-area bytes per page of NAND device
 896  * @oobsize: number of OOB/spare bytes per page of NAND device
 897  */
 898 static int omap_select_ecc_scheme(struct nand_chip *nand,
 899         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 900         struct omap_nand_info   *info           = nand->priv;
 901         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 902         int eccsteps = pagesize / SECTOR_BYTES;
 903         int i;
 904
 905         switch (ecc_scheme) {
 906         case OMAP_ECC_HAM1_CODE_SW:
 907                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 908                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 909                  * initialized in nand_scan_tail(), so just set ecc.mode */
 910                 info->control           = NULL;
 911                 nand->ecc.mode          = NAND_ECC_SOFT;
 912                 nand->ecc.layout        = NULL;
 913                 nand->ecc.size          = 0;
 914                 break;
 915
 916         case OMAP_ECC_HAM1_CODE_HW:
 917                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 918                 /* check ecc-scheme requirements before updating ecc info */
 919                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 920                         printf("nand: error: insufficient OOB: require=%d\n", (
 921                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 922                         return -EINVAL;
 923                 }
 924                 info->control           = NULL;
 925                 /* populate ecc specific fields */
 926                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 927                 nand->ecc.mode          = NAND_ECC_HW;
 928                 nand->ecc.strength      = 1;
 929                 nand->ecc.size          = SECTOR_BYTES;
 930                 nand->ecc.bytes         = 3;
 931                 nand->ecc.hwctl         = omap_enable_hwecc;
 932                 nand->ecc.correct       = omap_correct_data;
 933                 nand->ecc.calculate     = omap_calculate_ecc;
 934                 /* define ecc-layout */
 935                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 936                 for (i = 0; i < ecclayout->eccbytes; i++) {
 937                         if (nand->options & NAND_BUSWIDTH_16)
 938                                 ecclayout->eccpos[i] = i + 2;
 939                         else
 940                                 ecclayout->eccpos[i] = i + 1;
 941                 }
 942                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 943                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 944                                                 BADBLOCK_MARKER_LENGTH;
 945                 break;
 946
 947         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 948 #ifdef CONFIG_BCH
 949                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 950                 /* check ecc-scheme requirements before updating ecc info */
 951                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 952                         printf("nand: error: insufficient OOB: require=%d\n", (
 953                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 954                         return -EINVAL;
 955                 }
 956                 /* check if BCH S/W library can be used for error detection */
 957                 info->control = init_bch(13, 8, 0x201b);
 958                 if (!info->control) {
 959                         printf("nand: error: could not init_bch()\n");
 960                         return -ENODEV;
 961                 }
 962                 /* populate ecc specific fields */
 963                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 964                 nand->ecc.mode          = NAND_ECC_HW;
 965                 nand->ecc.strength      = 8;
 966                 nand->ecc.size          = SECTOR_BYTES;
 967                 nand->ecc.bytes         = 13;
 968                 nand->ecc.hwctl         = omap_enable_hwecc;
 969                 nand->ecc.correct       = omap_correct_data_bch_sw;
 970                 nand->ecc.calculate     = omap_calculate_ecc;
 971                 /* define ecc-layout */
 972                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 973                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 974                 for (i = 1; i < ecclayout->eccbytes; i++) {
 975                         if (i % nand->ecc.bytes)
 976                                 ecclayout->eccpos[i] =
 977                                                 ecclayout->eccpos[i - 1] + 1;
 978                         else
 979                                 ecclayout->eccpos[i] =
 980                                                 ecclayout->eccpos[i - 1] + 2;
 981                 }
 982                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 983                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 984                                                 BADBLOCK_MARKER_LENGTH;
 985                 break;
 986 #else
 987                 printf("nand: error: CONFIG_BCH required for ECC\n");
 988                 return -EINVAL;
 989 #endif
 990
 991         case OMAP_ECC_BCH8_CODE_HW:
 992 #ifdef CONFIG_NAND_OMAP_ELM
 993                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 994                 /* check ecc-scheme requirements before updating ecc info */
 995                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 996                         printf("nand: error: insufficient OOB: require=%d\n", (
 997                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 998                         return -EINVAL;
 999                 }
1000                 /* intialize ELM for ECC error detection */
1001                 elm_init();
1002                 info->control           = NULL;
1003                 /* populate ecc specific fields */
1004                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
1005                 nand->ecc.mode          = NAND_ECC_HW;
1006                 nand->ecc.strength      = 8;
1007                 nand->ecc.size          = SECTOR_BYTES;
1008                 nand->ecc.bytes         = 14;
1009                 nand->ecc.hwctl         = omap_enable_hwecc;
1010                 nand->ecc.correct       = omap_correct_data_bch;
1011                 nand->ecc.calculate     = omap_calculate_ecc;
1012                 nand->ecc.read_page     = omap_read_page_bch;
1013                 /* define ecc-layout */
1014                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
1015                 for (i = 0; i < ecclayout->eccbytes; i++)
1016                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
1017                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
1018                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
1019                                                 BADBLOCK_MARKER_LENGTH;
1020                 break;
1021 #else
1022                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
1023                 return -EINVAL;
1024 #endif
1025
1026         case OMAP_ECC_BCH16_CODE_HW:
1027 #ifdef CONFIG_NAND_OMAP_ELM
1028                 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
1029                 /* check ecc-scheme requirements before updating ecc info */
1030                 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
1031                         printf("nand: error: insufficient OOB: require=%d\n", (
1032                                 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
1033                         return -EINVAL;
1034                 }
1035                 /* intialize ELM for ECC error detection */
1036                 elm_init();
1037                 /* populate ecc specific fields */
1038                 nand->ecc.mode          = NAND_ECC_HW;
1039                 nand->ecc.size          = SECTOR_BYTES;
1040                 nand->ecc.bytes         = 26;
1041                 nand->ecc.strength      = 16;
1042                 nand->ecc.hwctl         = omap_enable_hwecc;
1043                 nand->ecc.correct       = omap_correct_data_bch;
1044                 nand->ecc.calculate     = omap_calculate_ecc;
1045                 nand->ecc.read_page     = omap_read_page_bch;
1046                 /* define ecc-layout */
1047                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
1048                 for (i = 0; i < ecclayout->eccbytes; i++)
1049                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
1050                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
1051                 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
1052                                                 BADBLOCK_MARKER_LENGTH;
1053                 break;
1054 #else
1055                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
1056                 return -EINVAL;
1057 #endif
1058         default:
1059                 debug("nand: error: ecc scheme not enabled or supported\n");
1060                 return -EINVAL;
1061         }
1062
1063         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
1064         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
1065                 nand->ecc.layout = ecclayout;
1066
1067         info->ecc_scheme = ecc_scheme;
1068         return 0;
1069 }
1070
1071 #ifndef CONFIG_SPL_BUILD
1072 /*
1073  * omap_nand_switch_ecc - switch the ECC operation between different engines
1074  * (h/w and s/w) and different algorithms (hamming and BCHx)
1075  *
1076  * @hardware            - true if one of the HW engines should be used
1077  * @eccstrength         - the number of bits that could be corrected
1078  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
1079  */
1080 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
1081 {
1082         struct nand_chip *nand;
1083         struct mtd_info *mtd;
1084         int err = 0;
1085
1086         if (nand_curr_device < 0 ||
1087             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
1088             !nand_info[nand_curr_device].name) {
1089                 printf("nand: error: no NAND devices found\n");
1090                 return -ENODEV;
1091         }
1092
1093         mtd = &nand_info[nand_curr_device];
1094         nand = mtd->priv;
1095         nand->options |= NAND_OWN_BUFFERS;
1096         nand->options &= ~NAND_SUBPAGE_READ;
1097         /* Setup the ecc configurations again */
1098         if (hardware) {
1099                 if (eccstrength == 1) {
1100                         err = omap_select_ecc_scheme(nand,
1101                                         OMAP_ECC_HAM1_CODE_HW,
1102                                         mtd->writesize, mtd->oobsize);
1103                 } else if (eccstrength == 8) {
1104                         err = omap_select_ecc_scheme(nand,
1105                                         OMAP_ECC_BCH8_CODE_HW,
1106                                         mtd->writesize, mtd->oobsize);
1107                 } else {
1108                         printf("nand: error: unsupported ECC scheme\n");
1109                         return -EINVAL;
1110                 }
1111         } else {
1112                 if (eccstrength == 1) {
1113                         err = omap_select_ecc_scheme(nand,
1114                                         OMAP_ECC_HAM1_CODE_SW,
1115                                         mtd->writesize, mtd->oobsize);
1116                 } else if (eccstrength == 8) {
1117                         err = omap_select_ecc_scheme(nand,
1118                                         OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
1119                                         mtd->writesize, mtd->oobsize);
1120                 } else {
1121                         printf("nand: error: unsupported ECC scheme\n");
1122                         return -EINVAL;
1123                 }
1124         }
1125
1126         /* Update NAND handling after ECC mode switch */
1127         if (!err)
1128                 err = nand_scan_tail(mtd);
1129         return err;
1130 }
1131 #endif /* CONFIG_SPL_BUILD */
1132
1133 /*
1134  * Board-specific NAND initialization. The following members of the
1135  * argument are board-specific:
1136  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
1137  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
1138  * - cmd_ctrl: hardwarespecific function for accesing control-lines
1139  * - waitfunc: hardwarespecific function for accesing device ready/busy line
1140  * - ecc.hwctl: function to enable (reset) hardware ecc generator
1141  * - ecc.mode: mode of ecc, see defines
1142  * - chip_delay: chip dependent delay for transfering data from array to
1143  *   read regs (tR)
1144  * - options: various chip options. They can partly be set to inform
1145  *   nand_scan about special functionality. See the defines for further
1146  *   explanation
1147  */
1148 int board_nand_init(struct nand_chip *nand)
1149 {
1150         int32_t gpmc_config = 0;
1151         int cs = cs_next++;
1152         int err = 0;
1153         /*
1154          * xloader/Uboot's gpmc configuration would have configured GPMC for
1155          * nand type of memory. The following logic scans and latches on to the
1156          * first CS with NAND type memory.
1157          * TBD: need to make this logic generic to handle multiple CS NAND
1158          * devices.
1159          */
1160         while (cs < GPMC_MAX_CS) {
1161                 /* Check if NAND type is set */
1162                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
1163                         /* Found it!! */
1164                         break;
1165                 }
1166                 cs++;
1167         }
1168         if (cs >= GPMC_MAX_CS) {
1169                 printf("nand: error: Unable to find NAND settings in "
1170                         "GPMC Configuration - quitting\n");
1171                 return -ENODEV;
1172         }
1173
1174         gpmc_config = readl(&gpmc_cfg->config);
1175         /* Disable Write protect */
1176         gpmc_config |= 0x10;
1177         writel(gpmc_config, &gpmc_cfg->config);
1178
1179         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
1180         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
1181         omap_nand_info[cs].control = NULL;
1182         omap_nand_info[cs].cs = cs;
1183         omap_nand_info[cs].ws = wscfg[cs];
1184         nand->priv      = &omap_nand_info[cs];
1185         nand->cmd_ctrl  = omap_nand_hwcontrol;
1186         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
1187         nand->chip_delay = 100;
1188         nand->ecc.layout = &omap_ecclayout;
1189
1190         /* configure driver and controller based on NAND device bus-width */
1191         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
1192 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
1193         nand->options |= NAND_BUSWIDTH_16;
1194         writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
1195 #else
1196         nand->options &= ~NAND_BUSWIDTH_16;
1197         writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
1198 #endif
1199         /* select ECC scheme */
1200 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
1201         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
1202                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
1203 #else
1204         /* pagesize and oobsize are not required to configure sw ecc-scheme */
1205         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
1206                         0, 0);
1207 #endif
1208         if (err)
1209                 return err;
1210 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1211         if (nand->ecc.layout) {
1212                 bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
1213                 bbt_main_descr.veroffs = bbt_main_descr.offs +
1214                         sizeof(bbt_pattern);
1215
1216                 bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
1217                 bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
1218                         sizeof(mirror_pattern);
1219         }
1220
1221         nand->bbt_options |= NAND_BBT_USE_FLASH;
1222         nand->bbt_td = &bbt_main_descr;
1223         nand->bbt_md = &bbt_mirror_descr;
1224 #endif
1225
1226 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
1227         nand->read_buf = omap_nand_read_prefetch;
1228 #else
1229         if (nand->options & NAND_BUSWIDTH_16)
1230                 nand->read_buf = nand_read_buf16;
1231         else
1232                 nand->read_buf = nand_read_buf;
1233 #endif
1234
1235         nand->dev_ready = omap_dev_ready;
1236
1237         return 0;
1238 }