2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/mem.h>
12 #include <linux/mtd/omap_gpmc.h>
13 #include <linux/mtd/nand_ecc.h>
14 #include <linux/bch.h>
15 #include <linux/compiler.h>
17 #include <linux/mtd/omap_elm.h>
19 #define BADBLOCK_MARKER_LENGTH 2
20 #define SECTOR_BYTES 512
21 #define ECCCLEAR (0x1 << 8)
22 #define ECCRESULTREG1 (0x1 << 0)
23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
24 #define BCH4_BIT_PAD 4
27 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
28 0x97, 0x79, 0xe5, 0x24, 0xb5};
30 static uint8_t cs_next;
31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
34 * Driver configurations
36 struct omap_nand_info {
37 struct bch_control *control;
38 enum omap_ecc ecc_scheme;
42 /* We are wasting a bit of memory but al least we are safe */
43 static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
45 static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE;
47 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
48 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
49 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
51 static struct nand_bbt_descr bbt_main_descr = {
52 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
53 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
54 .offs = 0, /* may be overwritten depending on ECC layout */
56 .veroffs = 4, /* may be overwritten depending on ECC layout */
58 .pattern = bbt_pattern,
61 static struct nand_bbt_descr bbt_mirror_descr = {
62 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
63 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
64 .offs = 0, /* may be overwritten depending on ECC layout */
66 .veroffs = 4, /* may be overwritten depending on ECC layout */
68 .pattern = mirror_pattern,
72 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
73 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
75 #define PREFETCH_ENABLEOPTIMIZEDACCESS (0x1 << 27)
77 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) (((val) >> 24) & 0x7F)
78 #define GPMC_PREFETCH_STATUS_COUNT(val) ((val) & 0x00003fff)
80 #define CS_NUM_SHIFT 24
81 #define ENABLE_PREFETCH (0x1 << 7)
82 #define DMA_MPU_MODE 2
84 #define OMAP_NAND_TIMEOUT_MS 5000
86 #define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
88 #ifdef CONFIG_SYS_GPMC_PREFETCH_ENABLE
90 * gpmc_prefetch_enable - configures and starts prefetch transfer
91 * @cs: cs (chip select) number
92 * @fifo_th: fifo threshold to be used for read/ write
93 * @count: number of bytes to be transferred
94 * @is_write: prefetch read(0) or write post(1) mode
96 static inline void gpmc_prefetch_enable(int cs, int fifo_th,
97 unsigned int count, int is_write)
99 writel(count, &gpmc_cfg->pref_config2);
101 /* Set the prefetch read / post write and enable the engine.
102 * Set which cs is has requested for.
104 uint32_t val = (cs << CS_NUM_SHIFT) |
105 PREFETCH_ENABLEOPTIMIZEDACCESS |
106 PREFETCH_FIFOTHRESHOLD(fifo_th) |
109 writel(val, &gpmc_cfg->pref_config1);
111 /* Start the prefetch engine */
112 writel(0x1, &gpmc_cfg->pref_control);
116 * gpmc_prefetch_reset - disables and stops the prefetch engine
118 static inline void gpmc_prefetch_reset(void)
120 /* Stop the PFPW engine */
121 writel(0x0, &gpmc_cfg->pref_control);
123 /* Reset/disable the PFPW engine */
124 writel(0x0, &gpmc_cfg->pref_config1);
127 //#define FIFO_IOADDR (nand->IO_ADDR_R)
128 #define FIFO_IOADDR PISMO1_NAND_BASE
131 * read_buf_pref - read data from NAND controller into buffer
132 * @mtd: MTD device structure
133 * @buf: buffer to store date
134 * @len: number of bytes to read
136 static void read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
138 gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 0);
140 // Get number of bytes waiting in the FIFO
141 uint32_t read_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
145 // Alignment of Destination Buffer
146 while (read_bytes && ((unsigned int)buf & 3)) {
147 *buf++ = readb(FIFO_IOADDR);
151 // Use maximum word size (32bit) inside this loop, because speed is limited by
152 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
153 len -= read_bytes & ~3;
154 while (read_bytes >= 4) {
155 *((uint32_t*)buf) = readl(FIFO_IOADDR);
159 // Transfer the last (non-aligned) bytes only at the last iteration,
160 // to maintain full speed up to the end of the transfer.
161 if (read_bytes == len) {
163 *buf++ = readb(FIFO_IOADDR);
169 gpmc_prefetch_reset();
173 * write_buf_pref - write buffer to NAND controller
174 * @mtd: MTD device structure
176 * @len: number of bytes to write
178 static void write_buf_pref(struct mtd_info *mtd, const u_char *buf, int len)
180 /* configure and start prefetch transfer */
181 gpmc_prefetch_enable(cs, PREFETCH_FIFOTHRESHOLD_MAX, len, 1);
184 // Get number of free bytes in the FIFO
185 uint32_t write_bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(readl(&gpmc_cfg->pref_status));
187 // don't write more bytes than requested
188 if (write_bytes > len)
191 // Alignment of Source Buffer
192 while (write_bytes && ((unsigned int)buf & 3)) {
193 writeb(*buf++, FIFO_IOADDR);
198 // Use maximum word size (32bit) inside this loop, because speed is limited by
199 // GPMC bus arbitration with a maximum transfer rate of 3.000.000/sec.
200 len -= write_bytes & ~3;
201 while (write_bytes >= 4) {
202 writel(*((uint32_t*)buf), FIFO_IOADDR);
207 // Transfer the last (non-aligned) bytes only at the last iteration,
208 // to maintain full speed up to the end of the transfer.
209 if (write_bytes == len) {
210 while (write_bytes) {
211 writeb(*buf++, FIFO_IOADDR);
218 /* wait for data to be flushed out before resetting the prefetch */
219 while ((len = GPMC_PREFETCH_STATUS_COUNT(readl(&gpmc_cfg->pref_status)))) {
220 debug("%u bytes still in FIFO\n", PREFETCH_FIFOTHRESHOLD_MAX - len);
224 /* disable and stop the PFPW engine */
225 gpmc_prefetch_reset();
227 #endif /* CONFIG_SYS_GPMC_PREFETCH_ENABLE */
230 * omap_nand_hwcontrol - Set the address pointers corretly for the
231 * following address/data/command operation
233 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
236 register struct nand_chip *this = mtd->priv;
237 struct omap_nand_info *info = this->priv;
241 * Point the IO_ADDR to DATA and ADDRESS registers instead
245 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
246 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
248 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
249 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
251 case NAND_CTRL_CHANGE | NAND_NCE:
252 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
256 if (cmd != NAND_CMD_NONE)
257 writeb(cmd, this->IO_ADDR_W);
260 /* Check wait pin as dev ready indicator */
261 static int omap_dev_ready(struct mtd_info *mtd)
263 return readl(&gpmc_cfg->status) & (1 << 8);
267 * gen_true_ecc - This function will generate true ECC value, which
268 * can be used when correcting data read from NAND flash memory core
270 * @ecc_buf: buffer to store ecc code
272 * @return: re-formatted ECC value
274 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
276 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
277 ((ecc_buf[2] & 0x0F) << 8);
281 * omap_correct_data - Compares the ecc read from nand spare area with ECC
282 * registers values and corrects one bit error if it has occured
283 * Further details can be had from OMAP TRM and the following selected links:
284 * http://en.wikipedia.org/wiki/Hamming_code
285 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
287 * @mtd: MTD device structure
289 * @read_ecc: ecc read from nand flash
290 * @calc_ecc: ecc read from ECC registers
292 * @return 0 if data is OK or corrected, else returns -1
294 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
295 uint8_t *read_ecc, uint8_t *calc_ecc)
297 uint32_t orig_ecc, new_ecc, res, hm;
298 uint16_t parity_bits, byte;
301 /* Regenerate the orginal ECC */
302 orig_ecc = gen_true_ecc(read_ecc);
303 new_ecc = gen_true_ecc(calc_ecc);
304 /* Get the XOR of real ecc */
305 res = orig_ecc ^ new_ecc;
307 /* Get the hamming width */
309 /* Single bit errors can be corrected! */
311 /* Correctable data! */
312 parity_bits = res >> 16;
313 bit = (parity_bits & 0x7);
314 byte = (parity_bits >> 3) & 0x1FF;
315 /* Flip the bit to correct */
316 dat[byte] ^= (0x1 << bit);
317 } else if (hm == 1) {
318 printf("Error: Ecc is wrong\n");
319 /* ECC itself is corrupted */
323 * hm distance != parity pairs OR one, could mean 2 bit
324 * error OR potentially be on a blank page..
325 * orig_ecc: contains spare area data from nand flash.
326 * new_ecc: generated ecc while reading data area.
327 * Note: if the ecc = 0, all data bits from which it was
328 * generated are 0xFF.
329 * The 3 byte(24 bits) ecc is generated per 512byte
330 * chunk of a page. If orig_ecc(from spare area)
331 * is 0xFF && new_ecc(computed now from data area)=0x0,
332 * this means that data area is 0xFF and spare area is
333 * 0xFF. A sure sign of a erased page!
335 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
337 printf("Error: Bad compare! failed\n");
338 /* detected 2 bit error */
346 * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
347 * @mtd: MTD device structure
348 * @mode: Read/Write mode
351 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
353 struct nand_chip *nand = mtd->priv;
354 struct omap_nand_info *info = nand->priv;
355 unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
356 unsigned int ecc_algo = 0;
357 unsigned int bch_type = 0;
358 unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
359 u32 ecc_size_config_val = 0;
360 u32 ecc_config_val = 0;
363 /* configure GPMC for specific ecc-scheme */
364 switch (info->ecc_scheme) {
365 case OMAP_ECC_HAM1_CODE_SW:
367 case OMAP_ECC_HAM1_CODE_HW:
374 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
375 case OMAP_ECC_BCH8_CODE_HW:
378 if (mode == NAND_ECC_WRITE) {
380 eccsize0 = 0; /* extra bits in nibbles per sector */
381 eccsize1 = 28; /* OOB bits in nibbles per sector */
384 eccsize0 = 26; /* ECC bits in nibbles per sector */
385 eccsize1 = 2; /* non-ECC bits in nibbles per sector */
388 case OMAP_ECC_BCH16_CODE_HW:
391 if (mode == NAND_ECC_WRITE) {
393 eccsize0 = 0; /* extra bits in nibbles per sector */
394 eccsize1 = 52; /* OOB bits in nibbles per sector */
397 eccsize0 = 52; /* ECC bits in nibbles per sector */
398 eccsize1 = 0; /* non-ECC bits in nibbles per sector */
404 /* Clear ecc and enable bits */
405 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
406 /* Configure ecc size for BCH */
407 ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
408 writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
410 /* Configure device details for BCH engine */
411 ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */
412 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
413 (bch_wrapmode << 8) | /* wrap mode */
414 (dev_width << 7) | /* bus width */
415 (0x0 << 4) | /* number of sectors */
416 (cs << 1) | /* ECC CS */
417 (0x1)); /* enable ECC */
418 writel(ecc_config_val, &gpmc_cfg->ecc_config);
422 * omap_calculate_ecc - Read ECC result
423 * @mtd: MTD structure
425 * @ecc_code: ecc_code buffer
426 * Using noninverted ECC can be considered ugly since writing a blank
427 * page ie. padding will clear the ECC bytes. This is no problem as
428 * long nobody is trying to write data on the seemingly unused page.
429 * Reading an erased page will produce an ECC mismatch between
430 * generated and read ECC bytes that has to be dealt with separately.
431 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
432 * is used, the result of read will be 0x0 while the ECC offsets of the
433 * spare area will be 0xFF which will result in an ECC mismatch.
435 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
438 struct nand_chip *chip = mtd->priv;
439 struct omap_nand_info *info = chip->priv;
440 uint32_t *ptr, val = 0;
443 switch (info->ecc_scheme) {
444 case OMAP_ECC_HAM1_CODE_HW:
445 val = readl(&gpmc_cfg->ecc1_result);
446 ecc_code[0] = val & 0xFF;
447 ecc_code[1] = (val >> 16) & 0xFF;
448 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
451 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
453 case OMAP_ECC_BCH8_CODE_HW:
454 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
456 ecc_code[i++] = (val >> 0) & 0xFF;
458 for (j = 0; j < 3; j++) {
460 ecc_code[i++] = (val >> 24) & 0xFF;
461 ecc_code[i++] = (val >> 16) & 0xFF;
462 ecc_code[i++] = (val >> 8) & 0xFF;
463 ecc_code[i++] = (val >> 0) & 0xFF;
467 case OMAP_ECC_BCH16_CODE_HW:
468 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
469 ecc_code[i++] = (val >> 8) & 0xFF;
470 ecc_code[i++] = (val >> 0) & 0xFF;
471 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
472 ecc_code[i++] = (val >> 24) & 0xFF;
473 ecc_code[i++] = (val >> 16) & 0xFF;
474 ecc_code[i++] = (val >> 8) & 0xFF;
475 ecc_code[i++] = (val >> 0) & 0xFF;
476 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
477 ecc_code[i++] = (val >> 24) & 0xFF;
478 ecc_code[i++] = (val >> 16) & 0xFF;
479 ecc_code[i++] = (val >> 8) & 0xFF;
480 ecc_code[i++] = (val >> 0) & 0xFF;
481 for (j = 3; j >= 0; j--) {
482 val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
484 ecc_code[i++] = (val >> 24) & 0xFF;
485 ecc_code[i++] = (val >> 16) & 0xFF;
486 ecc_code[i++] = (val >> 8) & 0xFF;
487 ecc_code[i++] = (val >> 0) & 0xFF;
493 /* ECC scheme specific syndrome customizations */
494 switch (info->ecc_scheme) {
495 case OMAP_ECC_HAM1_CODE_HW:
498 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
500 for (i = 0; i < chip->ecc.bytes; i++)
501 *(ecc_code + i) = *(ecc_code + i) ^
505 case OMAP_ECC_BCH8_CODE_HW:
506 ecc_code[chip->ecc.bytes - 1] = 0x00;
508 case OMAP_ECC_BCH16_CODE_HW:
516 #ifdef CONFIG_NAND_OMAP_ELM
518 * omap_reverse_list - re-orders list elements in reverse order [internal]
519 * @list: pointer to start of list
520 * @length: length of list
522 static void omap_reverse_list(u8 *list, unsigned int length)
525 unsigned int half_length = length / 2;
527 for (i = 0, j = length - 1; i < half_length; i++, j--) {
535 * omap_correct_data_bch - Compares the ecc read from nand spare area
536 * with ECC registers values and corrects one bit error if it has occured
538 * @mtd: MTD device structure
540 * @read_ecc: ecc read from nand flash (ignored)
541 * @calc_ecc: ecc read from ECC registers
543 * @return 0 if data is OK or corrected, else returns -1
545 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
546 uint8_t *read_ecc, uint8_t *calc_ecc)
548 struct nand_chip *chip = mtd->priv;
549 struct omap_nand_info *info = chip->priv;
550 struct nand_ecc_ctrl *ecc = &chip->ecc;
551 uint32_t error_count = 0, error_max;
552 uint32_t error_loc[ELM_MAX_ERROR_COUNT];
553 enum bch_level bch_type;
554 uint32_t i, ecc_flag = 0;
556 uint32_t byte_pos, bit_pos;
559 /* check calculated ecc */
560 for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
561 if (calc_ecc[i] != 0x00)
567 /* check for whether its a erased-page */
569 for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
570 if (read_ecc[i] != 0xff)
577 * while reading ECC result we read it in big endian.
578 * Hence while loading to ELM we have rotate to get the right endian.
580 switch (info->ecc_scheme) {
581 case OMAP_ECC_BCH8_CODE_HW:
582 bch_type = BCH_8_BIT;
583 omap_reverse_list(calc_ecc, ecc->bytes - 1);
585 case OMAP_ECC_BCH16_CODE_HW:
586 bch_type = BCH_16_BIT;
587 omap_reverse_list(calc_ecc, ecc->bytes);
592 /* use elm module to check for errors */
593 elm_config(bch_type);
594 err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
598 /* correct bch error */
599 for (count = 0; count < error_count; count++) {
600 switch (info->ecc_scheme) {
601 case OMAP_ECC_BCH8_CODE_HW:
602 /* 14th byte in ECC is reserved to match ROM layout */
603 error_max = SECTOR_BYTES + (ecc->bytes - 1);
605 case OMAP_ECC_BCH16_CODE_HW:
606 error_max = SECTOR_BYTES + ecc->bytes;
611 byte_pos = error_max - (error_loc[count] / 8) - 1;
612 bit_pos = error_loc[count] % 8;
613 if (byte_pos < SECTOR_BYTES) {
614 dat[byte_pos] ^= 1 << bit_pos;
615 printf("nand: bit-flip corrected @data=%d\n", byte_pos);
616 } else if (byte_pos < error_max) {
617 read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
618 printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
622 printf("nand: error: invalid bit-flip location\n");
625 return (err) ? err : error_count;
629 * omap_read_page_bch - hardware ecc based page read function
630 * @mtd: mtd info structure
631 * @chip: nand chip info structure
632 * @buf: buffer to store read data
633 * @oob_required: caller expects OOB data read to chip->oob_poi
634 * @page: page number to read
637 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
638 uint8_t *buf, int oob_required, int page)
640 int i, eccsize = chip->ecc.size;
641 int eccbytes = chip->ecc.bytes;
642 int eccsteps = chip->ecc.steps;
644 uint8_t *ecc_calc = chip->buffers->ecccalc;
645 uint8_t *ecc_code = chip->buffers->ecccode;
646 uint32_t *eccpos = chip->ecc.layout->eccpos;
647 uint8_t *oob = &chip->oob_poi[eccpos[0]];
653 oob_pos = (eccsize * eccsteps) + eccpos[0];
655 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
657 chip->ecc.hwctl(mtd, NAND_ECC_READ);
659 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
660 chip->read_buf(mtd, p, eccsize);
662 /* read respective ecc from oob area */
663 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
664 chip->read_buf(mtd, oob, eccbytes);
666 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
672 for (i = 0; i < chip->ecc.total; i++)
673 ecc_code[i] = chip->oob_poi[eccpos[i]];
675 eccsteps = chip->ecc.steps;
678 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
681 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
683 mtd->ecc_stats.failed++;
685 mtd->ecc_stats.corrected += stat;
689 #endif /* CONFIG_NAND_OMAP_ELM */
692 * OMAP3 BCH8 support (with BCH library)
696 * omap_correct_data_bch_sw - Decode received data and correct errors
697 * @mtd: MTD device structure
699 * @read_ecc: ecc read from nand flash
700 * @calc_ecc: ecc read from HW ECC registers
702 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
703 u_char *read_ecc, u_char *calc_ecc)
706 /* cannot correct more than 8 errors */
707 unsigned int errloc[8];
708 struct nand_chip *chip = mtd->priv;
709 struct omap_nand_info *info = chip->priv;
711 count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
715 for (i = 0; i < count; i++) {
716 /* correct data only, not ecc bytes */
717 if (errloc[i] < 8*512)
718 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
719 printf("corrected bitflip %u\n", errloc[i]);
721 printf("read_ecc: ");
723 * BCH8 have 13 bytes of ECC; BCH4 needs adoption
726 for (i = 0; i < 13; i++)
727 printf("%02x ", read_ecc[i]);
729 printf("calc_ecc: ");
730 for (i = 0; i < 13; i++)
731 printf("%02x ", calc_ecc[i]);
735 } else if (count < 0) {
736 printf("ecc unrecoverable error\n");
742 * omap_free_bch - Release BCH ecc resources
743 * @mtd: MTD device structure
745 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
747 struct nand_chip *chip = mtd->priv;
748 struct omap_nand_info *info = chip->priv;
751 free_bch(info->control);
752 info->control = NULL;
755 #endif /* CONFIG_BCH */
758 * omap_select_ecc_scheme - configures driver for particular ecc-scheme
759 * @nand: NAND chip device structure
760 * @ecc_scheme: ecc scheme to configure
761 * @pagesize: number of main-area bytes per page of NAND device
762 * @oobsize: number of OOB/spare bytes per page of NAND device
764 static int omap_select_ecc_scheme(struct nand_chip *nand,
765 enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
766 struct omap_nand_info *info = nand->priv;
767 struct nand_ecclayout *ecclayout = &omap_ecclayout;
768 int eccsteps = pagesize / SECTOR_BYTES;
771 switch (ecc_scheme) {
772 case OMAP_ECC_HAM1_CODE_SW:
773 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
774 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
775 * initialized in nand_scan_tail(), so just set ecc.mode */
776 info->control = NULL;
777 nand->ecc.mode = NAND_ECC_SOFT;
778 nand->ecc.layout = NULL;
782 case OMAP_ECC_HAM1_CODE_HW:
783 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
784 /* check ecc-scheme requirements before updating ecc info */
785 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
786 printf("nand: error: insufficient OOB: require=%d\n", (
787 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
790 info->control = NULL;
791 /* populate ecc specific fields */
792 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
793 nand->ecc.mode = NAND_ECC_HW;
794 nand->ecc.strength = 1;
795 nand->ecc.size = SECTOR_BYTES;
797 nand->ecc.hwctl = omap_enable_hwecc;
798 nand->ecc.correct = omap_correct_data;
799 nand->ecc.calculate = omap_calculate_ecc;
800 /* define ecc-layout */
801 ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
802 for (i = 0; i < ecclayout->eccbytes; i++) {
803 if (nand->options & NAND_BUSWIDTH_16)
804 ecclayout->eccpos[i] = i + 2;
806 ecclayout->eccpos[i] = i + 1;
808 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
809 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
810 BADBLOCK_MARKER_LENGTH;
813 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
815 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
816 /* check ecc-scheme requirements before updating ecc info */
817 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
818 printf("nand: error: insufficient OOB: require=%d\n", (
819 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
822 /* check if BCH S/W library can be used for error detection */
823 info->control = init_bch(13, 8, 0x201b);
824 if (!info->control) {
825 printf("nand: error: could not init_bch()\n");
828 /* populate ecc specific fields */
829 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
830 nand->ecc.mode = NAND_ECC_HW;
831 nand->ecc.strength = 8;
832 nand->ecc.size = SECTOR_BYTES;
833 nand->ecc.bytes = 13;
834 nand->ecc.hwctl = omap_enable_hwecc;
835 nand->ecc.correct = omap_correct_data_bch_sw;
836 nand->ecc.calculate = omap_calculate_ecc;
837 /* define ecc-layout */
838 ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
839 ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH;
840 for (i = 1; i < ecclayout->eccbytes; i++) {
841 if (i % nand->ecc.bytes)
842 ecclayout->eccpos[i] =
843 ecclayout->eccpos[i - 1] + 1;
845 ecclayout->eccpos[i] =
846 ecclayout->eccpos[i - 1] + 2;
848 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
849 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
850 BADBLOCK_MARKER_LENGTH;
853 printf("nand: error: CONFIG_BCH required for ECC\n");
857 case OMAP_ECC_BCH8_CODE_HW:
858 #ifdef CONFIG_NAND_OMAP_ELM
859 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
860 /* check ecc-scheme requirements before updating ecc info */
861 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
862 printf("nand: error: insufficient OOB: require=%d\n", (
863 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
866 /* intialize ELM for ECC error detection */
868 info->control = NULL;
869 /* populate ecc specific fields */
870 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
871 nand->ecc.mode = NAND_ECC_HW;
872 nand->ecc.strength = 8;
873 nand->ecc.size = SECTOR_BYTES;
874 nand->ecc.bytes = 14;
875 nand->ecc.hwctl = omap_enable_hwecc;
876 nand->ecc.correct = omap_correct_data_bch;
877 nand->ecc.calculate = omap_calculate_ecc;
878 nand->ecc.read_page = omap_read_page_bch;
879 /* define ecc-layout */
880 ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
881 for (i = 0; i < ecclayout->eccbytes; i++)
882 ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
883 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
884 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
885 BADBLOCK_MARKER_LENGTH;
888 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
892 case OMAP_ECC_BCH16_CODE_HW:
893 #ifdef CONFIG_NAND_OMAP_ELM
894 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
895 /* check ecc-scheme requirements before updating ecc info */
896 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
897 printf("nand: error: insufficient OOB: require=%d\n", (
898 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
901 /* intialize ELM for ECC error detection */
903 /* populate ecc specific fields */
904 nand->ecc.mode = NAND_ECC_HW;
905 nand->ecc.size = SECTOR_BYTES;
906 nand->ecc.bytes = 26;
907 nand->ecc.strength = 16;
908 nand->ecc.hwctl = omap_enable_hwecc;
909 nand->ecc.correct = omap_correct_data_bch;
910 nand->ecc.calculate = omap_calculate_ecc;
911 nand->ecc.read_page = omap_read_page_bch;
912 /* define ecc-layout */
913 ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
914 for (i = 0; i < ecclayout->eccbytes; i++)
915 ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
916 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
917 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
918 BADBLOCK_MARKER_LENGTH;
921 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
925 debug("nand: error: ecc scheme not enabled or supported\n");
929 /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
930 if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
931 nand->ecc.layout = ecclayout;
933 info->ecc_scheme = ecc_scheme;
937 #ifndef CONFIG_SPL_BUILD
939 * omap_nand_switch_ecc - switch the ECC operation between different engines
940 * (h/w and s/w) and different algorithms (hamming and BCHx)
942 * @hardware - true if one of the HW engines should be used
943 * @eccstrength - the number of bits that could be corrected
944 * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
946 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
948 struct nand_chip *nand;
949 struct mtd_info *mtd;
952 if (nand_curr_device < 0 ||
953 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
954 !nand_info[nand_curr_device].name) {
955 printf("nand: error: no NAND devices found\n");
959 mtd = &nand_info[nand_curr_device];
961 nand->options |= NAND_OWN_BUFFERS;
962 nand->options &= ~NAND_SUBPAGE_READ;
963 /* Setup the ecc configurations again */
965 if (eccstrength == 1) {
966 err = omap_select_ecc_scheme(nand,
967 OMAP_ECC_HAM1_CODE_HW,
968 mtd->writesize, mtd->oobsize);
969 } else if (eccstrength == 8) {
970 err = omap_select_ecc_scheme(nand,
971 OMAP_ECC_BCH8_CODE_HW,
972 mtd->writesize, mtd->oobsize);
974 printf("nand: error: unsupported ECC scheme\n");
978 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
979 mtd->writesize, mtd->oobsize);
982 /* Update NAND handling after ECC mode switch */
984 err = nand_scan_tail(mtd);
987 #endif /* CONFIG_SPL_BUILD */
990 * Board-specific NAND initialization. The following members of the
991 * argument are board-specific:
992 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
993 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
994 * - cmd_ctrl: hardwarespecific function for accesing control-lines
995 * - waitfunc: hardwarespecific function for accesing device ready/busy line
996 * - ecc.hwctl: function to enable (reset) hardware ecc generator
997 * - ecc.mode: mode of ecc, see defines
998 * - chip_delay: chip dependent delay for transfering data from array to
1000 * - options: various chip options. They can partly be set to inform
1001 * nand_scan about special functionality. See the defines for further
1004 int board_nand_init(struct nand_chip *nand)
1006 int32_t gpmc_config = 0;
1010 * xloader/Uboot's gpmc configuration would have configured GPMC for
1011 * nand type of memory. The following logic scans and latches on to the
1012 * first CS with NAND type memory.
1013 * TBD: need to make this logic generic to handle multiple CS NAND
1016 while (cs < GPMC_MAX_CS) {
1017 /* Check if NAND type is set */
1018 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
1024 if (cs >= GPMC_MAX_CS) {
1025 printf("nand: error: Unable to find NAND settings in "
1026 "GPMC Configuration - quitting\n");
1030 gpmc_config = readl(&gpmc_cfg->config);
1031 /* Disable Write protect */
1032 gpmc_config |= 0x10;
1033 writel(gpmc_config, &gpmc_cfg->config);
1035 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
1036 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
1037 omap_nand_info[cs].control = NULL;
1038 omap_nand_info[cs].cs = cs;
1039 nand->priv = &omap_nand_info[cs];
1040 nand->cmd_ctrl = omap_nand_hwcontrol;
1041 nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
1042 nand->chip_delay = 100;
1043 nand->ecc.layout = &omap_ecclayout;
1045 /* configure driver and controller based on NAND device bus-width */
1046 gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
1047 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
1048 nand->options |= NAND_BUSWIDTH_16;
1049 writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
1051 nand->options &= ~NAND_BUSWIDTH_16;
1052 writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
1054 /* select ECC scheme */
1055 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
1056 err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
1057 CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
1059 /* pagesize and oobsize are not required to configure sw ecc-scheme */
1060 err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
1065 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1066 if (nand->ecc.layout) {
1067 bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
1068 bbt_main_descr.veroffs = bbt_main_descr.offs +
1069 sizeof(bbt_pattern);
1071 bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
1072 bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
1073 sizeof(mirror_pattern);
1076 nand->bbt_options |= NAND_BBT_USE_FLASH;
1077 nand->bbt_td = &bbt_main_descr;
1078 nand->bbt_md = &bbt_mirror_descr;
1081 #ifdef CONFIG_SPL_BUILD
1082 if (nand->options & NAND_BUSWIDTH_16)
1083 nand->read_buf = nand_read_buf16;
1085 nand->read_buf = nand_read_buf;
1088 nand->dev_ready = omap_dev_ready;