drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/arch/mem.h>
  13 #include <linux/mtd/omap_gpmc.h>
  14 #include <linux/mtd/nand_ecc.h>
  15 #include <linux/bch.h>
  16 #include <linux/compiler.h>
  17 #include <nand.h>
  18 #include <linux/mtd/omap_elm.h>
  19
  20 #define BADBLOCK_MARKER_LENGTH  2
  21 #define SECTOR_BYTES            512
  22 #define ECCCLEAR                (0x1 << 8)
  23 #define ECCRESULTREG1           (0x1 << 0)
  24 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  25 #define BCH4_BIT_PAD            4
  26
  27 #ifdef CONFIG_BCH
  28 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  29                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  30 #endif
  31 static uint8_t cs_next;
  32 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  33
  34 #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
  35 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
  36         { CONFIG_NAND_OMAP_GPMC_WSCFG };
  37 #else
  38 /* wscfg is preset to zero since its a static variable */
  39 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
  40 #endif
  41
  42 /*
  43  * Driver configurations
  44  */
  45 struct omap_nand_info {
  46         struct bch_control *control;
  47         enum omap_ecc ecc_scheme;
  48         uint8_t cs;
  49         uint8_t ws;             /* wait status pin (0,1) */
  50 };
  51
  52 /* We are wasting a bit of memory but al least we are safe */
  53 static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
  54
  55 static struct gpmc __iomem *gpmc_cfg = (void __iomem *)GPMC_BASE;
  56
  57 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  58 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
  59 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
  60
  61 static struct nand_bbt_descr bbt_main_descr = {
  62         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  63                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  64         .offs = 0, /* may be overwritten depending on ECC layout */
  65         .len = 4,
  66         .veroffs = 4, /* may be overwritten depending on ECC layout */
  67         .maxblocks = 4,
  68         .pattern = bbt_pattern,
  69 };
  70
  71 static struct nand_bbt_descr bbt_mirror_descr = {
  72         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  73                 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  74         .offs = 0, /* may be overwritten depending on ECC layout */
  75         .len = 4,
  76         .veroffs = 4, /* may be overwritten depending on ECC layout */
  77         .maxblocks = 4,
  78         .pattern = mirror_pattern,
  79 };
  80 #endif
  81
  82 #define PREFETCH_FIFOTHRESHOLD_MAX              0x40
  83 #define PREFETCH_FIFOTHRESHOLD(val)             ((val) << 8)
  84
  85 #define PREFETCH_ENABLEOPTIMIZEDACCESS          (0x1 << 27)
  86
  87 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      (((val) >> 24) & 0x7F)
  88 #define GPMC_PREFETCH_STATUS_COUNT(val)         ((val) & 0x00003fff)
  89
  90 #define CS_NUM_SHIFT                            24
  91 #define ENABLE_PREFETCH                         (0x1 << 7)
  92 #define DMA_MPU_MODE                            2
  93
  94 #define OMAP_NAND_TIMEOUT_MS                    5000
  95
  96 #define PRINT_REG(x) debug("+++ %.15s (0x%08x)=0x%08x\n", #x, &gpmc_cfg->x, readl(&gpmc_cfg->x))
  97
  98 /*
  99  * omap_nand_hwcontrol - Set the address pointers corretly for the
 100  *                      following address/data/command operation
 101  */
 102 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 103                                 uint32_t ctrl)
 104 {
 105         register struct nand_chip *this = mtd->priv;
 106         struct omap_nand_info *info = this->priv;
 107         int cs = info->cs;
 108
 109         /*
 110          * Point the IO_ADDR to DATA and ADDRESS registers instead
 111          * of chip address
 112          */
 113         switch (ctrl) {
 114         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
 115                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 116                 break;
 117         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
 118                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
 119                 break;
 120         case NAND_CTRL_CHANGE | NAND_NCE:
 121                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 122                 break;
 123         }
 124
 125         if (cmd != NAND_CMD_NONE)
 126                 writeb(cmd, this->IO_ADDR_W);
 127 }
 128
 129 /* Check wait pin as dev ready indicator */
 130 static int omap_dev_ready(struct mtd_info *mtd)
 131 {
 132         struct nand_chip *this = mtd->priv;
 133         struct omap_nand_info *info = this->priv;
 134         return !!(readl(&gpmc_cfg->status) & (1 << (8 + info->ws)));
 135 }
 136
 137 /*
 138  * gen_true_ecc - This function will generate true ECC value, which
 139  * can be used when correcting data read from NAND flash memory core
 140  *
 141  * @ecc_buf:    buffer to store ecc code
 142  *
 143  * @return:     re-formatted ECC value
 144  */
 145 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
 146 {
 147         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
 148                 ((ecc_buf[2] & 0x0F) << 8);
 149 }
 150
 151 /*
 152  * omap_correct_data - Compares the ecc read from nand spare area with ECC
 153  * registers values and corrects one bit error if it has occured
 154  * Further details can be had from OMAP TRM and the following selected links:
 155  * http://en.wikipedia.org/wiki/Hamming_code
 156  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
 157  *
 158  * @mtd:                 MTD device structure
 159  * @dat:                 page data
 160  * @read_ecc:            ecc read from nand flash
 161  * @calc_ecc:            ecc read from ECC registers
 162  *
 163  * @return 0 if data is OK or corrected, else returns -1
 164  */
 165 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 166                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 167 {
 168         uint32_t orig_ecc, new_ecc, res, hm;
 169         uint16_t parity_bits, byte;
 170         uint8_t bit;
 171
 172         /* Regenerate the orginal ECC */
 173         orig_ecc = gen_true_ecc(read_ecc);
 174         new_ecc = gen_true_ecc(calc_ecc);
 175         /* Get the XOR of real ecc */
 176         res = orig_ecc ^ new_ecc;
 177         if (res) {
 178                 /* Get the hamming width */
 179                 hm = hweight32(res);
 180                 /* Single bit errors can be corrected! */
 181                 if (hm == 12) {
 182                         /* Correctable data! */
 183                         parity_bits = res >> 16;
 184                         bit = (parity_bits & 0x7);
 185                         byte = (parity_bits >> 3) & 0x1FF;
 186                         /* Flip the bit to correct */
 187                         dat[byte] ^= (0x1 << bit);
 188                 } else if (hm == 1) {
 189                         printf("Error: Ecc is wrong\n");
 190                         /* ECC itself is corrupted */
 191                         return 2;
 192                 } else {
 193                         /*
 194                          * hm distance != parity pairs OR one, could mean 2 bit
 195                          * error OR potentially be on a blank page..
 196                          * orig_ecc: contains spare area data from nand flash.
 197                          * new_ecc: generated ecc while reading data area.
 198                          * Note: if the ecc = 0, all data bits from which it was
 199                          * generated are 0xFF.
 200                          * The 3 byte(24 bits) ecc is generated per 512byte
 201                          * chunk of a page. If orig_ecc(from spare area)
 202                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 203                          * this means that data area is 0xFF and spare area is
 204                          * 0xFF. A sure sign of a erased page!
 205                          */
 206                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 207                                 return 0;
 208                         printf("Error: Bad compare! failed\n");
 209                         /* detected 2 bit error */
 210                         return -1;
 211                 }
 212         }
 213         return 0;
 214 }
 215
 216 /*
 217  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 218  * @mtd:        MTD device structure
 219  * @mode:       Read/Write mode
 220  */
 221 __maybe_unused
 222 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 223 {
 224         struct nand_chip        *nand   = mtd->priv;
 225         struct omap_nand_info   *info   = nand->priv;
 226         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 227         unsigned int ecc_algo = 0;
 228         unsigned int bch_type = 0;
 229         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 230         u32 ecc_size_config_val = 0;
 231         u32 ecc_config_val = 0;
 232         int cs = info->cs;
 233
 234         /* configure GPMC for specific ecc-scheme */
 235         switch (info->ecc_scheme) {
 236         case OMAP_ECC_HAM1_CODE_SW:
 237                 return;
 238         case OMAP_ECC_HAM1_CODE_HW:
 239                 ecc_algo = 0x0;
 240                 bch_type = 0x0;
 241                 bch_wrapmode = 0x00;
 242                 eccsize0 = 0xFF;
 243                 eccsize1 = 0xFF;
 244                 break;
 245         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 246         case OMAP_ECC_BCH8_CODE_HW:
 247                 ecc_algo = 0x1;
 248                 bch_type = 0x1;
 249                 if (mode == NAND_ECC_WRITE) {
 250                         bch_wrapmode = 0x01;
 251                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 252                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 253                 } else {
 254                         bch_wrapmode = 0x01;
 255                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 256                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 257                 }
 258                 break;
 259         case OMAP_ECC_BCH16_CODE_HW:
 260                 ecc_algo = 0x1;
 261                 bch_type = 0x2;
 262                 if (mode == NAND_ECC_WRITE) {
 263                         bch_wrapmode = 0x01;
 264                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 265                         eccsize1 = 52; /* OOB bits in nibbles per sector */
 266                 } else {
 267                         bch_wrapmode = 0x01;
 268                         eccsize0 = 52; /* ECC bits in nibbles per sector */
 269                         eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
 270                 }
 271                 break;
 272         default:
 273                 return;
 274         }
 275         /* Clear ecc and enable bits */
 276         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 277         /* Configure ecc size for BCH */
 278         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 279         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 280
 281         /* Configure device details for BCH engine */
 282         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 283                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 284                         (bch_wrapmode << 8)     | /* wrap mode */
 285                         (dev_width << 7)        | /* bus width */
 286                         (0x0 << 4)              | /* number of sectors */
 287                         (cs <<  1)              | /* ECC CS */
 288                         (0x1));                   /* enable ECC */
 289         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 290 }
 291
 292 /*
 293  *  omap_calculate_ecc - Read ECC result
 294  *  @mtd:       MTD structure
 295  *  @dat:       unused
 296  *  @ecc_code:  ecc_code buffer
 297  *  Using noninverted ECC can be considered ugly since writing a blank
 298  *  page ie. padding will clear the ECC bytes. This is no problem as
 299  *  long nobody is trying to write data on the seemingly unused page.
 300  *  Reading an erased page will produce an ECC mismatch between
 301  *  generated and read ECC bytes that has to be dealt with separately.
 302  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 303  *  is used, the result of read will be 0x0 while the ECC offsets of the
 304  *  spare area will be 0xFF which will result in an ECC mismatch.
 305  */
 306 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 307                                 uint8_t *ecc_code)
 308 {
 309         struct nand_chip *chip = mtd->priv;
 310         struct omap_nand_info *info = chip->priv;
 311         uint32_t *ptr, val = 0;
 312         int8_t i = 0, j;
 313
 314         switch (info->ecc_scheme) {
 315         case OMAP_ECC_HAM1_CODE_HW:
 316                 val = readl(&gpmc_cfg->ecc1_result);
 317                 ecc_code[0] = val & 0xFF;
 318                 ecc_code[1] = (val >> 16) & 0xFF;
 319                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 320                 break;
 321 #ifdef CONFIG_BCH
 322         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 323 #endif
 324         case OMAP_ECC_BCH8_CODE_HW:
 325                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 326                 val = readl(ptr);
 327                 ecc_code[i++] = (val >>  0) & 0xFF;
 328                 ptr--;
 329                 for (j = 0; j < 3; j++) {
 330                         val = readl(ptr);
 331                         ecc_code[i++] = (val >> 24) & 0xFF;
 332                         ecc_code[i++] = (val >> 16) & 0xFF;
 333                         ecc_code[i++] = (val >>  8) & 0xFF;
 334                         ecc_code[i++] = (val >>  0) & 0xFF;
 335                         ptr--;
 336                 }
 337                 break;
 338         case OMAP_ECC_BCH16_CODE_HW:
 339                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
 340                 ecc_code[i++] = (val >>  8) & 0xFF;
 341                 ecc_code[i++] = (val >>  0) & 0xFF;
 342                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
 343                 ecc_code[i++] = (val >> 24) & 0xFF;
 344                 ecc_code[i++] = (val >> 16) & 0xFF;
 345                 ecc_code[i++] = (val >>  8) & 0xFF;
 346                 ecc_code[i++] = (val >>  0) & 0xFF;
 347                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
 348                 ecc_code[i++] = (val >> 24) & 0xFF;
 349                 ecc_code[i++] = (val >> 16) & 0xFF;
 350                 ecc_code[i++] = (val >>  8) & 0xFF;
 351                 ecc_code[i++] = (val >>  0) & 0xFF;
 352                 for (j = 3; j >= 0; j--) {
 353                         val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
 354                                                                         );
 355                         ecc_code[i++] = (val >> 24) & 0xFF;
 356                         ecc_code[i++] = (val >> 16) & 0xFF;
 357                         ecc_code[i++] = (val >>  8) & 0xFF;
 358                         ecc_code[i++] = (val >>  0) & 0xFF;
 359                 }
 360                 break;
 361         default:
 362                 return -EINVAL;
 363         }
 364         /* ECC scheme specific syndrome customizations */
 365         switch (info->ecc_scheme) {
 366         case OMAP_ECC_HAM1_CODE_HW:
 367                 break;
 368 #ifdef CONFIG_BCH
 369         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 370
 371                 for (i = 0; i < chip->ecc.bytes; i++)
 372                         *(ecc_code + i) = *(ecc_code + i) ^
 373                                                 bch8_polynomial[i];
 374                 break;
 375 #endif
 376         case OMAP_ECC_BCH8_CODE_HW:
 377                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 378                 break;
 379         case OMAP_ECC_BCH16_CODE_HW:
 380                 break;
 381         default:
 382                 return -EINVAL;
 383         }
 384         return 0;
 385 }
 386
 387 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
 388
 389 #define PREFETCH_CONFIG1_CS_SHIFT       24
 390 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 391 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 392 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 393 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 394 #define ENABLE_PREFETCH                 (1 << 7)
 395
 396 /**
 397  * omap_prefetch_enable - configures and starts prefetch transfer
 398  * @fifo_th: fifo threshold to be used for read/ write
 399  * @count: number of bytes to be transferred
 400  * @is_write: prefetch read(0) or write post(1) mode
 401  * @cs: chip select to use
 402  */
 403 static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
 404 {
 405         uint32_t val;
 406
 407         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 408                 return -EINVAL;
 409
 410         if (readl(&gpmc_cfg->prefetch_control))
 411                 return -EBUSY;
 412
 413         /* Set the amount of bytes to be prefetched */
 414         writel(count, &gpmc_cfg->prefetch_config2);
 415
 416         val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
 417                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
 418         writel(val, &gpmc_cfg->prefetch_config1);
 419
 420         /*  Start the prefetch engine */
 421         writel(1, &gpmc_cfg->prefetch_control);
 422
 423         return 0;
 424 }
 425
 426 /**
 427  * omap_prefetch_reset - disables and stops the prefetch engine
 428  */
 429 static void omap_prefetch_reset(void)
 430 {
 431         writel(0, &gpmc_cfg->prefetch_control);
 432         writel(0, &gpmc_cfg->prefetch_config1);
 433 }
 434
 435 static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
 436 {
 437         int ret;
 438         uint32_t cnt;
 439         struct omap_nand_info *info = chip->priv;
 440
 441         ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
 442         if (ret < 0)
 443                 return ret;
 444
 445         do {
 446                 int i;
 447
 448                 cnt = readl(&gpmc_cfg->prefetch_status);
 449                 cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
 450
 451                 for (i = 0; i < cnt / 4; i++) {
 452                         *buf++ = readl(CONFIG_SYS_NAND_BASE);
 453                         len -= 4;
 454                 }
 455         } while (len);
 456
 457         omap_prefetch_reset();
 458
 459         return 0;
 460 }
 461
 462 static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
 463 {
 464         struct nand_chip *chip = mtd->priv;
 465
 466         if (chip->options & NAND_BUSWIDTH_16)
 467                 nand_read_buf16(mtd, buf, len);
 468         else
 469                 nand_read_buf(mtd, buf, len);
 470 }
 471
 472 static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 473 {
 474         int ret;
 475         uint32_t head, tail;
 476         struct nand_chip *chip = mtd->priv;
 477
 478         /*
 479          * If the destination buffer is unaligned, start with reading
 480          * the overlap byte-wise.
 481          */
 482         head = ((uint32_t) buf) % 4;
 483         if (head) {
 484                 omap_nand_read(mtd, buf, head);
 485                 buf += head;
 486                 len -= head;
 487         }
 488
 489         /*
 490          * Only transfer multiples of 4 bytes in a pre-fetched fashion.
 491          * If there's a residue, care for it byte-wise afterwards.
 492          */
 493         tail = len % 4;
 494
 495         ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
 496         if (ret < 0) {
 497                 /* fallback in case the prefetch engine is busy */
 498                 omap_nand_read(mtd, buf, len);
 499         } else if (tail) {
 500                 buf += len - tail;
 501                 omap_nand_read(mtd, buf, tail);
 502         }
 503 }
 504 #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
 505
 506 #ifdef CONFIG_NAND_OMAP_ELM
 507 /*
 508  * omap_reverse_list - re-orders list elements in reverse order [internal]
 509  * @list:       pointer to start of list
 510  * @length:     length of list
 511 */
 512 static void omap_reverse_list(u8 *list, unsigned int length)
 513 {
 514         unsigned int i, j;
 515         unsigned int half_length = length / 2;
 516         u8 tmp;
 517         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 518                 tmp = list[i];
 519                 list[i] = list[j];
 520                 list[j] = tmp;
 521         }
 522 }
 523
 524 /*
 525  * omap_correct_data_bch - Compares the ecc read from nand spare area
 526  * with ECC registers values and corrects one bit error if it has occured
 527  *
 528  * @mtd:        MTD device structure
 529  * @dat:        page data
 530  * @read_ecc:   ecc read from nand flash (ignored)
 531  * @calc_ecc:   ecc read from ECC registers
 532  *
 533  * @return 0 if data is OK or corrected, else returns -1
 534  */
 535 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 536                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 537 {
 538         struct nand_chip *chip = mtd->priv;
 539         struct omap_nand_info *info = chip->priv;
 540         struct nand_ecc_ctrl *ecc = &chip->ecc;
 541         uint32_t error_count = 0, error_max;
 542         uint32_t error_loc[ELM_MAX_ERROR_COUNT];
 543         enum bch_level bch_type;
 544         uint32_t i, ecc_flag = 0;
 545         uint8_t count;
 546         uint32_t byte_pos, bit_pos;
 547         int err = 0;
 548
 549         /* check calculated ecc */
 550         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 551                 if (calc_ecc[i] != 0x00)
 552                         ecc_flag = 1;
 553         }
 554         if (!ecc_flag)
 555                 return 0;
 556
 557         /* check for whether its a erased-page */
 558         ecc_flag = 0;
 559         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 560                 if (read_ecc[i] != 0xff)
 561                         ecc_flag = 1;
 562         }
 563         if (!ecc_flag)
 564                 return 0;
 565
 566         /*
 567          * while reading ECC result we read it in big endian.
 568          * Hence while loading to ELM we have rotate to get the right endian.
 569          */
 570         switch (info->ecc_scheme) {
 571         case OMAP_ECC_BCH8_CODE_HW:
 572                 bch_type = BCH_8_BIT;
 573                 omap_reverse_list(calc_ecc, ecc->bytes - 1);
 574                 break;
 575         case OMAP_ECC_BCH16_CODE_HW:
 576                 bch_type = BCH_16_BIT;
 577                 omap_reverse_list(calc_ecc, ecc->bytes);
 578                 break;
 579         default:
 580                 return -EINVAL;
 581         }
 582         /* use elm module to check for errors */
 583         elm_config(bch_type);
 584         err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
 585         if (err)
 586                 return err;
 587
 588         /* correct bch error */
 589         for (count = 0; count < error_count; count++) {
 590                 switch (info->ecc_scheme) {
 591                 case OMAP_ECC_BCH8_CODE_HW:
 592                         /* 14th byte in ECC is reserved to match ROM layout */
 593                         error_max = SECTOR_BYTES + (ecc->bytes - 1);
 594                         break;
 595                 case OMAP_ECC_BCH16_CODE_HW:
 596                         error_max = SECTOR_BYTES + ecc->bytes;
 597                         break;
 598                 default:
 599                         return -EINVAL;
 600                 }
 601                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 602                 bit_pos  = error_loc[count] % 8;
 603                 if (byte_pos < SECTOR_BYTES) {
 604                         dat[byte_pos] ^= 1 << bit_pos;
 605                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 606                 } else if (byte_pos < error_max) {
 607                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 608                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 609                                                                 SECTOR_BYTES);
 610                 } else {
 611                         err = -EBADMSG;
 612                         printf("nand: error: invalid bit-flip location\n");
 613                 }
 614         }
 615         return (err) ? err : error_count;
 616 }
 617
 618 /**
 619  * omap_read_page_bch - hardware ecc based page read function
 620  * @mtd:        mtd info structure
 621  * @chip:       nand chip info structure
 622  * @buf:        buffer to store read data
 623  * @oob_required: caller expects OOB data read to chip->oob_poi
 624  * @page:       page number to read
 625  *
 626  */
 627 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 628                                 uint8_t *buf, int oob_required, int page)
 629 {
 630         int i, eccsize = chip->ecc.size;
 631         int eccbytes = chip->ecc.bytes;
 632         int eccsteps = chip->ecc.steps;
 633         uint8_t *p = buf;
 634         uint8_t *ecc_calc = chip->buffers->ecccalc;
 635         uint8_t *ecc_code = chip->buffers->ecccode;
 636         uint32_t *eccpos = chip->ecc.layout->eccpos;
 637         uint8_t *oob = &chip->oob_poi[eccpos[0]];
 638         uint32_t data_pos;
 639         uint32_t oob_pos;
 640
 641         data_pos = 0;
 642         /* oob area start */
 643         oob_pos = (eccsize * eccsteps) + eccpos[0];
 644
 645         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 646                                 oob += eccbytes) {
 647                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 648                 /* read data */
 649                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
 650                 chip->read_buf(mtd, p, eccsize);
 651
 652                 /* read respective ecc from oob area */
 653                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
 654                 chip->read_buf(mtd, oob, eccbytes);
 655                 /* read syndrome */
 656                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 657
 658                 if (oob_required) {
 659                         /* reread the OOB area to get the metadata */
 660                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, page);
 661                         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 662                 }
 663
 664                 data_pos += eccsize;
 665                 oob_pos += eccbytes;
 666         }
 667
 668         for (i = 0; i < chip->ecc.total; i++)
 669                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 670
 671         eccsteps = chip->ecc.steps;
 672         p = buf;
 673
 674         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 675                 int stat;
 676
 677                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 678                 if (stat < 0)
 679                         mtd->ecc_stats.failed++;
 680                 else
 681                         mtd->ecc_stats.corrected += stat;
 682         }
 683         return 0;
 684 }
 685 #endif /* CONFIG_NAND_OMAP_ELM */
 686
 687 /*
 688  * OMAP3 BCH8 support (with BCH library)
 689  */
 690 #ifdef CONFIG_BCH
 691 /**
 692  * omap_correct_data_bch_sw - Decode received data and correct errors
 693  * @mtd: MTD device structure
 694  * @data: page data
 695  * @read_ecc: ecc read from nand flash
 696  * @calc_ecc: ecc read from HW ECC registers
 697  */
 698 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 699                                  u_char *read_ecc, u_char *calc_ecc)
 700 {
 701         int i, count;
 702         /* cannot correct more than 8 errors */
 703         unsigned int errloc[8];
 704         struct nand_chip *chip = mtd->priv;
 705         struct omap_nand_info *info = chip->priv;
 706
 707         count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 708                                                         NULL, errloc);
 709         if (count > 0) {
 710                 /* correct errors */
 711                 for (i = 0; i < count; i++) {
 712                         /* correct data only, not ecc bytes */
 713                         if (errloc[i] < 8*512)
 714                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 715                         printf("corrected bitflip %u\n", errloc[i]);
 716 #ifdef DEBUG
 717                         printf("read_ecc: ");
 718                         /*
 719                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 720                          * here!
 721                          */
 722                         for (i = 0; i < 13; i++)
 723                                 printf("%02x ", read_ecc[i]);
 724                         printf("\n");
 725                         printf("calc_ecc: ");
 726                         for (i = 0; i < 13; i++)
 727                                 printf("%02x ", calc_ecc[i]);
 728                         printf("\n");
 729 #endif
 730                 }
 731         } else if (count < 0) {
 732                 printf("ecc unrecoverable error\n");
 733         }
 734         return count;
 735 }
 736
 737 /**
 738  * omap_free_bch - Release BCH ecc resources
 739  * @mtd: MTD device structure
 740  */
 741 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 742 {
 743         struct nand_chip *chip = mtd->priv;
 744         struct omap_nand_info *info = chip->priv;
 745
 746         if (info->control) {
 747                 free_bch(info->control);
 748                 info->control = NULL;
 749         }
 750 }
 751 #endif /* CONFIG_BCH */
 752
 753 /**
 754  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 755  * @nand: NAND chip device structure
 756  * @ecc_scheme: ecc scheme to configure
 757  * @pagesize: number of main-area bytes per page of NAND device
 758  * @oobsize: number of OOB/spare bytes per page of NAND device
 759  */
 760 static int omap_select_ecc_scheme(struct nand_chip *nand,
 761         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 762         struct omap_nand_info   *info           = nand->priv;
 763         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 764         int eccsteps = pagesize / SECTOR_BYTES;
 765         int i;
 766
 767         switch (ecc_scheme) {
 768         case OMAP_ECC_HAM1_CODE_SW:
 769                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 770                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 771                  * initialized in nand_scan_tail(), so just set ecc.mode */
 772                 info->control           = NULL;
 773                 nand->ecc.mode          = NAND_ECC_SOFT;
 774                 nand->ecc.layout        = NULL;
 775                 nand->ecc.size          = 0;
 776                 break;
 777
 778         case OMAP_ECC_HAM1_CODE_HW:
 779                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 780                 /* check ecc-scheme requirements before updating ecc info */
 781                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 782                         printf("nand: error: insufficient OOB: require=%d\n", (
 783                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 784                         return -EINVAL;
 785                 }
 786                 info->control           = NULL;
 787                 /* populate ecc specific fields */
 788                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 789                 nand->ecc.mode          = NAND_ECC_HW;
 790                 nand->ecc.strength      = 1;
 791                 nand->ecc.size          = SECTOR_BYTES;
 792                 nand->ecc.bytes         = 3;
 793                 nand->ecc.hwctl         = omap_enable_hwecc;
 794                 nand->ecc.correct       = omap_correct_data;
 795                 nand->ecc.calculate     = omap_calculate_ecc;
 796                 /* define ecc-layout */
 797                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 798                 for (i = 0; i < ecclayout->eccbytes; i++) {
 799                         if (nand->options & NAND_BUSWIDTH_16)
 800                                 ecclayout->eccpos[i] = i + 2;
 801                         else
 802                                 ecclayout->eccpos[i] = i + 1;
 803                 }
 804                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 805                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 806                                                 BADBLOCK_MARKER_LENGTH;
 807                 break;
 808
 809         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 810 #ifdef CONFIG_BCH
 811                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 812                 /* check ecc-scheme requirements before updating ecc info */
 813                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 814                         printf("nand: error: insufficient OOB: require=%d\n", (
 815                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 816                         return -EINVAL;
 817                 }
 818                 /* check if BCH S/W library can be used for error detection */
 819                 info->control = init_bch(13, 8, 0x201b);
 820                 if (!info->control) {
 821                         printf("nand: error: could not init_bch()\n");
 822                         return -ENODEV;
 823                 }
 824                 /* populate ecc specific fields */
 825                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 826                 nand->ecc.mode          = NAND_ECC_HW;
 827                 nand->ecc.strength      = 8;
 828                 nand->ecc.size          = SECTOR_BYTES;
 829                 nand->ecc.bytes         = 13;
 830                 nand->ecc.hwctl         = omap_enable_hwecc;
 831                 nand->ecc.correct       = omap_correct_data_bch_sw;
 832                 nand->ecc.calculate     = omap_calculate_ecc;
 833                 /* define ecc-layout */
 834                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 835                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 836                 for (i = 1; i < ecclayout->eccbytes; i++) {
 837                         if (i % nand->ecc.bytes)
 838                                 ecclayout->eccpos[i] =
 839                                                 ecclayout->eccpos[i - 1] + 1;
 840                         else
 841                                 ecclayout->eccpos[i] =
 842                                                 ecclayout->eccpos[i - 1] + 2;
 843                 }
 844                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 845                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 846                                                 BADBLOCK_MARKER_LENGTH;
 847                 break;
 848 #else
 849                 printf("nand: error: CONFIG_BCH required for ECC\n");
 850                 return -EINVAL;
 851 #endif
 852
 853         case OMAP_ECC_BCH8_CODE_HW:
 854 #ifdef CONFIG_NAND_OMAP_ELM
 855                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 856                 /* check ecc-scheme requirements before updating ecc info */
 857                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 858                         printf("nand: error: insufficient OOB: require=%d\n", (
 859                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 860                         return -EINVAL;
 861                 }
 862                 /* intialize ELM for ECC error detection */
 863                 elm_init();
 864                 info->control           = NULL;
 865                 /* populate ecc specific fields */
 866                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 867                 nand->ecc.mode          = NAND_ECC_HW;
 868                 nand->ecc.strength      = 8;
 869                 nand->ecc.size          = SECTOR_BYTES;
 870                 nand->ecc.bytes         = 14;
 871                 nand->ecc.hwctl         = omap_enable_hwecc;
 872                 nand->ecc.correct       = omap_correct_data_bch;
 873                 nand->ecc.calculate     = omap_calculate_ecc;
 874                 nand->ecc.read_page     = omap_read_page_bch;
 875                 /* define ecc-layout */
 876                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 877                 for (i = 0; i < ecclayout->eccbytes; i++)
 878                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 879                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 880                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 881                                                 BADBLOCK_MARKER_LENGTH;
 882                 break;
 883 #else
 884                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 885                 return -EINVAL;
 886 #endif
 887
 888         case OMAP_ECC_BCH16_CODE_HW:
 889 #ifdef CONFIG_NAND_OMAP_ELM
 890                 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
 891                 /* check ecc-scheme requirements before updating ecc info */
 892                 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 893                         printf("nand: error: insufficient OOB: require=%d\n", (
 894                                 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 895                         return -EINVAL;
 896                 }
 897                 /* intialize ELM for ECC error detection */
 898                 elm_init();
 899                 /* populate ecc specific fields */
 900                 nand->ecc.mode          = NAND_ECC_HW;
 901                 nand->ecc.size          = SECTOR_BYTES;
 902                 nand->ecc.bytes         = 26;
 903                 nand->ecc.strength      = 16;
 904                 nand->ecc.hwctl         = omap_enable_hwecc;
 905                 nand->ecc.correct       = omap_correct_data_bch;
 906                 nand->ecc.calculate     = omap_calculate_ecc;
 907                 nand->ecc.read_page     = omap_read_page_bch;
 908                 /* define ecc-layout */
 909                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 910                 for (i = 0; i < ecclayout->eccbytes; i++)
 911                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 912                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 913                 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
 914                                                 BADBLOCK_MARKER_LENGTH;
 915                 break;
 916 #else
 917                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 918                 return -EINVAL;
 919 #endif
 920         default:
 921                 debug("nand: error: ecc scheme not enabled or supported\n");
 922                 return -EINVAL;
 923         }
 924
 925         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
 926         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
 927                 nand->ecc.layout = ecclayout;
 928
 929         info->ecc_scheme = ecc_scheme;
 930         return 0;
 931 }
 932
 933 #ifndef CONFIG_SPL_BUILD
 934 /*
 935  * omap_nand_switch_ecc - switch the ECC operation between different engines
 936  * (h/w and s/w) and different algorithms (hamming and BCHx)
 937  *
 938  * @hardware            - true if one of the HW engines should be used
 939  * @eccstrength         - the number of bits that could be corrected
 940  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
 941  */
 942 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 943 {
 944         struct nand_chip *nand;
 945         struct mtd_info *mtd;
 946         int err = 0;
 947
 948         if (nand_curr_device < 0 ||
 949             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 950             !nand_info[nand_curr_device].name) {
 951                 printf("nand: error: no NAND devices found\n");
 952                 return -ENODEV;
 953         }
 954
 955         mtd = &nand_info[nand_curr_device];
 956         nand = mtd->priv;
 957         nand->options |= NAND_OWN_BUFFERS;
 958         nand->options &= ~NAND_SUBPAGE_READ;
 959         /* Setup the ecc configurations again */
 960         if (hardware) {
 961                 if (eccstrength == 1) {
 962                         err = omap_select_ecc_scheme(nand,
 963                                         OMAP_ECC_HAM1_CODE_HW,
 964                                         mtd->writesize, mtd->oobsize);
 965                 } else if (eccstrength == 8) {
 966                         err = omap_select_ecc_scheme(nand,
 967                                         OMAP_ECC_BCH8_CODE_HW,
 968                                         mtd->writesize, mtd->oobsize);
 969                 } else {
 970                         printf("nand: error: unsupported ECC scheme\n");
 971                         return -EINVAL;
 972                 }
 973         } else {
 974                 if (eccstrength == 1) {
 975                         err = omap_select_ecc_scheme(nand,
 976                                         OMAP_ECC_HAM1_CODE_SW,
 977                                         mtd->writesize, mtd->oobsize);
 978                 } else if (eccstrength == 8) {
 979                         err = omap_select_ecc_scheme(nand,
 980                                         OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
 981                                         mtd->writesize, mtd->oobsize);
 982                 } else {
 983                         printf("nand: error: unsupported ECC scheme\n");
 984                         return -EINVAL;
 985                 }
 986         }
 987
 988         /* Update NAND handling after ECC mode switch */
 989         if (!err)
 990                 err = nand_scan_tail(mtd);
 991         return err;
 992 }
 993 #endif /* CONFIG_SPL_BUILD */
 994
 995 /*
 996  * Board-specific NAND initialization. The following members of the
 997  * argument are board-specific:
 998  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 999  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
1000  * - cmd_ctrl: hardwarespecific function for accesing control-lines
1001  * - waitfunc: hardwarespecific function for accesing device ready/busy line
1002  * - ecc.hwctl: function to enable (reset) hardware ecc generator
1003  * - ecc.mode: mode of ecc, see defines
1004  * - chip_delay: chip dependent delay for transfering data from array to
1005  *   read regs (tR)
1006  * - options: various chip options. They can partly be set to inform
1007  *   nand_scan about special functionality. See the defines for further
1008  *   explanation
1009  */
1010 int board_nand_init(struct nand_chip *nand)
1011 {
1012         int32_t gpmc_config = 0;
1013         int cs = cs_next++;
1014         int err = 0;
1015         /*
1016          * xloader/Uboot's gpmc configuration would have configured GPMC for
1017          * nand type of memory. The following logic scans and latches on to the
1018          * first CS with NAND type memory.
1019          * TBD: need to make this logic generic to handle multiple CS NAND
1020          * devices.
1021          */
1022         while (cs < GPMC_MAX_CS) {
1023                 /* Check if NAND type is set */
1024                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
1025                         /* Found it!! */
1026                         break;
1027                 }
1028                 cs++;
1029         }
1030         if (cs >= GPMC_MAX_CS) {
1031                 printf("nand: error: Unable to find NAND settings in "
1032                         "GPMC Configuration - quitting\n");
1033                 return -ENODEV;
1034         }
1035
1036         gpmc_config = readl(&gpmc_cfg->config);
1037         /* Disable Write protect */
1038         gpmc_config |= 0x10;
1039         writel(gpmc_config, &gpmc_cfg->config);
1040
1041         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
1042         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
1043         omap_nand_info[cs].control = NULL;
1044         omap_nand_info[cs].cs = cs;
1045         omap_nand_info[cs].ws = wscfg[cs];
1046         nand->priv      = &omap_nand_info[cs];
1047         nand->cmd_ctrl  = omap_nand_hwcontrol;
1048         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
1049         nand->chip_delay = 100;
1050         nand->ecc.layout = &omap_ecclayout;
1051
1052         /* configure driver and controller based on NAND device bus-width */
1053         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
1054 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
1055         nand->options |= NAND_BUSWIDTH_16;
1056         writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
1057 #else
1058         nand->options &= ~NAND_BUSWIDTH_16;
1059         writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
1060 #endif
1061         /* select ECC scheme */
1062 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
1063         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
1064                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
1065 #else
1066         /* pagesize and oobsize are not required to configure sw ecc-scheme */
1067         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
1068                         0, 0);
1069 #endif
1070         if (err)
1071                 return err;
1072 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1073         if (nand->ecc.layout) {
1074                 bbt_main_descr.offs = nand->ecc.layout->oobfree[0].offset;
1075                 bbt_main_descr.veroffs = bbt_main_descr.offs +
1076                         sizeof(bbt_pattern);
1077
1078                 bbt_mirror_descr.offs = nand->ecc.layout->oobfree[0].offset;
1079                 bbt_mirror_descr.veroffs = bbt_mirror_descr.offs +
1080                         sizeof(mirror_pattern);
1081         }
1082
1083         nand->bbt_options |= NAND_BBT_USE_FLASH;
1084         nand->bbt_td = &bbt_main_descr;
1085         nand->bbt_md = &bbt_mirror_descr;
1086 #endif
1087
1088 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
1089         nand->read_buf = omap_nand_read_prefetch;
1090 #else
1091         if (nand->options & NAND_BUSWIDTH_16)
1092                 nand->read_buf = nand_read_buf16;
1093         else
1094                 nand->read_buf = nand_read_buf;
1095 #endif
1096
1097         nand->dev_ready = omap_dev_ready;
1098
1099         return 0;
1100 }