drivers/mtd/nand/sunxi_nand_spl.c

   1 /*
   2  * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
   3  * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/arch/clock.h>
   9 #include <asm/io.h>
  10 #include <common.h>
  11 #include <config.h>
  12 #include <nand.h>
  13
  14 /* registers */
  15 #define NFC_CTL                    0x00000000
  16 #define NFC_ST                     0x00000004
  17 #define NFC_INT                    0x00000008
  18 #define NFC_TIMING_CTL             0x0000000C
  19 #define NFC_TIMING_CFG             0x00000010
  20 #define NFC_ADDR_LOW               0x00000014
  21 #define NFC_ADDR_HIGH              0x00000018
  22 #define NFC_SECTOR_NUM             0x0000001C
  23 #define NFC_CNT                    0x00000020
  24 #define NFC_CMD                    0x00000024
  25 #define NFC_RCMD_SET               0x00000028
  26 #define NFC_WCMD_SET               0x0000002C
  27 #define NFC_IO_DATA                0x00000030
  28 #define NFC_ECC_CTL                0x00000034
  29 #define NFC_ECC_ST                 0x00000038
  30 #define NFC_DEBUG                  0x0000003C
  31 #define NFC_ECC_CNT0               0x00000040
  32 #define NFC_ECC_CNT1               0x00000044
  33 #define NFC_ECC_CNT2               0x00000048
  34 #define NFC_ECC_CNT3               0x0000004C
  35 #define NFC_USER_DATA_BASE         0x00000050
  36 #define NFC_EFNAND_STATUS          0x00000090
  37 #define NFC_SPARE_AREA             0x000000A0
  38 #define NFC_PATTERN_ID             0x000000A4
  39 #define NFC_RAM0_BASE              0x00000400
  40 #define NFC_RAM1_BASE              0x00000800
  41
  42 #define NFC_CTL_EN                 (1 << 0)
  43 #define NFC_CTL_RESET              (1 << 1)
  44 #define NFC_CTL_RAM_METHOD         (1 << 14)
  45
  46
  47 #define NFC_ECC_EN                 (1 << 0)
  48 #define NFC_ECC_PIPELINE           (1 << 3)
  49 #define NFC_ECC_EXCEPTION          (1 << 4)
  50 #define NFC_ECC_BLOCK_SIZE         (1 << 5)
  51 #define NFC_ECC_RANDOM_EN          (1 << 9)
  52 #define NFC_ECC_RANDOM_DIRECTION   (1 << 10)
  53
  54
  55 #define NFC_ADDR_NUM_OFFSET        16
  56 #define NFC_SEND_ADR               (1 << 19)
  57 #define NFC_ACCESS_DIR             (1 << 20)
  58 #define NFC_DATA_TRANS             (1 << 21)
  59 #define NFC_SEND_CMD1              (1 << 22)
  60 #define NFC_WAIT_FLAG              (1 << 23)
  61 #define NFC_SEND_CMD2              (1 << 24)
  62 #define NFC_SEQ                    (1 << 25)
  63 #define NFC_DATA_SWAP_METHOD       (1 << 26)
  64 #define NFC_ROW_AUTO_INC           (1 << 27)
  65 #define NFC_SEND_CMD3              (1 << 28)
  66 #define NFC_SEND_CMD4              (1 << 29)
  67
  68 #define NFC_CMD_INT_FLAG           (1 << 1)
  69
  70 #define NFC_READ_CMD_OFFSET         0
  71 #define NFC_RANDOM_READ_CMD0_OFFSET 8
  72 #define NFC_RANDOM_READ_CMD1_OFFSET 16
  73
  74 #define NFC_CMD_RNDOUTSTART        0xE0
  75 #define NFC_CMD_RNDOUT             0x05
  76 #define NFC_CMD_READSTART          0x30
  77
  78
  79 #define NFC_PAGE_CMD               (2 << 30)
  80
  81 #define SUNXI_DMA_CFG_REG0              0x300
  82 #define SUNXI_DMA_SRC_START_ADDR_REG0   0x304
  83 #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
  84 #define SUNXI_DMA_DDMA_BC_REG0          0x30C
  85 #define SUNXI_DMA_DDMA_PARA_REG0        0x318
  86
  87 #define SUNXI_DMA_DDMA_CFG_REG_LOADING  (1 << 31)
  88 #define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
  89 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
  90 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
  91 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
  92 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
  93
  94 #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
  95 #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
  96
  97 /* minimal "boot0" style NAND support for Allwinner A20 */
  98
  99 /* random seed used by linux */
 100 const uint16_t random_seed[128] = {
 101         0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
 102         0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
 103         0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
 104         0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
 105         0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
 106         0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
 107         0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
 108         0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
 109         0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
 110         0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
 111         0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
 112         0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
 113         0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
 114         0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
 115         0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
 116         0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
 117 };
 118
 119 /* random seed used for syndrome calls */
 120 const uint16_t random_seed_syndrome = 0x4a80;
 121
 122 #define MAX_RETRIES 10
 123
 124 static int check_value_inner(int offset, int expected_bits,
 125                                 int max_number_of_retries, int negation)
 126 {
 127         int retries = 0;
 128         do {
 129                 int val = readl(offset) & expected_bits;
 130                 if (negation ? !val : val)
 131                         return 1;
 132                 mdelay(1);
 133                 retries++;
 134         } while (retries < max_number_of_retries);
 135
 136         return 0;
 137 }
 138
 139 static inline int check_value(int offset, int expected_bits,
 140                                 int max_number_of_retries)
 141 {
 142         return check_value_inner(offset, expected_bits,
 143                                         max_number_of_retries, 0);
 144 }
 145
 146 static inline int check_value_negated(int offset, int unexpected_bits,
 147                                         int max_number_of_retries)
 148 {
 149         return check_value_inner(offset, unexpected_bits,
 150                                         max_number_of_retries, 1);
 151 }
 152
 153 void nand_init(void)
 154 {
 155         uint32_t val;
 156
 157         board_nand_init();
 158
 159         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 160         /* enable and reset CTL */
 161         writel(val | NFC_CTL_EN | NFC_CTL_RESET,
 162                SUNXI_NFC_BASE + NFC_CTL);
 163
 164         if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
 165                                  NFC_CTL_RESET, MAX_RETRIES)) {
 166                 printf("Couldn't initialize nand\n");
 167         }
 168
 169         /* reset NAND */
 170         writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
 171                SUNXI_NFC_BASE + NFC_CMD);
 172
 173         if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_CMD_INT_FLAG,
 174                          MAX_RETRIES)) {
 175                 printf("Error timeout waiting for nand reset\n");
 176                 return;
 177         }
 178 }
 179
 180 static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
 181                            int syndrome, uint32_t *ecc_errors)
 182 {
 183         uint32_t val;
 184         int ecc_off = 0;
 185         uint16_t ecc_mode = 0;
 186         uint16_t rand_seed;
 187         uint32_t page;
 188         uint16_t column;
 189         uint32_t oob_offset;
 190
 191         switch (CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH) {
 192         case 16:
 193                 ecc_mode = 0;
 194                 ecc_off = 0x20;
 195                 break;
 196         case 24:
 197                 ecc_mode = 1;
 198                 ecc_off = 0x2e;
 199                 break;
 200         case 28:
 201                 ecc_mode = 2;
 202                 ecc_off = 0x32;
 203                 break;
 204         case 32:
 205                 ecc_mode = 3;
 206                 ecc_off = 0x3c;
 207                 break;
 208         case 40:
 209                 ecc_mode = 4;
 210                 ecc_off = 0x4a;
 211                 break;
 212         case 48:
 213                 ecc_mode = 4;
 214                 ecc_off = 0x52;
 215                 break;
 216         case 56:
 217                 ecc_mode = 4;
 218                 ecc_off = 0x60;
 219                 break;
 220         case 60:
 221                 ecc_mode = 4;
 222                 ecc_off = 0x0;
 223                 break;
 224         case 64:
 225                 ecc_mode = 4;
 226                 ecc_off = 0x0;
 227                 break;
 228         default:
 229                 ecc_mode = 0;
 230                 ecc_off = 0;
 231         }
 232
 233         if (ecc_off == 0) {
 234                 printf("Unsupported ECC strength (%d)!\n",
 235                        CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH);
 236                 return;
 237         }
 238
 239         page = real_addr / CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
 240         column = real_addr % CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
 241
 242         if (syndrome)
 243                 column += (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
 244                         * ecc_off;
 245
 246         /* clear ecc status */
 247         writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
 248
 249         /* Choose correct seed */
 250         if (syndrome)
 251                 rand_seed = random_seed_syndrome;
 252         else
 253                 rand_seed = random_seed[page % 128];
 254
 255         writel((rand_seed << 16) | NFC_ECC_RANDOM_EN | NFC_ECC_EN
 256                 | NFC_ECC_PIPELINE | (ecc_mode << 12),
 257                 SUNXI_NFC_BASE + NFC_ECC_CTL);
 258
 259         val = readl(SUNXI_NFC_BASE + NFC_CTL);
 260         writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
 261
 262         if (!syndrome) {
 263                 oob_offset = CONFIG_NAND_SUNXI_SPL_PAGE_SIZE
 264                         + (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
 265                         * ecc_off;
 266                 writel(oob_offset, SUNXI_NFC_BASE + NFC_SPARE_AREA);
 267         }
 268
 269         flush_dcache_range(dst,
 270                            ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
 271                                  ARCH_DMA_MINALIGN));
 272
 273         /* SUNXI_DMA */
 274         writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
 275         /* read from REG_IO_DATA */
 276         writel(SUNXI_NFC_BASE + NFC_IO_DATA,
 277                SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
 278         /* read to RAM */
 279         writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
 280         writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC
 281                         | SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
 282                         SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
 283         writel(CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
 284                SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); /* 1kB */
 285         writel(SUNXI_DMA_DDMA_CFG_REG_LOADING
 286                 | SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32
 287                 | SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM
 288                 | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32
 289                 | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO
 290                 | SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
 291                 SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
 292
 293         writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET)
 294                 | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET)
 295                 | (NFC_CMD_READSTART | NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE
 296                         + NFC_RCMD_SET);
 297         writel(1, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
 298         writel(((page & 0xFFFF) << 16) | column,
 299                SUNXI_NFC_BASE + NFC_ADDR_LOW);
 300         writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
 301         writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
 302                 NFC_PAGE_CMD | NFC_WAIT_FLAG | (4 << NFC_ADDR_NUM_OFFSET) |
 303                 NFC_SEND_ADR | NFC_DATA_SWAP_METHOD | (syndrome ? NFC_SEQ : 0),
 304                 SUNXI_NFC_BASE + NFC_CMD);
 305
 306         if (!check_value(SUNXI_NFC_BASE + NFC_ST, (1 << 2),
 307                          MAX_RETRIES)) {
 308                 printf("Error while initializing dma interrupt\n");
 309                 return;
 310         }
 311
 312         if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
 313                                  SUNXI_DMA_DDMA_CFG_REG_LOADING, MAX_RETRIES)) {
 314                 printf("Error while waiting for dma transfer to finish\n");
 315                 return;
 316         }
 317
 318         invalidate_dcache_range(dst,
 319                         ALIGN(dst + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
 320                               ARCH_DMA_MINALIGN));
 321
 322         if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
 323                 (*ecc_errors)++;
 324 }
 325
 326 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
 327 {
 328         void *current_dest;
 329         uint32_t ecc_errors = 0;
 330
 331         for (current_dest = dest;
 332                         current_dest < (dest + size);
 333                         current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
 334                 nand_read_page(offs, (dma_addr_t)current_dest,
 335                         offs < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
 336                         &ecc_errors);
 337                 offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
 338         }
 339         return ecc_errors ? -1 : 0;
 340 }
 341
 342 void nand_deselect(void)
 343 {
 344         struct sunxi_ccm_reg *const ccm =
 345                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 346
 347         clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
 348 #ifdef CONFIG_MACH_SUN9I
 349         clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
 350 #else
 351         clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
 352 #endif
 353         clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
 354 }