2 * Copyright (c) 2014-2015, Antmicro Ltd <www.antmicro.com>
3 * Copyright (c) 2015, AW-SOM Technologies <www.aw-som.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
15 #define NFC_CTL 0x00000000
16 #define NFC_ST 0x00000004
17 #define NFC_INT 0x00000008
18 #define NFC_TIMING_CTL 0x0000000C
19 #define NFC_TIMING_CFG 0x00000010
20 #define NFC_ADDR_LOW 0x00000014
21 #define NFC_ADDR_HIGH 0x00000018
22 #define NFC_SECTOR_NUM 0x0000001C
23 #define NFC_CNT 0x00000020
24 #define NFC_CMD 0x00000024
25 #define NFC_RCMD_SET 0x00000028
26 #define NFC_WCMD_SET 0x0000002C
27 #define NFC_IO_DATA 0x00000030
28 #define NFC_ECC_CTL 0x00000034
29 #define NFC_ECC_ST 0x00000038
30 #define NFC_DEBUG 0x0000003C
31 #define NFC_ECC_CNT0 0x00000040
32 #define NFC_ECC_CNT1 0x00000044
33 #define NFC_ECC_CNT2 0x00000048
34 #define NFC_ECC_CNT3 0x0000004C
35 #define NFC_USER_DATA_BASE 0x00000050
36 #define NFC_EFNAND_STATUS 0x00000090
37 #define NFC_SPARE_AREA 0x000000A0
38 #define NFC_PATTERN_ID 0x000000A4
39 #define NFC_RAM0_BASE 0x00000400
40 #define NFC_RAM1_BASE 0x00000800
42 #define NFC_CTL_EN (1 << 0)
43 #define NFC_CTL_RESET (1 << 1)
44 #define NFC_CTL_RAM_METHOD (1 << 14)
47 #define NFC_ECC_EN (1 << 0)
48 #define NFC_ECC_PIPELINE (1 << 3)
49 #define NFC_ECC_EXCEPTION (1 << 4)
50 #define NFC_ECC_BLOCK_SIZE (1 << 5)
51 #define NFC_ECC_RANDOM_EN (1 << 9)
52 #define NFC_ECC_RANDOM_DIRECTION (1 << 10)
55 #define NFC_ADDR_NUM_OFFSET 16
56 #define NFC_SEND_ADR (1 << 19)
57 #define NFC_ACCESS_DIR (1 << 20)
58 #define NFC_DATA_TRANS (1 << 21)
59 #define NFC_SEND_CMD1 (1 << 22)
60 #define NFC_WAIT_FLAG (1 << 23)
61 #define NFC_SEND_CMD2 (1 << 24)
62 #define NFC_SEQ (1 << 25)
63 #define NFC_DATA_SWAP_METHOD (1 << 26)
64 #define NFC_ROW_AUTO_INC (1 << 27)
65 #define NFC_SEND_CMD3 (1 << 28)
66 #define NFC_SEND_CMD4 (1 << 29)
68 #define NFC_CMD_INT_FLAG (1 << 1)
70 #define NFC_READ_CMD_OFFSET 0
71 #define NFC_RANDOM_READ_CMD0_OFFSET 8
72 #define NFC_RANDOM_READ_CMD1_OFFSET 16
74 #define NFC_CMD_RNDOUTSTART 0xE0
75 #define NFC_CMD_RNDOUT 0x05
76 #define NFC_CMD_READSTART 0x30
79 #define NFC_PAGE_CMD (2 << 30)
81 #define SUNXI_DMA_CFG_REG0 0x300
82 #define SUNXI_DMA_SRC_START_ADDR_REG0 0x304
83 #define SUNXI_DMA_DEST_START_ADDRR_REG0 0x308
84 #define SUNXI_DMA_DDMA_BC_REG0 0x30C
85 #define SUNXI_DMA_DDMA_PARA_REG0 0x318
87 #define SUNXI_DMA_DDMA_CFG_REG_LOADING (1 << 31)
88 #define SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32 (2 << 25)
89 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM (1 << 16)
90 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32 (2 << 9)
91 #define SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO (1 << 5)
92 #define SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC (3 << 0)
94 #define SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC (0x0F << 0)
95 #define SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE (0x7F << 8)
97 /* minimal "boot0" style NAND support for Allwinner A20 */
99 /* random seed used by linux */
100 const uint16_t random_seed[128] = {
101 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
102 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
103 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
104 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
105 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
106 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
107 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
108 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
109 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
110 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
111 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
112 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
113 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
114 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
115 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
116 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
119 /* random seed used for syndrome calls */
120 const uint16_t random_seed_syndrome = 0x4a80;
122 #define MAX_RETRIES 10
124 static int check_value_inner(int offset, int expected_bits,
125 int max_number_of_retries, int negation)
129 int val = readl(offset) & expected_bits;
130 if (negation ? !val : val)
134 } while (retries < max_number_of_retries);
139 static inline int check_value(int offset, int expected_bits,
140 int max_number_of_retries)
142 return check_value_inner(offset, expected_bits,
143 max_number_of_retries, 0);
146 static inline int check_value_negated(int offset, int unexpected_bits,
147 int max_number_of_retries)
149 return check_value_inner(offset, unexpected_bits,
150 max_number_of_retries, 1);
159 val = readl(SUNXI_NFC_BASE + NFC_CTL);
160 /* enable and reset CTL */
161 writel(val | NFC_CTL_EN | NFC_CTL_RESET,
162 SUNXI_NFC_BASE + NFC_CTL);
164 if (!check_value_negated(SUNXI_NFC_BASE + NFC_CTL,
165 NFC_CTL_RESET, MAX_RETRIES)) {
166 printf("Couldn't initialize nand\n");
170 writel(NFC_SEND_CMD1 | NFC_WAIT_FLAG | NAND_CMD_RESET,
171 SUNXI_NFC_BASE + NFC_CMD);
173 if (!check_value(SUNXI_NFC_BASE + NFC_ST, NFC_CMD_INT_FLAG,
175 printf("Error timeout waiting for nand reset\n");
180 static void nand_read_page(unsigned int real_addr, dma_addr_t dst,
181 int syndrome, uint32_t *ecc_errors)
185 uint16_t ecc_mode = 0;
191 switch (CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH) {
234 printf("Unsupported ECC strength (%d)!\n",
235 CONFIG_NAND_SUNXI_SPL_ECC_STRENGTH);
239 page = real_addr / CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
240 column = real_addr % CONFIG_NAND_SUNXI_SPL_PAGE_SIZE;
243 column += (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
246 /* clear ecc status */
247 writel(0, SUNXI_NFC_BASE + NFC_ECC_ST);
249 /* Choose correct seed */
251 rand_seed = random_seed_syndrome;
253 rand_seed = random_seed[page % 128];
255 writel((rand_seed << 16) | NFC_ECC_RANDOM_EN | NFC_ECC_EN
256 | NFC_ECC_PIPELINE | (ecc_mode << 12),
257 SUNXI_NFC_BASE + NFC_ECC_CTL);
259 val = readl(SUNXI_NFC_BASE + NFC_CTL);
260 writel(val | NFC_CTL_RAM_METHOD, SUNXI_NFC_BASE + NFC_CTL);
263 oob_offset = CONFIG_NAND_SUNXI_SPL_PAGE_SIZE
264 + (column / CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE)
266 writel(oob_offset, SUNXI_NFC_BASE + NFC_SPARE_AREA);
270 writel(0x0, SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0); /* clr dma cmd */
271 /* read from REG_IO_DATA */
272 writel(SUNXI_NFC_BASE + NFC_IO_DATA,
273 SUNXI_DMA_BASE + SUNXI_DMA_SRC_START_ADDR_REG0);
275 writel(dst, SUNXI_DMA_BASE + SUNXI_DMA_DEST_START_ADDRR_REG0);
276 writel(SUNXI_DMA_DDMA_PARA_REG_SRC_WAIT_CYC
277 | SUNXI_DMA_DDMA_PARA_REG_SRC_BLK_SIZE,
278 SUNXI_DMA_BASE + SUNXI_DMA_DDMA_PARA_REG0);
279 writel(CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE,
280 SUNXI_DMA_BASE + SUNXI_DMA_DDMA_BC_REG0); /* 1kB */
281 writel(SUNXI_DMA_DDMA_CFG_REG_LOADING
282 | SUNXI_DMA_DDMA_CFG_REG_DMA_DEST_DATA_WIDTH_32
283 | SUNXI_DMA_DDMA_CFG_REG_DDMA_DST_DRQ_TYPE_DRAM
284 | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_DATA_WIDTH_32
285 | SUNXI_DMA_DDMA_CFG_REG_DMA_SRC_ADDR_MODE_IO
286 | SUNXI_DMA_DDMA_CFG_REG_DDMA_SRC_DRQ_TYPE_NFC,
287 SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0);
289 writel((NFC_CMD_RNDOUTSTART << NFC_RANDOM_READ_CMD1_OFFSET)
290 | (NFC_CMD_RNDOUT << NFC_RANDOM_READ_CMD0_OFFSET)
291 | (NFC_CMD_READSTART | NFC_READ_CMD_OFFSET), SUNXI_NFC_BASE
293 writel(1, SUNXI_NFC_BASE + NFC_SECTOR_NUM);
294 writel(((page & 0xFFFF) << 16) | column,
295 SUNXI_NFC_BASE + NFC_ADDR_LOW);
296 writel((page >> 16) & 0xFF, SUNXI_NFC_BASE + NFC_ADDR_HIGH);
297 writel(NFC_SEND_CMD1 | NFC_SEND_CMD2 | NFC_DATA_TRANS |
298 NFC_PAGE_CMD | NFC_WAIT_FLAG | (4 << NFC_ADDR_NUM_OFFSET) |
299 NFC_SEND_ADR | NFC_DATA_SWAP_METHOD | (syndrome ? NFC_SEQ : 0),
300 SUNXI_NFC_BASE + NFC_CMD);
302 if (!check_value(SUNXI_NFC_BASE + NFC_ST, (1 << 2),
304 printf("Error while initializing dma interrupt\n");
308 if (!check_value_negated(SUNXI_DMA_BASE + SUNXI_DMA_CFG_REG0,
309 SUNXI_DMA_DDMA_CFG_REG_LOADING, MAX_RETRIES)) {
310 printf("Error while waiting for dma transfer to finish\n");
314 if (readl(SUNXI_NFC_BASE + NFC_ECC_ST))
318 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
321 uint32_t ecc_errors = 0;
323 for (current_dest = dest;
324 current_dest < (dest + size);
325 current_dest += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE) {
326 nand_read_page(offs, (dma_addr_t)current_dest,
327 offs < CONFIG_NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END,
329 offs += CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE;
331 return ecc_errors ? -1 : 0;
334 void nand_deselect(void)
336 struct sunxi_ccm_reg *const ccm =
337 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
339 clrbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
340 #ifdef CONFIG_MACH_SUN9I
341 clrbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
343 clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
345 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);