drivers/mtd/nand/tegra_nand.c

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * (C) Copyright 2011 NVIDIA Corporation <www.nvidia.com>
   4  * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
   5  * (C) Copyright 2006 DENX Software Engineering
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <nand.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/funcmux.h>
  15 #include <asm/arch-tegra/clk_rst.h>
  16 #include <asm/errno.h>
  17 #include <asm/gpio.h>
  18 #include <fdtdec.h>
  19 #include <bouncebuf.h>
  20 #include "tegra_nand.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #define NAND_CMD_TIMEOUT_MS             10
  25
  26 #define SKIPPED_SPARE_BYTES             4
  27
  28 /* ECC bytes to be generated for tag data */
  29 #define TAG_ECC_BYTES                   4
  30
  31 /* 64 byte oob block info for large page (== 2KB) device
  32  *
  33  * OOB flash layout for Tegra with Reed-Solomon 4 symbol correct ECC:
  34  *      Skipped bytes(4)
  35  *      Main area Ecc(36)
  36  *      Tag data(20)
  37  *      Tag data Ecc(4)
  38  *
  39  * Yaffs2 will use 16 tag bytes.
  40  */
  41 static struct nand_ecclayout eccoob = {
  42         .eccbytes = 36,
  43         .eccpos = {
  44                 4,  5,  6,  7,  8,  9,  10, 11, 12,
  45                 13, 14, 15, 16, 17, 18, 19, 20, 21,
  46                 22, 23, 24, 25, 26, 27, 28, 29, 30,
  47                 31, 32, 33, 34, 35, 36, 37, 38, 39,
  48         },
  49         .oobavail = 20,
  50         .oobfree = {
  51                         {
  52                         .offset = 40,
  53                         .length = 20,
  54                         },
  55         }
  56 };
  57
  58 enum {
  59         ECC_OK,
  60         ECC_TAG_ERROR = 1 << 0,
  61         ECC_DATA_ERROR = 1 << 1
  62 };
  63
  64 /* Timing parameters */
  65 enum {
  66         FDT_NAND_MAX_TRP_TREA,
  67         FDT_NAND_TWB,
  68         FDT_NAND_MAX_TCR_TAR_TRR,
  69         FDT_NAND_TWHR,
  70         FDT_NAND_MAX_TCS_TCH_TALS_TALH,
  71         FDT_NAND_TWH,
  72         FDT_NAND_TWP,
  73         FDT_NAND_TRH,
  74         FDT_NAND_TADL,
  75
  76         FDT_NAND_TIMING_COUNT
  77 };
  78
  79 /* Information about an attached NAND chip */
  80 struct fdt_nand {
  81         struct nand_ctlr *reg;
  82         int enabled;            /* 1 to enable, 0 to disable */
  83         struct gpio_desc wp_gpio;       /* write-protect GPIO */
  84         s32 width;              /* bit width, normally 8 */
  85         u32 timing[FDT_NAND_TIMING_COUNT];
  86 };
  87
  88 struct nand_drv {
  89         struct nand_ctlr *reg;
  90         struct fdt_nand config;
  91 };
  92
  93 static struct nand_drv nand_ctrl;
  94 static struct mtd_info *our_mtd;
  95 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  96
  97 /**
  98  * Wait for command completion
  99  *
 100  * @param reg   nand_ctlr structure
 101  * @return
 102  *      1 - Command completed
 103  *      0 - Timeout
 104  */
 105 static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
 106 {
 107         u32 reg_val;
 108         int running;
 109         int i;
 110
 111         for (i = 0; i < NAND_CMD_TIMEOUT_MS * 1000; i++) {
 112                 if ((readl(&reg->command) & CMD_GO) ||
 113                                 !(readl(&reg->status) & STATUS_RBSY0) ||
 114                                 !(readl(&reg->isr) & ISR_IS_CMD_DONE)) {
 115                         udelay(1);
 116                         continue;
 117                 }
 118                 reg_val = readl(&reg->dma_mst_ctrl);
 119                 /*
 120                  * If DMA_MST_CTRL_EN_A_ENABLE or DMA_MST_CTRL_EN_B_ENABLE
 121                  * is set, that means DMA engine is running.
 122                  *
 123                  * Then we have to wait until DMA_MST_CTRL_IS_DMA_DONE
 124                  * is cleared, indicating DMA transfer completion.
 125                  */
 126                 running = reg_val & (DMA_MST_CTRL_EN_A_ENABLE |
 127                                 DMA_MST_CTRL_EN_B_ENABLE);
 128                 if (!running || (reg_val & DMA_MST_CTRL_IS_DMA_DONE))
 129                         return 1;
 130                 udelay(1);
 131         }
 132         return 0;
 133 }
 134
 135 /**
 136  * Read one byte from the chip
 137  *
 138  * @param mtd   MTD device structure
 139  * @return      data byte
 140  *
 141  * Read function for 8bit bus-width
 142  */
 143 static uint8_t read_byte(struct mtd_info *mtd)
 144 {
 145         struct nand_chip *chip = mtd->priv;
 146         struct nand_drv *info;
 147
 148         info = (struct nand_drv *)chip->priv;
 149
 150         writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
 151                &info->reg->command);
 152         if (!nand_waitfor_cmd_completion(info->reg))
 153                 printf("Command timeout\n");
 154
 155         return (uint8_t)readl(&info->reg->resp);
 156 }
 157
 158 /**
 159  * Read len bytes from the chip into a buffer
 160  *
 161  * @param mtd   MTD device structure
 162  * @param buf   buffer to store data to
 163  * @param len   number of bytes to read
 164  *
 165  * Read function for 8bit bus-width
 166  */
 167 static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 168 {
 169         int i, s;
 170         unsigned int reg;
 171         struct nand_chip *chip = mtd->priv;
 172         struct nand_drv *info = (struct nand_drv *)chip->priv;
 173
 174         for (i = 0; i < len; i += 4) {
 175                 s = (len - i) > 4 ? 4 : len - i;
 176                 writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
 177                         ((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
 178                         &info->reg->command);
 179                 if (!nand_waitfor_cmd_completion(info->reg))
 180                         puts("Command timeout during read_buf\n");
 181                 reg = readl(&info->reg->resp);
 182                 memcpy(buf + i, &reg, s);
 183         }
 184 }
 185
 186 /**
 187  * Check NAND status to see if it is ready or not
 188  *
 189  * @param mtd   MTD device structure
 190  * @return
 191  *      1 - ready
 192  *      0 - not ready
 193  */
 194 static int nand_dev_ready(struct mtd_info *mtd)
 195 {
 196         struct nand_chip *chip = mtd->priv;
 197         int reg_val;
 198         struct nand_drv *info;
 199
 200         info = (struct nand_drv *)chip->priv;
 201
 202         reg_val = readl(&info->reg->status);
 203         if (reg_val & STATUS_RBSY0)
 204                 return 1;
 205         else
 206                 return 0;
 207 }
 208
 209 /* Dummy implementation: we don't support multiple chips */
 210 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 211 {
 212         switch (chipnr) {
 213         case -1:
 214         case 0:
 215                 break;
 216
 217         default:
 218                 BUG();
 219         }
 220 }
 221
 222 /**
 223  * Clear all interrupt status bits
 224  *
 225  * @param reg   nand_ctlr structure
 226  */
 227 static void nand_clear_interrupt_status(struct nand_ctlr *reg)
 228 {
 229         u32 reg_val;
 230
 231         /* Clear interrupt status */
 232         reg_val = readl(&reg->isr);
 233         writel(reg_val, &reg->isr);
 234 }
 235
 236 /**
 237  * Send command to NAND device
 238  *
 239  * @param mtd           MTD device structure
 240  * @param command       the command to be sent
 241  * @param column        the column address for this command, -1 if none
 242  * @param page_addr     the page address for this command, -1 if none
 243  */
 244 static void nand_command(struct mtd_info *mtd, unsigned int command,
 245         int column, int page_addr)
 246 {
 247         struct nand_chip *chip = mtd->priv;
 248         struct nand_drv *info;
 249
 250         info = (struct nand_drv *)chip->priv;
 251
 252         /*
 253          * Write out the command to the device.
 254          *
 255          * Only command NAND_CMD_RESET or NAND_CMD_READID will come
 256          * here before mtd->writesize is initialized.
 257          */
 258
 259         /* Emulate NAND_CMD_READOOB */
 260         if (command == NAND_CMD_READOOB) {
 261                 assert(mtd->writesize != 0);
 262                 column += mtd->writesize;
 263                 command = NAND_CMD_READ0;
 264         }
 265
 266         /* Adjust columns for 16 bit bus-width */
 267         if (column != -1 && (chip->options & NAND_BUSWIDTH_16))
 268                 column >>= 1;
 269
 270         nand_clear_interrupt_status(info->reg);
 271
 272         /* Stop DMA engine, clear DMA completion status */
 273         writel(DMA_MST_CTRL_EN_A_DISABLE
 274                 | DMA_MST_CTRL_EN_B_DISABLE
 275                 | DMA_MST_CTRL_IS_DMA_DONE,
 276                 &info->reg->dma_mst_ctrl);
 277
 278         /*
 279          * Program and erase have their own busy handlers
 280          * status and sequential in needs no delay
 281          */
 282         switch (command) {
 283         case NAND_CMD_READID:
 284                 writel(NAND_CMD_READID, &info->reg->cmd_reg1);
 285                 writel(column & 0xFF, &info->reg->addr_reg1);
 286                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 287                        &info->reg->command);
 288                 break;
 289         case NAND_CMD_PARAM:
 290                 writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
 291                 writel(column & 0xFF, &info->reg->addr_reg1);
 292                 writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
 293                         &info->reg->command);
 294                 break;
 295         case NAND_CMD_READ0:
 296                 writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
 297                 writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
 298                 writel((page_addr << 16) | (column & 0xFFFF),
 299                         &info->reg->addr_reg1);
 300                 writel(page_addr >> 16, &info->reg->addr_reg2);
 301                 return;
 302         case NAND_CMD_SEQIN:
 303                 writel(NAND_CMD_SEQIN, &info->reg->cmd_reg1);
 304                 writel(NAND_CMD_PAGEPROG, &info->reg->cmd_reg2);
 305                 writel((page_addr << 16) | (column & 0xFFFF),
 306                         &info->reg->addr_reg1);
 307                 writel(page_addr >> 16,
 308                         &info->reg->addr_reg2);
 309                 return;
 310         case NAND_CMD_PAGEPROG:
 311                 return;
 312         case NAND_CMD_ERASE1:
 313                 writel(NAND_CMD_ERASE1, &info->reg->cmd_reg1);
 314                 writel(NAND_CMD_ERASE2, &info->reg->cmd_reg2);
 315                 writel(page_addr, &info->reg->addr_reg1);
 316                 writel(CMD_GO | CMD_CLE | CMD_ALE |
 317                         CMD_SEC_CMD | CMD_CE0 | CMD_ALE_BYTES3,
 318                         &info->reg->command);
 319                 break;
 320         case NAND_CMD_ERASE2:
 321                 return;
 322         case NAND_CMD_STATUS:
 323                 writel(NAND_CMD_STATUS, &info->reg->cmd_reg1);
 324                 writel(CMD_GO | CMD_CLE | CMD_PIO | CMD_RX
 325                         | ((1 - 0) << CMD_TRANS_SIZE_SHIFT)
 326                         | CMD_CE0,
 327                         &info->reg->command);
 328                 break;
 329         case NAND_CMD_RESET:
 330                 writel(NAND_CMD_RESET, &info->reg->cmd_reg1);
 331                 writel(CMD_GO | CMD_CLE | CMD_CE0,
 332                         &info->reg->command);
 333                 break;
 334         case NAND_CMD_RNDOUT:
 335         default:
 336                 printf("%s: Unsupported command %d\n", __func__, command);
 337                 return;
 338         }
 339         if (!nand_waitfor_cmd_completion(info->reg))
 340                 printf("Command 0x%02X timeout\n", command);
 341 }
 342
 343 /**
 344  * Check whether the pointed buffer are all 0xff (blank).
 345  *
 346  * @param buf   data buffer for blank check
 347  * @param len   length of the buffer in byte
 348  * @return
 349  *      1 - blank
 350  *      0 - non-blank
 351  */
 352 static int blank_check(u8 *buf, int len)
 353 {
 354         int i;
 355
 356         for (i = 0; i < len; i++)
 357                 if (buf[i] != 0xFF)
 358                         return 0;
 359         return 1;
 360 }
 361
 362 /**
 363  * After a DMA transfer for read, we call this function to see whether there
 364  * is any uncorrectable error on the pointed data buffer or oob buffer.
 365  *
 366  * @param reg           nand_ctlr structure
 367  * @param databuf       data buffer
 368  * @param a_len         data buffer length
 369  * @param oobbuf        oob buffer
 370  * @param b_len         oob buffer length
 371  * @return
 372  *      ECC_OK - no ECC error or correctable ECC error
 373  *      ECC_TAG_ERROR - uncorrectable tag ECC error
 374  *      ECC_DATA_ERROR - uncorrectable data ECC error
 375  *      ECC_DATA_ERROR + ECC_TAG_ERROR - uncorrectable data+tag ECC error
 376  */
 377 static int check_ecc_error(struct nand_ctlr *reg, u8 *databuf,
 378         int a_len, u8 *oobbuf, int b_len)
 379 {
 380         int return_val = ECC_OK;
 381         u32 reg_val;
 382
 383         if (!(readl(&reg->isr) & ISR_IS_ECC_ERR))
 384                 return ECC_OK;
 385
 386         /*
 387          * Area A is used for the data block (databuf). Area B is used for
 388          * the spare block (oobbuf)
 389          */
 390         reg_val = readl(&reg->dec_status);
 391         if ((reg_val & DEC_STATUS_A_ECC_FAIL) && databuf) {
 392                 reg_val = readl(&reg->bch_dec_status_buf);
 393                 /*
 394                  * If uncorrectable error occurs on data area, then see whether
 395                  * they are all FF. If all are FF, it's a blank page.
 396                  * Not error.
 397                  */
 398                 if ((reg_val & BCH_DEC_STATUS_FAIL_SEC_FLAG_MASK) &&
 399                                 !blank_check(databuf, a_len))
 400                         return_val |= ECC_DATA_ERROR;
 401         }
 402
 403         if ((reg_val & DEC_STATUS_B_ECC_FAIL) && oobbuf) {
 404                 reg_val = readl(&reg->bch_dec_status_buf);
 405                 /*
 406                  * If uncorrectable error occurs on tag area, then see whether
 407                  * they are all FF. If all are FF, it's a blank page.
 408                  * Not error.
 409                  */
 410                 if ((reg_val & BCH_DEC_STATUS_FAIL_TAG_MASK) &&
 411                                 !blank_check(oobbuf, b_len))
 412                         return_val |= ECC_TAG_ERROR;
 413         }
 414
 415         return return_val;
 416 }
 417
 418 /**
 419  * Set GO bit to send command to device
 420  *
 421  * @param reg   nand_ctlr structure
 422  */
 423 static void start_command(struct nand_ctlr *reg)
 424 {
 425         u32 reg_val;
 426
 427         reg_val = readl(&reg->command);
 428         reg_val |= CMD_GO;
 429         writel(reg_val, &reg->command);
 430 }
 431
 432 /**
 433  * Clear command GO bit, DMA GO bit, and DMA completion status
 434  *
 435  * @param reg   nand_ctlr structure
 436  */
 437 static void stop_command(struct nand_ctlr *reg)
 438 {
 439         /* Stop command */
 440         writel(0, &reg->command);
 441
 442         /* Stop DMA engine and clear DMA completion status */
 443         writel(DMA_MST_CTRL_GO_DISABLE
 444                 | DMA_MST_CTRL_IS_DMA_DONE,
 445                 &reg->dma_mst_ctrl);
 446 }
 447
 448 /**
 449  * Set up NAND bus width and page size
 450  *
 451  * @param info          nand_info structure
 452  * @param *reg_val      address of reg_val
 453  * @return 0 if ok, -1 on error
 454  */
 455 static int set_bus_width_page_size(struct fdt_nand *config,
 456         u32 *reg_val)
 457 {
 458         if (config->width == 8)
 459                 *reg_val = CFG_BUS_WIDTH_8BIT;
 460         else if (config->width == 16)
 461                 *reg_val = CFG_BUS_WIDTH_16BIT;
 462         else {
 463                 debug("%s: Unsupported bus width %d\n", __func__,
 464                       config->width);
 465                 return -1;
 466         }
 467
 468         if (our_mtd->writesize == 512)
 469                 *reg_val |= CFG_PAGE_SIZE_512;
 470         else if (our_mtd->writesize == 2048)
 471                 *reg_val |= CFG_PAGE_SIZE_2048;
 472         else if (our_mtd->writesize == 4096)
 473                 *reg_val |= CFG_PAGE_SIZE_4096;
 474         else {
 475                 debug("%s: Unsupported page size %d\n", __func__,
 476                       our_mtd->writesize);
 477                 return -1;
 478         }
 479
 480         return 0;
 481 }
 482
 483 /**
 484  * Page read/write function
 485  *
 486  * @param mtd           mtd info structure
 487  * @param chip          nand chip info structure
 488  * @param buf           data buffer
 489  * @param page          page number
 490  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 491  * @param is_writing    0 for read, 1 for write
 492  * @return      0 when successfully completed
 493  *              -EIO when command timeout
 494  */
 495 static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 496         uint8_t *buf, int page, int with_ecc, int is_writing)
 497 {
 498         u32 reg_val;
 499         int tag_size;
 500         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 501         /* 4*128=512 (byte) is the value that our HW can support. */
 502         ALLOC_CACHE_ALIGN_BUFFER(u32, tag_buf, 128);
 503         char *tag_ptr;
 504         struct nand_drv *info;
 505         struct fdt_nand *config;
 506         unsigned int bbflags;
 507         struct bounce_buffer bbstate, bbstate_oob;
 508
 509         if ((uintptr_t)buf & 0x03) {
 510                 printf("buf %p has to be 4-byte aligned\n", buf);
 511                 return -EINVAL;
 512         }
 513
 514         info = (struct nand_drv *)chip->priv;
 515         config = &info->config;
 516         if (set_bus_width_page_size(config, &reg_val))
 517                 return -EINVAL;
 518
 519         /* Need to be 4-byte aligned */
 520         tag_ptr = (char *)tag_buf;
 521
 522         stop_command(info->reg);
 523
 524         if (is_writing)
 525                 bbflags = GEN_BB_READ;
 526         else
 527                 bbflags = GEN_BB_WRITE;
 528
 529         bounce_buffer_start(&bbstate, (void *)buf, 1 << chip->page_shift,
 530                             bbflags);
 531         writel((1 << chip->page_shift) - 1, &info->reg->dma_cfg_a);
 532         writel(virt_to_phys(bbstate.bounce_buffer), &info->reg->data_block_ptr);
 533
 534         /* Set ECC selection, configure ECC settings */
 535         if (with_ecc) {
 536                 if (is_writing)
 537                         memcpy(tag_ptr, chip->oob_poi + free->offset,
 538                                chip->ecc.layout->oobavail + TAG_ECC_BYTES);
 539                 tag_size = chip->ecc.layout->oobavail + TAG_ECC_BYTES;
 540                 reg_val |= (CFG_SKIP_SPARE_SEL_4
 541                         | CFG_SKIP_SPARE_ENABLE
 542                         | CFG_HW_ECC_CORRECTION_ENABLE
 543                         | CFG_ECC_EN_TAG_DISABLE
 544                         | CFG_HW_ECC_SEL_RS
 545                         | CFG_HW_ECC_ENABLE
 546                         | CFG_TVAL4
 547                         | (tag_size - 1));
 548
 549                 if (!is_writing)
 550                         tag_size += SKIPPED_SPARE_BYTES;
 551                 bounce_buffer_start(&bbstate_oob, (void *)tag_ptr, tag_size,
 552                                     bbflags);
 553         } else {
 554                 tag_size = mtd->oobsize;
 555                 reg_val |= (CFG_SKIP_SPARE_DISABLE
 556                         | CFG_HW_ECC_CORRECTION_DISABLE
 557                         | CFG_ECC_EN_TAG_DISABLE
 558                         | CFG_HW_ECC_DISABLE
 559                         | (tag_size - 1));
 560                 bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi,
 561                                     tag_size, bbflags);
 562         }
 563         writel(reg_val, &info->reg->config);
 564         writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
 565         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 566         writel(tag_size - 1, &info->reg->dma_cfg_b);
 567
 568         nand_clear_interrupt_status(info->reg);
 569
 570         reg_val = CMD_CLE | CMD_ALE
 571                 | CMD_SEC_CMD
 572                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 573                 | CMD_A_VALID
 574                 | CMD_B_VALID
 575                 | (CMD_TRANS_SIZE_PAGE << CMD_TRANS_SIZE_SHIFT)
 576                 | CMD_CE0;
 577         if (!is_writing)
 578                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 579         else
 580                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 581         writel(reg_val, &info->reg->command);
 582
 583         /* Setup DMA engine */
 584         reg_val = DMA_MST_CTRL_GO_ENABLE
 585                 | DMA_MST_CTRL_BURST_8WORDS
 586                 | DMA_MST_CTRL_EN_A_ENABLE
 587                 | DMA_MST_CTRL_EN_B_ENABLE;
 588
 589         if (!is_writing)
 590                 reg_val |= DMA_MST_CTRL_DIR_READ;
 591         else
 592                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 593
 594         writel(reg_val, &info->reg->dma_mst_ctrl);
 595
 596         start_command(info->reg);
 597
 598         if (!nand_waitfor_cmd_completion(info->reg)) {
 599                 if (!is_writing)
 600                         printf("Read Page 0x%X timeout ", page);
 601                 else
 602                         printf("Write Page 0x%X timeout ", page);
 603                 if (with_ecc)
 604                         printf("with ECC");
 605                 else
 606                         printf("without ECC");
 607                 printf("\n");
 608                 return -EIO;
 609         }
 610
 611         bounce_buffer_stop(&bbstate_oob);
 612         bounce_buffer_stop(&bbstate);
 613
 614         if (with_ecc && !is_writing) {
 615                 memcpy(chip->oob_poi, tag_ptr,
 616                         SKIPPED_SPARE_BYTES);
 617                 memcpy(chip->oob_poi + free->offset,
 618                         tag_ptr + SKIPPED_SPARE_BYTES,
 619                         chip->ecc.layout->oobavail);
 620                 reg_val = (u32)check_ecc_error(info->reg, (u8 *)buf,
 621                         1 << chip->page_shift,
 622                         (u8 *)(tag_ptr + SKIPPED_SPARE_BYTES),
 623                         chip->ecc.layout->oobavail);
 624                 if (reg_val & ECC_TAG_ERROR)
 625                         printf("Read Page 0x%X tag ECC error\n", page);
 626                 if (reg_val & ECC_DATA_ERROR)
 627                         printf("Read Page 0x%X data ECC error\n",
 628                                 page);
 629                 if (reg_val & (ECC_DATA_ERROR | ECC_TAG_ERROR))
 630                         return -EIO;
 631         }
 632         return 0;
 633 }
 634
 635 /**
 636  * Hardware ecc based page read function
 637  *
 638  * @param mtd   mtd info structure
 639  * @param chip  nand chip info structure
 640  * @param buf   buffer to store read data
 641  * @param page  page number to read
 642  * @return      0 when successfully completed
 643  *              -EIO when command timeout
 644  */
 645 static int nand_read_page_hwecc(struct mtd_info *mtd,
 646         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 647 {
 648         return nand_rw_page(mtd, chip, buf, page, 1, 0);
 649 }
 650
 651 /**
 652  * Hardware ecc based page write function
 653  *
 654  * @param mtd   mtd info structure
 655  * @param chip  nand chip info structure
 656  * @param buf   data buffer
 657  */
 658 static int nand_write_page_hwecc(struct mtd_info *mtd,
 659         struct nand_chip *chip, const uint8_t *buf, int oob_required)
 660 {
 661         int page;
 662         struct nand_drv *info;
 663
 664         info = (struct nand_drv *)chip->priv;
 665
 666         page = (readl(&info->reg->addr_reg1) >> 16) |
 667                 (readl(&info->reg->addr_reg2) << 16);
 668
 669         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
 670         return 0;
 671 }
 672
 673
 674 /**
 675  * Read raw page data without ecc
 676  *
 677  * @param mtd   mtd info structure
 678  * @param chip  nand chip info structure
 679  * @param buf   buffer to store read data
 680  * @param page  page number to read
 681  * @return      0 when successfully completed
 682  *              -EINVAL when chip->oob_poi is not double-word aligned
 683  *              -EIO when command timeout
 684  */
 685 static int nand_read_page_raw(struct mtd_info *mtd,
 686         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 687 {
 688         return nand_rw_page(mtd, chip, buf, page, 0, 0);
 689 }
 690
 691 /**
 692  * Raw page write function
 693  *
 694  * @param mtd   mtd info structure
 695  * @param chip  nand chip info structure
 696  * @param buf   data buffer
 697  */
 698 static int nand_write_page_raw(struct mtd_info *mtd,
 699                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 700 {
 701         int page;
 702         struct nand_drv *info;
 703
 704         info = (struct nand_drv *)chip->priv;
 705         page = (readl(&info->reg->addr_reg1) >> 16) |
 706                 (readl(&info->reg->addr_reg2) << 16);
 707
 708         nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
 709         return 0;
 710 }
 711
 712 /**
 713  * OOB data read/write function
 714  *
 715  * @param mtd           mtd info structure
 716  * @param chip          nand chip info structure
 717  * @param page          page number to read
 718  * @param with_ecc      1 to enable ECC, 0 to disable ECC
 719  * @param is_writing    0 for read, 1 for write
 720  * @return      0 when successfully completed
 721  *              -EINVAL when chip->oob_poi is not double-word aligned
 722  *              -EIO when command timeout
 723  */
 724 static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 725         int page, int with_ecc, int is_writing)
 726 {
 727         u32 reg_val;
 728         int tag_size;
 729         struct nand_oobfree *free = chip->ecc.layout->oobfree;
 730         struct nand_drv *info;
 731         unsigned int bbflags;
 732         struct bounce_buffer bbstate_oob;
 733
 734         if (((int)chip->oob_poi) & 0x03)
 735                 return -EINVAL;
 736         info = (struct nand_drv *)chip->priv;
 737         if (set_bus_width_page_size(&info->config, &reg_val))
 738                 return -EINVAL;
 739
 740         stop_command(info->reg);
 741
 742         /* Set ECC selection */
 743         tag_size = mtd->oobsize;
 744         if (with_ecc)
 745                 reg_val |= CFG_ECC_EN_TAG_ENABLE;
 746         else
 747                 reg_val |= (CFG_ECC_EN_TAG_DISABLE);
 748
 749         reg_val |= ((tag_size - 1) |
 750                 CFG_SKIP_SPARE_DISABLE |
 751                 CFG_HW_ECC_CORRECTION_DISABLE |
 752                 CFG_HW_ECC_DISABLE);
 753         writel(reg_val, &info->reg->config);
 754
 755         if (is_writing && with_ecc)
 756                 tag_size -= TAG_ECC_BYTES;
 757
 758         if (is_writing)
 759                 bbflags = GEN_BB_READ;
 760         else
 761                 bbflags = GEN_BB_WRITE;
 762
 763         bounce_buffer_start(&bbstate_oob, (void *)chip->oob_poi, tag_size,
 764                             bbflags);
 765         writel(virt_to_phys(bbstate_oob.bounce_buffer), &info->reg->tag_ptr);
 766
 767         writel(BCH_CONFIG_BCH_ECC_DISABLE, &info->reg->bch_config);
 768
 769         writel(tag_size - 1, &info->reg->dma_cfg_b);
 770
 771         nand_clear_interrupt_status(info->reg);
 772
 773         reg_val = CMD_CLE | CMD_ALE
 774                 | CMD_SEC_CMD
 775                 | (CMD_ALE_BYTES5 << CMD_ALE_BYTE_SIZE_SHIFT)
 776                 | CMD_B_VALID
 777                 | CMD_CE0;
 778         if (!is_writing)
 779                 reg_val |= (CMD_AFT_DAT_DISABLE | CMD_RX);
 780         else
 781                 reg_val |= (CMD_AFT_DAT_ENABLE | CMD_TX);
 782         writel(reg_val, &info->reg->command);
 783
 784         /* Setup DMA engine */
 785         reg_val = DMA_MST_CTRL_GO_ENABLE
 786                 | DMA_MST_CTRL_BURST_8WORDS
 787                 | DMA_MST_CTRL_EN_B_ENABLE;
 788         if (!is_writing)
 789                 reg_val |= DMA_MST_CTRL_DIR_READ;
 790         else
 791                 reg_val |= DMA_MST_CTRL_DIR_WRITE;
 792
 793         writel(reg_val, &info->reg->dma_mst_ctrl);
 794
 795         start_command(info->reg);
 796
 797         if (!nand_waitfor_cmd_completion(info->reg)) {
 798                 if (!is_writing)
 799                         printf("Read OOB of Page 0x%X timeout\n", page);
 800                 else
 801                         printf("Write OOB of Page 0x%X timeout\n", page);
 802                 return -EIO;
 803         }
 804
 805         bounce_buffer_stop(&bbstate_oob);
 806
 807         if (with_ecc && !is_writing) {
 808                 reg_val = (u32)check_ecc_error(info->reg, 0, 0,
 809                         (u8 *)(chip->oob_poi + free->offset),
 810                         chip->ecc.layout->oobavail);
 811                 if (reg_val & ECC_TAG_ERROR)
 812                         printf("Read OOB of Page 0x%X tag ECC error\n", page);
 813         }
 814         return 0;
 815 }
 816
 817 /**
 818  * OOB data read function
 819  *
 820  * @param mtd           mtd info structure
 821  * @param chip          nand chip info structure
 822  * @param page          page number to read
 823  */
 824 static int nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 825         int page)
 826 {
 827         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 828         nand_rw_oob(mtd, chip, page, 0, 0);
 829         return 0;
 830 }
 831
 832 /**
 833  * OOB data write function
 834  *
 835  * @param mtd   mtd info structure
 836  * @param chip  nand chip info structure
 837  * @param page  page number to write
 838  * @return      0 when successfully completed
 839  *              -EINVAL when chip->oob_poi is not double-word aligned
 840  *              -EIO when command timeout
 841  */
 842 static int nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
 843         int page)
 844 {
 845         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 846
 847         return nand_rw_oob(mtd, chip, page, 0, 1);
 848 }
 849
 850 /**
 851  * Set up NAND memory timings according to the provided parameters
 852  *
 853  * @param timing        Timing parameters
 854  * @param reg           NAND controller register address
 855  */
 856 static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT],
 857                          struct nand_ctlr *reg)
 858 {
 859         u32 reg_val, clk_rate, clk_period, time_val;
 860
 861         clk_rate = (u32)clock_get_periph_rate(PERIPH_ID_NDFLASH,
 862                 CLOCK_ID_PERIPH) / 1000000;
 863         clk_period = 1000 / clk_rate;
 864         reg_val = ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 865                 TIMING_TRP_RESP_CNT_SHIFT) & TIMING_TRP_RESP_CNT_MASK;
 866         reg_val |= ((timing[FDT_NAND_TWB] / clk_period) <<
 867                 TIMING_TWB_CNT_SHIFT) & TIMING_TWB_CNT_MASK;
 868         time_val = timing[FDT_NAND_MAX_TCR_TAR_TRR] / clk_period;
 869         if (time_val > 2)
 870                 reg_val |= ((time_val - 2) << TIMING_TCR_TAR_TRR_CNT_SHIFT) &
 871                         TIMING_TCR_TAR_TRR_CNT_MASK;
 872         reg_val |= ((timing[FDT_NAND_TWHR] / clk_period) <<
 873                 TIMING_TWHR_CNT_SHIFT) & TIMING_TWHR_CNT_MASK;
 874         time_val = timing[FDT_NAND_MAX_TCS_TCH_TALS_TALH] / clk_period;
 875         if (time_val > 1)
 876                 reg_val |= ((time_val - 1) << TIMING_TCS_CNT_SHIFT) &
 877                         TIMING_TCS_CNT_MASK;
 878         reg_val |= ((timing[FDT_NAND_TWH] / clk_period) <<
 879                 TIMING_TWH_CNT_SHIFT) & TIMING_TWH_CNT_MASK;
 880         reg_val |= ((timing[FDT_NAND_TWP] / clk_period) <<
 881                 TIMING_TWP_CNT_SHIFT) & TIMING_TWP_CNT_MASK;
 882         reg_val |= ((timing[FDT_NAND_TRH] / clk_period) <<
 883                 TIMING_TRH_CNT_SHIFT) & TIMING_TRH_CNT_MASK;
 884         reg_val |= ((timing[FDT_NAND_MAX_TRP_TREA] / clk_period) <<
 885                 TIMING_TRP_CNT_SHIFT) & TIMING_TRP_CNT_MASK;
 886         writel(reg_val, &reg->timing);
 887
 888         reg_val = 0;
 889         time_val = timing[FDT_NAND_TADL] / clk_period;
 890         if (time_val > 2)
 891                 reg_val = (time_val - 2) & TIMING2_TADL_CNT_MASK;
 892         writel(reg_val, &reg->timing2);
 893 }
 894
 895 /**
 896  * Decode NAND parameters from the device tree
 897  *
 898  * @param blob  Device tree blob
 899  * @param node  Node containing "nand-flash" compatble node
 900  * @return 0 if ok, -ve on error (FDT_ERR_...)
 901  */
 902 static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config)
 903 {
 904         int err;
 905
 906         config->reg = (struct nand_ctlr *)fdtdec_get_addr(blob, node, "reg");
 907         config->enabled = fdtdec_get_is_enabled(blob, node);
 908         config->width = fdtdec_get_int(blob, node, "nvidia,nand-width", 8);
 909         err = gpio_request_by_name_nodev(blob, node, "nvidia,wp-gpios", 0,
 910                                  &config->wp_gpio, GPIOD_IS_OUT);
 911         if (err)
 912                 return err;
 913         err = fdtdec_get_int_array(blob, node, "nvidia,timing",
 914                         config->timing, FDT_NAND_TIMING_COUNT);
 915         if (err < 0)
 916                 return err;
 917
 918         /* Now look up the controller and decode that */
 919         node = fdt_next_node(blob, node, NULL);
 920         if (node < 0)
 921                 return node;
 922
 923         return 0;
 924 }
 925
 926 /**
 927  * Board-specific NAND initialization
 928  *
 929  * @param nand  nand chip info structure
 930  * @return 0, after initialized, -1 on error
 931  */
 932 int tegra_nand_init(struct nand_chip *nand, int devnum)
 933 {
 934         struct nand_drv *info = &nand_ctrl;
 935         struct fdt_nand *config = &info->config;
 936         int node, ret;
 937
 938         node = fdtdec_next_compatible(gd->fdt_blob, 0,
 939                                       COMPAT_NVIDIA_TEGRA20_NAND);
 940         if (node < 0)
 941                 return -1;
 942         if (fdt_decode_nand(gd->fdt_blob, node, config)) {
 943                 printf("Could not decode nand-flash in device tree\n");
 944                 return -1;
 945         }
 946         if (!config->enabled)
 947                 return -1;
 948         info->reg = config->reg;
 949         nand->ecc.mode = NAND_ECC_HW;
 950         nand->ecc.layout = &eccoob;
 951
 952         nand->options = LP_OPTIONS;
 953         nand->cmdfunc = nand_command;
 954         nand->read_byte = read_byte;
 955         nand->read_buf = read_buf;
 956         nand->ecc.read_page = nand_read_page_hwecc;
 957         nand->ecc.write_page = nand_write_page_hwecc;
 958         nand->ecc.read_page_raw = nand_read_page_raw;
 959         nand->ecc.write_page_raw = nand_write_page_raw;
 960         nand->ecc.read_oob = nand_read_oob;
 961         nand->ecc.write_oob = nand_write_oob;
 962         nand->ecc.strength = 1;
 963         nand->select_chip = nand_select_chip;
 964         nand->dev_ready  = nand_dev_ready;
 965         nand->priv = &nand_ctrl;
 966
 967         /* Disable subpage writes as we do not provide ecc->hwctl */
 968         nand->options |= NAND_NO_SUBPAGE_WRITE;
 969
 970         /* Adjust controller clock rate */
 971         clock_start_periph_pll(PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH, 52000000);
 972
 973         /* Adjust timing for NAND device */
 974         setup_timing(config->timing, info->reg);
 975
 976         dm_gpio_set_value(&config->wp_gpio, 1);
 977
 978         our_mtd = &nand_info[devnum];
 979         our_mtd->priv = nand;
 980         ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 981         if (ret)
 982                 return ret;
 983
 984         nand->ecc.size = our_mtd->writesize;
 985         nand->ecc.bytes = our_mtd->oobsize;
 986
 987         ret = nand_scan_tail(our_mtd);
 988         if (ret)
 989                 return ret;
 990
 991         ret = nand_register(devnum);
 992         if (ret)
 993                 return ret;
 994
 995         return 0;
 996 }
 997
 998 void board_nand_init(void)
 999 {
1000         struct nand_chip *nand = &nand_chip[0];
1001
1002         if (tegra_nand_init(nand, 0))
1003                 puts("Tegra NAND init failed\n");
1004 }