drivers/mtd/spi/sf_internal.h

   1 /*
   2  * SPI flash internal definitions
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   6  *
   7  * Licensed under the GPL-2 or later.
   8  */
   9
  10 #ifndef _SPI_FLASH_INTERNAL_H_
  11 #define _SPI_FLASH_INTERNAL_H_
  12
  13 #define SPI_FLASH_16MB_BOUN             0x1000000
  14
  15 /* SECT flags */
  16 #define SECT_4K                         (1 << 1)
  17 #define SECT_32K                        (1 << 2)
  18 #define E_FSR                           (1 << 3)
  19
  20 /* Erase commands */
  21 #define CMD_ERASE_4K                    0x20
  22 #define CMD_ERASE_32K                   0x52
  23 #define CMD_ERASE_CHIP                  0xc7
  24 #define CMD_ERASE_64K                   0xd8
  25
  26 /* Write commands */
  27 #define CMD_WRITE_STATUS                0x01
  28 #define CMD_PAGE_PROGRAM                0x02
  29 #define CMD_WRITE_DISABLE               0x04
  30 #define CMD_READ_STATUS                 0x05
  31 #define CMD_WRITE_ENABLE                0x06
  32 #define CMD_READ_CONFIG                 0x35
  33 #define CMD_FLAG_STATUS                 0x70
  34
  35 /* Read commands */
  36 #define CMD_READ_ARRAY_SLOW             0x03
  37 #define CMD_READ_ARRAY_FAST             0x0b
  38 #define CMD_READ_ID                     0x9f
  39
  40 /* Bank addr access commands */
  41 #ifdef CONFIG_SPI_FLASH_BAR
  42 # define CMD_BANKADDR_BRWR              0x17
  43 # define CMD_BANKADDR_BRRD              0x16
  44 # define CMD_EXTNADDR_WREAR             0xC5
  45 # define CMD_EXTNADDR_RDEAR             0xC8
  46 #endif
  47
  48 /* Common status */
  49 #define STATUS_WIP                      0x01
  50 #define STATUS_PEC                      0x80
  51
  52 /* Flash timeout values */
  53 #define SPI_FLASH_PROG_TIMEOUT          (2 * CONFIG_SYS_HZ)
  54 #define SPI_FLASH_PAGE_ERASE_TIMEOUT    (5 * CONFIG_SYS_HZ)
  55 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT  (10 * CONFIG_SYS_HZ)
  56
  57 /* SST specific */
  58 #ifdef CONFIG_SPI_FLASH_SST
  59 # define SST_WP                 0x01    /* Supports AAI word program */
  60 # define CMD_SST_BP             0x02    /* Byte Program */
  61 # define CMD_SST_AAI_WP         0xAD    /* Auto Address Incr Word Program */
  62
  63 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
  64                 const void *buf);
  65 #endif
  66
  67 /* Send a single-byte command to the device and read the response */
  68 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
  69
  70 /*
  71  * Send a multi-byte command to the device and read the response. Used
  72  * for flash array reads, etc.
  73  */
  74 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
  75                 size_t cmd_len, void *data, size_t data_len);
  76
  77 /*
  78  * Send a multi-byte command to the device followed by (optional)
  79  * data. Used for programming the flash array, etc.
  80  */
  81 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
  82                 const void *data, size_t data_len);
  83
  84
  85 /* Flash erase(sectors) operation, support all possible erase commands */
  86 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
  87
  88 /* Program the status register */
  89 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
  90
  91 /* Set quad enbale bit */
  92 int spi_flash_set_qeb(struct spi_flash *flash);
  93
  94 /* Enable writing on the SPI flash */
  95 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
  96 {
  97         return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
  98 }
  99
 100 /* Disable writing on the SPI flash */
 101 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 102 {
 103         return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
 104 }
 105
 106 /*
 107  * Send the read status command to the device and wait for the wip
 108  * (write-in-progress) bit to clear itself.
 109  */
 110 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
 111
 112 /*
 113  * Used for spi_flash write operation
 114  * - SPI claim
 115  * - spi_flash_cmd_write_enable
 116  * - spi_flash_cmd_write
 117  * - spi_flash_cmd_wait_ready
 118  * - SPI release
 119  */
 120 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 121                 size_t cmd_len, const void *buf, size_t buf_len);
 122
 123 /*
 124  * Flash write operation, support all possible write commands.
 125  * Write the requested data out breaking it up into multiple write
 126  * commands as needed per the write size.
 127  */
 128 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 129                 size_t len, const void *buf);
 130
 131 /*
 132  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
 133  * bus. Used as common part of the ->read() operation.
 134  */
 135 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 136                 size_t cmd_len, void *data, size_t data_len);
 137
 138 /* Flash read operation, support all possible read commands */
 139 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 140                 size_t len, void *data);
 141
 142 #endif /* _SPI_FLASH_INTERNAL_H_ */