drivers/mtd/spi/sf_internal.h

   1 /*
   2  * SPI flash internal definitions
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _SF_INTERNAL_H_
  11 #define _SF_INTERNAL_H_
  12
  13 #define SPI_FLASH_16MB_BOUN             0x1000000
  14
  15 /* CFI Manufacture ID's */
  16 #define SPI_FLASH_CFI_MFR_SPANSION      0x01
  17 #define SPI_FLASH_CFI_MFR_STMICRO       0x20
  18 #define SPI_FLASH_CFI_MFR_WINBOND       0xef
  19
  20 /* SECT flags */
  21 #define SECT_4K                         (1 << 1)
  22 #define SECT_32K                        (1 << 2)
  23 #define E_FSR                           (1 << 3)
  24
  25 /* Erase commands */
  26 #define CMD_ERASE_4K                    0x20
  27 #define CMD_ERASE_32K                   0x52
  28 #define CMD_ERASE_CHIP                  0xc7
  29 #define CMD_ERASE_64K                   0xd8
  30
  31 /* Write commands */
  32 #define CMD_WRITE_STATUS                0x01
  33 #define CMD_PAGE_PROGRAM                0x02
  34 #define CMD_WRITE_DISABLE               0x04
  35 #define CMD_READ_STATUS                 0x05
  36 #define CMD_QUAD_PAGE_PROGRAM           0x32
  37 #define CMD_READ_STATUS1                0x35
  38 #define CMD_WRITE_ENABLE                0x06
  39 #define CMD_READ_CONFIG                 0x35
  40 #define CMD_FLAG_STATUS                 0x70
  41
  42 /* Read commands */
  43 #define CMD_READ_ARRAY_SLOW             0x03
  44 #define CMD_READ_ARRAY_FAST             0x0b
  45 #define CMD_READ_DUAL_OUTPUT_FAST       0x3b
  46 #define CMD_READ_DUAL_IO_FAST           0xbb
  47 #define CMD_READ_QUAD_OUTPUT_FAST       0x6b
  48 #define CMD_READ_QUAD_IO_FAST           0xeb
  49 #define CMD_READ_ID                     0x9f
  50
  51 /* Bank addr access commands */
  52 #ifdef CONFIG_SPI_FLASH_BAR
  53 # define CMD_BANKADDR_BRWR              0x17
  54 # define CMD_BANKADDR_BRRD              0x16
  55 # define CMD_EXTNADDR_WREAR             0xC5
  56 # define CMD_EXTNADDR_RDEAR             0xC8
  57 #endif
  58
  59 /* Common status */
  60 #define STATUS_WIP                      0x01
  61 #define STATUS_QEB_WINSPAN              (1 << 1)
  62 #define STATUS_PEC                      0x80
  63
  64 /* Flash timeout values */
  65 #define SPI_FLASH_PROG_TIMEOUT          (2 * CONFIG_SYS_HZ)
  66 #define SPI_FLASH_PAGE_ERASE_TIMEOUT    (5 * CONFIG_SYS_HZ)
  67 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT  (10 * CONFIG_SYS_HZ)
  68
  69 /* SST specific */
  70 #ifdef CONFIG_SPI_FLASH_SST
  71 # define SST_WP                 0x01    /* Supports AAI word program */
  72 # define CMD_SST_BP             0x02    /* Byte Program */
  73 # define CMD_SST_AAI_WP         0xAD    /* Auto Address Incr Word Program */
  74
  75 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
  76                 const void *buf);
  77 #endif
  78
  79 /* Send a single-byte command to the device and read the response */
  80 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
  81
  82 /*
  83  * Send a multi-byte command to the device and read the response. Used
  84  * for flash array reads, etc.
  85  */
  86 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
  87                 size_t cmd_len, void *data, size_t data_len);
  88
  89 /*
  90  * Send a multi-byte command to the device followed by (optional)
  91  * data. Used for programming the flash array, etc.
  92  */
  93 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
  94                 const void *data, size_t data_len);
  95
  96
  97 /* Flash erase(sectors) operation, support all possible erase commands */
  98 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
  99
 100 /* Program the status register */
 101 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
 102
 103 /* Set quad enbale bit for winbond and spansion flashes */
 104 int spi_flash_set_qeb_winspan(struct spi_flash *flash);
 105
 106 /* Enable writing on the SPI flash */
 107 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
 108 {
 109         return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
 110 }
 111
 112 /* Disable writing on the SPI flash */
 113 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 114 {
 115         return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
 116 }
 117
 118 /*
 119  * Send the read status command to the device and wait for the wip
 120  * (write-in-progress) bit to clear itself.
 121  */
 122 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
 123
 124 /*
 125  * Used for spi_flash write operation
 126  * - SPI claim
 127  * - spi_flash_cmd_write_enable
 128  * - spi_flash_cmd_write
 129  * - spi_flash_cmd_wait_ready
 130  * - SPI release
 131  */
 132 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 133                 size_t cmd_len, const void *buf, size_t buf_len);
 134
 135 /*
 136  * Flash write operation, support all possible write commands.
 137  * Write the requested data out breaking it up into multiple write
 138  * commands as needed per the write size.
 139  */
 140 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 141                 size_t len, const void *buf);
 142
 143 /*
 144  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
 145  * bus. Used as common part of the ->read() operation.
 146  */
 147 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 148                 size_t cmd_len, void *data, size_t data_len);
 149
 150 /* Flash read operation, support all possible read commands */
 151 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 152                 size_t len, void *data);
 153
 154 #endif /* _SF_INTERNAL_H_ */