drivers/mtd/spi/sf_internal.h

   1 /*
   2  * SPI flash internal definitions
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _SF_INTERNAL_H_
  11 #define _SF_INTERNAL_H_
  12
  13 #define SPI_FLASH_3B_ADDR_LEN           3
  14 #define SPI_FLASH_CMD_LEN               (1 + SPI_FLASH_3B_ADDR_LEN)
  15 #define SPI_FLASH_16MB_BOUN             0x1000000
  16
  17 /* CFI Manufacture ID's */
  18 #define SPI_FLASH_CFI_MFR_SPANSION      0x01
  19 #define SPI_FLASH_CFI_MFR_STMICRO       0x20
  20 #define SPI_FLASH_CFI_MFR_WINBOND       0xef
  21
  22 /* SECT flags */
  23 #define SECT_4K                         (1 << 1)
  24 #define SECT_32K                        (1 << 2)
  25 #define E_FSR                           (1 << 3)
  26
  27 /* Erase commands */
  28 #define CMD_ERASE_4K                    0x20
  29 #define CMD_ERASE_32K                   0x52
  30 #define CMD_ERASE_CHIP                  0xc7
  31 #define CMD_ERASE_64K                   0xd8
  32
  33 /* Write commands */
  34 #define CMD_WRITE_STATUS                0x01
  35 #define CMD_PAGE_PROGRAM                0x02
  36 #define CMD_WRITE_DISABLE               0x04
  37 #define CMD_READ_STATUS                 0x05
  38 #define CMD_QUAD_PAGE_PROGRAM           0x32
  39 #define CMD_READ_STATUS1                0x35
  40 #define CMD_WRITE_ENABLE                0x06
  41 #define CMD_READ_CONFIG                 0x35
  42 #define CMD_FLAG_STATUS                 0x70
  43
  44 /* Read commands */
  45 #define CMD_READ_ARRAY_SLOW             0x03
  46 #define CMD_READ_ARRAY_FAST             0x0b
  47 #define CMD_READ_DUAL_OUTPUT_FAST       0x3b
  48 #define CMD_READ_DUAL_IO_FAST           0xbb
  49 #define CMD_READ_QUAD_OUTPUT_FAST       0x6b
  50 #define CMD_READ_QUAD_IO_FAST           0xeb
  51 #define CMD_READ_ID                     0x9f
  52
  53 /* Bank addr access commands */
  54 #ifdef CONFIG_SPI_FLASH_BAR
  55 # define CMD_BANKADDR_BRWR              0x17
  56 # define CMD_BANKADDR_BRRD              0x16
  57 # define CMD_EXTNADDR_WREAR             0xC5
  58 # define CMD_EXTNADDR_RDEAR             0xC8
  59 #endif
  60
  61 /* Common status */
  62 #define STATUS_WIP                      0x01
  63 #define STATUS_QEB_WINSPAN              (1 << 1)
  64 #define STATUS_PEC                      0x80
  65
  66 /* Flash timeout values */
  67 #define SPI_FLASH_PROG_TIMEOUT          (2 * CONFIG_SYS_HZ)
  68 #define SPI_FLASH_PAGE_ERASE_TIMEOUT    (5 * CONFIG_SYS_HZ)
  69 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT  (10 * CONFIG_SYS_HZ)
  70
  71 /* SST specific */
  72 #ifdef CONFIG_SPI_FLASH_SST
  73 # define SST_WP                 0x01    /* Supports AAI word program */
  74 # define CMD_SST_BP             0x02    /* Byte Program */
  75 # define CMD_SST_AAI_WP         0xAD    /* Auto Address Incr Word Program */
  76
  77 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
  78                 const void *buf);
  79 #endif
  80
  81 /* Send a single-byte command to the device and read the response */
  82 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
  83
  84 /*
  85  * Send a multi-byte command to the device and read the response. Used
  86  * for flash array reads, etc.
  87  */
  88 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
  89                 size_t cmd_len, void *data, size_t data_len);
  90
  91 /*
  92  * Send a multi-byte command to the device followed by (optional)
  93  * data. Used for programming the flash array, etc.
  94  */
  95 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
  96                 const void *data, size_t data_len);
  97
  98
  99 /* Flash erase(sectors) operation, support all possible erase commands */
 100 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
 101
 102 /* Program the status register */
 103 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
 104
 105 /* Set quad enbale bit for winbond and spansion flashes */
 106 int spi_flash_set_qeb_winspan(struct spi_flash *flash);
 107
 108 /* Enable writing on the SPI flash */
 109 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
 110 {
 111         return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
 112 }
 113
 114 /* Disable writing on the SPI flash */
 115 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 116 {
 117         return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
 118 }
 119
 120 /*
 121  * Send the read status command to the device and wait for the wip
 122  * (write-in-progress) bit to clear itself.
 123  */
 124 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout);
 125
 126 /*
 127  * Used for spi_flash write operation
 128  * - SPI claim
 129  * - spi_flash_cmd_write_enable
 130  * - spi_flash_cmd_write
 131  * - spi_flash_cmd_wait_ready
 132  * - SPI release
 133  */
 134 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 135                 size_t cmd_len, const void *buf, size_t buf_len);
 136
 137 /*
 138  * Flash write operation, support all possible write commands.
 139  * Write the requested data out breaking it up into multiple write
 140  * commands as needed per the write size.
 141  */
 142 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 143                 size_t len, const void *buf);
 144
 145 /*
 146  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
 147  * bus. Used as common part of the ->read() operation.
 148  */
 149 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 150                 size_t cmd_len, void *data, size_t data_len);
 151
 152 /* Flash read operation, support all possible read commands */
 153 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 154                 size_t len, void *data);
 155
 156 #endif /* _SF_INTERNAL_H_ */