drivers/net/cpsw.c

   1 /*
   2  * CPSW Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <common.h>
  17 #include <command.h>
  18 #include <cpsw.h>
  19 #include <net.h>
  20 #include <miiphy.h>
  21 #include <malloc.h>
  22 #include <net.h>
  23 #include <netdev.h>
  24 #include <asm/errno.h>
  25 #include <asm/io.h>
  26 #include <phy.h>
  27 #include <asm/arch/cpu.h>
  28
  29 #define BITMASK(bits)           (BIT(bits) - 1)
  30
  31 #define PHY_REG_MASK            0x1f
  32 #define PHY_ID_MASK             0x1f
  33 #define NUM_DESCS               (PKTBUFSRX * 2)
  34 #define PKT_MIN                 60
  35 #define PKT_MAX                 (1500 + 14 + 4 + 4)
  36 #define CLEAR_BIT               1
  37
  38 /* MAC_CONTROL register bits */
  39 #define GIGABITEN               BIT(7)
  40 #define FULLDUPLEXEN            BIT(0)
  41 #define MAC_CTRL_CMD_IDLE       BIT(11)
  42 #define MIIEN                   BIT(15)
  43
  44 /* MAC_STATUS register bits */
  45 #define MAC_STAT_IDLE           BIT(31)
  46
  47 /* DMA Registers */
  48 #define CPDMA_TXCONTROL         0x004
  49 #define CPDMA_RXCONTROL         0x014
  50 #define CPDMA_SOFTRESET         0x01c
  51 #define CPDMA_DMACONTROL        0x020
  52 #define CPDMA_DMASTATUS         0x024
  53 #define CPDMA_RXFREE            0x0e0
  54 #define CPDMA_TXHDP_VER1        0x100
  55 #define CPDMA_TXHDP_VER2        0x200
  56 #define CPDMA_RXHDP_VER1        0x120
  57 #define CPDMA_RXHDP_VER2        0x220
  58 #define CPDMA_TXCP_VER1         0x140
  59 #define CPDMA_TXCP_VER2         0x240
  60 #define CPDMA_RXCP_VER1         0x160
  61 #define CPDMA_RXCP_VER2         0x260
  62
  63 #define DMACONTROL_CMD_IDLE     BIT(3)
  64
  65 #define DMASTATUS_IDLE          BIT(31)
  66
  67 /* Descriptor mode bits */
  68 #define CPDMA_DESC_SOP          BIT(31)
  69 #define CPDMA_DESC_EOP          BIT(30)
  70 #define CPDMA_DESC_OWNER        BIT(29)
  71 #define CPDMA_DESC_EOQ          BIT(28)
  72
  73 /*
  74  * This timeout definition is a worst-case ultra defensive measure against
  75  * unexpected controller lock ups.  Ideally, we should never ever hit this
  76  * scenario in practice.
  77  */
  78 #define MDIO_TIMEOUT            100 /* msecs */
  79 #define CPDMA_TIMEOUT           100 /* msecs */
  80
  81 struct cpsw_mdio_regs {
  82         u32     version;
  83         u32     control;
  84 #define CONTROL_IDLE            BIT(31)
  85 #define CONTROL_ENABLE          BIT(30)
  86
  87         u32     alive;
  88         u32     link;
  89         u32     linkintraw;
  90         u32     linkintmasked;
  91         u32     __reserved_0[2];
  92         u32     userintraw;
  93         u32     userintmasked;
  94         u32     userintmaskset;
  95         u32     userintmaskclr;
  96         u32     __reserved_1[20];
  97
  98         struct {
  99                 u32             access;
 100                 u32             physel;
 101 #define USERACCESS_GO           BIT(31)
 102 #define USERACCESS_WRITE        BIT(30)
 103 #define USERACCESS_ACK          BIT(29)
 104 #define USERACCESS_READ         0
 105 #define USERACCESS_DATA         0xffff
 106         } user[0];
 107 };
 108
 109 struct cpsw_regs {
 110         u32     id_ver;
 111         u32     control;
 112         u32     soft_reset;
 113         u32     stat_port_en;
 114         u32     ptype;
 115 };
 116
 117 struct cpsw_slave_regs {
 118         u32     max_blks;
 119         u32     blk_cnt;
 120         u32     flow_thresh;
 121         u32     port_vlan;
 122         u32     tx_pri_map;
 123 #ifdef CONFIG_AM33XX
 124         u32     gap_thresh;
 125 #elif defined(CONFIG_TI814X)
 126         u32     ts_ctl;
 127         u32     ts_seq_ltype;
 128         u32     ts_vlan;
 129 #endif
 130         u32     sa_lo;
 131         u32     sa_hi;
 132 };
 133
 134 struct cpsw_host_regs {
 135         u32     max_blks;
 136         u32     blk_cnt;
 137         u32     flow_thresh;
 138         u32     port_vlan;
 139         u32     tx_pri_map;
 140         u32     cpdma_tx_pri_map;
 141         u32     cpdma_rx_chan_map;
 142 };
 143
 144 struct cpsw_sliver_regs {
 145         u32     id_ver;
 146         u32     mac_control;
 147         u32     mac_status;
 148         u32     soft_reset;
 149         u32     rx_maxlen;
 150         u32     __reserved_0;
 151         u32     rx_pause;
 152         u32     tx_pause;
 153         u32     __reserved_1;
 154         u32     rx_pri_map;
 155 };
 156
 157 #define ALE_ENTRY_BITS          68
 158 #define ALE_ENTRY_WORDS         DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
 159
 160 /* ALE Registers */
 161 #define ALE_CONTROL             0x08
 162 #define ALE_UNKNOWNVLAN         0x18
 163 #define ALE_TABLE_CONTROL       0x20
 164 #define ALE_TABLE               0x34
 165 #define ALE_PORTCTL             0x40
 166
 167 #define ALE_TABLE_WRITE         BIT(31)
 168
 169 #define ALE_TYPE_FREE                   0
 170 #define ALE_TYPE_ADDR                   1
 171 #define ALE_TYPE_VLAN                   2
 172 #define ALE_TYPE_VLAN_ADDR              3
 173
 174 #define ALE_UCAST_PERSISTANT            0
 175 #define ALE_UCAST_UNTOUCHED             1
 176 #define ALE_UCAST_OUI                   2
 177 #define ALE_UCAST_TOUCHED               3
 178
 179 #define ALE_MCAST_FWD                   0
 180 #define ALE_MCAST_BLOCK_LEARN_FWD       1
 181 #define ALE_MCAST_FWD_LEARN             2
 182 #define ALE_MCAST_FWD_2                 3
 183
 184 enum cpsw_ale_port_state {
 185         ALE_PORT_STATE_DISABLE  = 0x00,
 186         ALE_PORT_STATE_BLOCK    = 0x01,
 187         ALE_PORT_STATE_LEARN    = 0x02,
 188         ALE_PORT_STATE_FORWARD  = 0x03,
 189 };
 190
 191 /* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
 192 #define ALE_SECURE      1
 193 #define ALE_BLOCKED     2
 194
 195 struct cpsw_slave {
 196         struct cpsw_slave_regs          *regs;
 197         struct cpsw_sliver_regs         *sliver;
 198         int                             slave_num;
 199         u32                             mac_control;
 200         struct cpsw_slave_data          *data;
 201 };
 202
 203 struct cpdma_desc {
 204         /* hardware fields */
 205         u32                     hw_next;
 206         u32                     hw_buffer;
 207         u32                     hw_len;
 208         u32                     hw_mode;
 209 } __attribute__((aligned(CONFIG_SYS_CACHELINE_SIZE)));
 210
 211 struct cpsw_desc {
 212         void *sw_buffer;
 213         struct cpsw_desc *next;
 214         struct cpdma_desc *dma_desc;
 215 };
 216
 217 struct cpdma_chan {
 218         struct cpsw_desc        *head, *tail;
 219         void                    *hdp, *cp, *rxfree;
 220 };
 221
 222 #define desc_write(desc, fld, val)      __raw_writel((u32)(val), &(desc)->dma_desc->fld)
 223 #define desc_read(desc, fld)            __raw_readl(&(desc)->dma_desc->fld)
 224 #define desc_read_ptr(desc, fld)        ((void *)__raw_readl(&(desc)->dma_desc->fld))
 225
 226 #define chan_write(chan, fld, val)      __raw_writel((u32)(val), (chan)->fld)
 227 #define chan_read(chan, fld)            __raw_readl((chan)->fld)
 228 #define chan_read_ptr(chan, fld)        ((void *)__raw_readl((chan)->fld))
 229
 230 #define for_active_slave(slave, priv) \
 231         slave = (priv)->slaves + (priv)->data->active_slave; if (slave)
 232 #define for_each_slave(slave, priv) \
 233         for (slave = (priv)->slaves; slave != (priv)->slaves + \
 234                                 (priv)->data->slaves; slave++)
 235
 236 struct cpsw_priv {
 237         struct eth_device               *dev;
 238         struct cpsw_platform_data       *data;
 239         int                             host_port;
 240
 241         struct cpsw_regs                *regs;
 242         void                            *dma_regs;
 243         struct cpsw_host_regs           *host_port_regs;
 244         void                            *ale_regs;
 245
 246         struct cpsw_desc                descs[NUM_DESCS];
 247         struct cpsw_desc                *desc_free;
 248         struct cpdma_chan               rx_chan, tx_chan;
 249
 250         struct cpsw_slave               *slaves;
 251         struct phy_device               *phydev;
 252         struct mii_dev                  *bus;
 253
 254         u32                             phy_mask;
 255 };
 256
 257 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
 258 {
 259         int idx;
 260
 261         idx    = start / 32;
 262         start -= idx * 32;
 263         idx    = 2 - idx; /* flip */
 264         return (ale_entry[idx] >> start) & BITMASK(bits);
 265 }
 266
 267 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
 268                                       u32 value)
 269 {
 270         int idx;
 271
 272         value &= BITMASK(bits);
 273         idx    = start / 32;
 274         start -= idx * 32;
 275         idx    = 2 - idx; /* flip */
 276         ale_entry[idx] &= ~(BITMASK(bits) << start);
 277         ale_entry[idx] |=  (value << start);
 278 }
 279
 280 #define DEFINE_ALE_FIELD(name, start, bits)                             \
 281 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
 282 {                                                                       \
 283         return cpsw_ale_get_field(ale_entry, start, bits);              \
 284 }                                                                       \
 285 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
 286 {                                                                       \
 287         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 288 }
 289
 290 DEFINE_ALE_FIELD(entry_type,            60,     2)
 291 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 292 DEFINE_ALE_FIELD(port_mask,             66,     3)
 293 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 294 DEFINE_ALE_FIELD(port_num,              66,     2)
 295 DEFINE_ALE_FIELD(blocked,               65,     1)
 296 DEFINE_ALE_FIELD(secure,                64,     1)
 297 DEFINE_ALE_FIELD(mcast,                 40,     1)
 298
 299 /* The MAC address field in the ALE entry cannot be macroized as above */
 300 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 301 {
 302         int i;
 303
 304         for (i = 0; i < 6; i++)
 305                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 306 }
 307
 308 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 309 {
 310         int i;
 311
 312         for (i = 0; i < 6; i++)
 313                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 314 }
 315
 316 static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 317 {
 318         int i;
 319
 320         __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
 321
 322         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 323                 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i);
 324
 325         return idx;
 326 }
 327
 328 static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
 329 {
 330         int i;
 331
 332         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 333                 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
 334
 335         __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
 336
 337         return idx;
 338 }
 339
 340 static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr)
 341 {
 342         u32 ale_entry[ALE_ENTRY_WORDS];
 343         int type, idx;
 344
 345         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 346                 u8 entry_addr[6];
 347
 348                 cpsw_ale_read(priv, idx, ale_entry);
 349                 type = cpsw_ale_get_entry_type(ale_entry);
 350                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 351                         continue;
 352                 cpsw_ale_get_addr(ale_entry, entry_addr);
 353                 if (memcmp(entry_addr, addr, 6) == 0)
 354                         return idx;
 355         }
 356         return -ENOENT;
 357 }
 358
 359 static int cpsw_ale_match_free(struct cpsw_priv *priv)
 360 {
 361         u32 ale_entry[ALE_ENTRY_WORDS];
 362         int type, idx;
 363
 364         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 365                 cpsw_ale_read(priv, idx, ale_entry);
 366                 type = cpsw_ale_get_entry_type(ale_entry);
 367                 if (type == ALE_TYPE_FREE)
 368                         return idx;
 369         }
 370         return -ENOENT;
 371 }
 372
 373 static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
 374 {
 375         u32 ale_entry[ALE_ENTRY_WORDS];
 376         int type, idx;
 377
 378         for (idx = 0; idx < priv->data->ale_entries; idx++) {
 379                 cpsw_ale_read(priv, idx, ale_entry);
 380                 type = cpsw_ale_get_entry_type(ale_entry);
 381                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 382                         continue;
 383                 if (cpsw_ale_get_mcast(ale_entry))
 384                         continue;
 385                 type = cpsw_ale_get_ucast_type(ale_entry);
 386                 if (type != ALE_UCAST_PERSISTANT &&
 387                     type != ALE_UCAST_OUI)
 388                         return idx;
 389         }
 390         return -ENOENT;
 391 }
 392
 393 static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr,
 394                               int port, int flags)
 395 {
 396         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 397         int idx;
 398
 399         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 400         cpsw_ale_set_addr(ale_entry, addr);
 401         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 402         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 403         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 404         cpsw_ale_set_port_num(ale_entry, port);
 405
 406         idx = cpsw_ale_match_addr(priv, addr);
 407         if (idx < 0)
 408                 idx = cpsw_ale_match_free(priv);
 409         if (idx < 0)
 410                 idx = cpsw_ale_find_ageable(priv);
 411         if (idx < 0)
 412                 return -ENOMEM;
 413
 414         cpsw_ale_write(priv, idx, ale_entry);
 415         return 0;
 416 }
 417
 418 static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr,
 419                               int port_mask)
 420 {
 421         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 422         int idx, mask;
 423
 424         idx = cpsw_ale_match_addr(priv, addr);
 425         if (idx >= 0)
 426                 cpsw_ale_read(priv, idx, ale_entry);
 427
 428         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 429         cpsw_ale_set_addr(ale_entry, addr);
 430         cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
 431
 432         mask = cpsw_ale_get_port_mask(ale_entry);
 433         port_mask |= mask;
 434         cpsw_ale_set_port_mask(ale_entry, port_mask);
 435
 436         if (idx < 0)
 437                 idx = cpsw_ale_match_free(priv);
 438         if (idx < 0)
 439                 idx = cpsw_ale_find_ageable(priv);
 440         if (idx < 0)
 441                 return -ENOMEM;
 442
 443         cpsw_ale_write(priv, idx, ale_entry);
 444         return 0;
 445 }
 446
 447 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
 448 {
 449         u32 tmp, mask = BIT(bit);
 450
 451         tmp  = __raw_readl(priv->ale_regs + ALE_CONTROL);
 452         tmp &= ~mask;
 453         tmp |= val ? mask : 0;
 454         __raw_writel(tmp, priv->ale_regs + ALE_CONTROL);
 455 }
 456
 457 #define cpsw_ale_enable(priv, val)      cpsw_ale_control(priv, 31, val)
 458 #define cpsw_ale_clear(priv, val)       cpsw_ale_control(priv, 30, val)
 459 #define cpsw_ale_vlan_aware(priv, val)  cpsw_ale_control(priv,  2, val)
 460
 461 static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
 462                                        int val)
 463 {
 464         int offset = ALE_PORTCTL + 4 * port;
 465         u32 tmp, mask = 0x3;
 466
 467         tmp  = __raw_readl(priv->ale_regs + offset);
 468         tmp &= ~mask;
 469         tmp |= val & mask;
 470         __raw_writel(tmp, priv->ale_regs + offset);
 471 }
 472
 473 static struct cpsw_mdio_regs *mdio_regs;
 474
 475 /* wait until hardware is ready for another user access */
 476 static inline u32 wait_for_user_access(void)
 477 {
 478         int timeout = MDIO_TIMEOUT;
 479         u32 reg;
 480
 481         while ((reg = __raw_readl(&mdio_regs->user[0].access)) & USERACCESS_GO) {
 482                 udelay(1000);
 483                 if (--timeout <= 0) {
 484                         printf("TIMEOUT waiting for USERACCESS_GO\n");
 485                         break;
 486                 }
 487         }
 488
 489         return reg;
 490 }
 491
 492 /* wait until hardware state machine is idle */
 493 static inline void wait_for_idle(void)
 494 {
 495         int timeout = MDIO_TIMEOUT;
 496
 497         while ((__raw_readl(&mdio_regs->control) & CONTROL_IDLE) == 0) {
 498                 if (--timeout <= 0) {
 499                         printf("TIMEOUT waiting for state machine idle\n");
 500                         break;
 501                 }
 502                 udelay(1000);
 503         }
 504 }
 505
 506 static int cpsw_mdio_read(struct mii_dev *bus, int phy_id,
 507                                 int dev_addr, int phy_reg)
 508 {
 509         int data;
 510         u32 reg;
 511
 512         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 513                 return -EINVAL;
 514
 515         if (wait_for_user_access() & USERACCESS_GO)
 516                 /* promote error from previous access */
 517                 return -ETIME;
 518
 519         reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
 520                (phy_id << 16));
 521         __raw_writel(reg, &mdio_regs->user[0].access);
 522         reg = wait_for_user_access();
 523         if (reg & USERACCESS_GO)
 524                 return -ETIME;
 525
 526         data = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -1;
 527         return data;
 528 }
 529
 530 static int cpsw_mdio_write(struct mii_dev *bus, int phy_id, int dev_addr,
 531                                 int phy_reg, u16 data)
 532 {
 533         u32 reg;
 534
 535         if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
 536                 return -EINVAL;
 537
 538         if (wait_for_user_access() & USERACCESS_GO)
 539                 /* promote error from previous access */
 540                 return -ETIME;
 541
 542         reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
 543                    (phy_id << 16) | (data & USERACCESS_DATA));
 544         __raw_writel(reg, &mdio_regs->user[0].access);
 545         if (wait_for_user_access() & USERACCESS_GO)
 546                 return -ETIME;
 547
 548         return 0;
 549 }
 550
 551 static void cpsw_mdio_init(char *name, u32 mdio_base, u32 div)
 552 {
 553         struct mii_dev *bus = mdio_alloc();
 554
 555         mdio_regs = (struct cpsw_mdio_regs *)mdio_base;
 556
 557         /* set enable and clock divider */
 558         __raw_writel(div | CONTROL_ENABLE, &mdio_regs->control);
 559
 560         /*
 561          * wait for scan logic to settle:
 562          * the scan time consists of (a) a large fixed component, and (b) a
 563          * small component that varies with the mii bus frequency.  These
 564          * were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
 565          * silicon.  Since the effect of (b) was found to be largely
 566          * negligible, we keep things simple here.
 567          */
 568         udelay(1000);
 569
 570         bus->read = cpsw_mdio_read;
 571         bus->write = cpsw_mdio_write;
 572         sprintf(bus->name, name);
 573
 574         mdio_register(bus);
 575 }
 576
 577 /* Set a self-clearing bit in a register, and wait for it to clear */
 578 static inline void setbit_and_wait_for_clear32(void *addr)
 579 {
 580         int loops = 0;
 581
 582         __raw_writel(CLEAR_BIT, addr);
 583         while (__raw_readl(addr) & CLEAR_BIT)
 584                 loops++;
 585         debug("%s: reset finished after %u loops\n", __func__, loops);
 586 }
 587
 588 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 589                          ((mac)[2] << 16) | ((mac)[3] << 24))
 590 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 591
 592 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 593                                struct cpsw_priv *priv)
 594 {
 595         __raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
 596         __raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
 597 }
 598
 599 #define NUM_TRIES 50
 600 static void cpsw_slave_update_link(struct cpsw_slave *slave,
 601                                    struct cpsw_priv *priv, int *link)
 602 {
 603         struct phy_device *phy = priv->phydev;
 604         u32 mac_control = 0;
 605         int retries = NUM_TRIES;
 606
 607         do {
 608                 phy_startup(phy);
 609                 *link = phy->link;
 610
 611                 if (*link) { /* link up */
 612                         mac_control = priv->data->mac_control;
 613                         if (phy->speed == 1000)
 614                                 mac_control |= GIGABITEN;
 615                         if (phy->duplex == DUPLEX_FULL)
 616                                 mac_control |= FULLDUPLEXEN;
 617                         if (phy->speed == 100)
 618                                 mac_control |= MIIEN;
 619                 } else {
 620                         udelay(10000);
 621                 }
 622         } while (!*link && retries-- > 0);
 623         debug("%s: mac_control: %08x -> %08x after %u loops\n", __func__,
 624                 slave->mac_control, mac_control, NUM_TRIES - retries);
 625
 626         if (mac_control == slave->mac_control)
 627                 return;
 628
 629         if (mac_control) {
 630                 printf("link up on port %d, speed %d, %s duplex\n",
 631                                 slave->slave_num, phy->speed,
 632                                 (phy->duplex == DUPLEX_FULL) ? "full" : "half");
 633         } else {
 634                 printf("link down on port %d\n", slave->slave_num);
 635         }
 636
 637         __raw_writel(mac_control, &slave->sliver->mac_control);
 638         slave->mac_control = mac_control;
 639 }
 640
 641 static int cpsw_update_link(struct cpsw_priv *priv)
 642 {
 643         int link = 0;
 644         struct cpsw_slave *slave;
 645
 646         for_active_slave(slave, priv)
 647                 cpsw_slave_update_link(slave, priv, &link);
 648
 649         return link;
 650 }
 651
 652 static inline u32  cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 653 {
 654         if (priv->host_port == 0)
 655                 return slave_num + 1;
 656         else
 657                 return slave_num;
 658 }
 659
 660 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
 661 {
 662         u32     slave_port;
 663
 664         debug("%s\n", __func__);
 665         setbit_and_wait_for_clear32(&slave->sliver->soft_reset);
 666
 667         /* setup priority mapping */
 668         __raw_writel(0x76543210, &slave->sliver->rx_pri_map);
 669         __raw_writel(0x33221100, &slave->regs->tx_pri_map);
 670
 671         /* setup max packet size, and mac address */
 672         __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen);
 673         cpsw_set_slave_mac(slave, priv);
 674
 675         slave->mac_control = 0; /* no link yet */
 676
 677         /* enable forwarding */
 678         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 679         cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
 680
 681         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port);
 682
 683         priv->phy_mask |= 1 << slave->data->phy_addr;
 684 }
 685
 686 static void cpdma_desc_get(struct cpsw_desc *desc)
 687 {
 688         invalidate_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
 689 }
 690
 691 static void cpdma_desc_put(struct cpsw_desc *desc)
 692 {
 693         flush_dcache_range((u32)desc->dma_desc, (u32)(&desc->dma_desc[1]));
 694 }
 695
 696 static struct cpsw_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
 697 {
 698         struct cpsw_desc *desc = priv->desc_free;
 699
 700         if (desc) {
 701                 cpdma_desc_get(desc);
 702                 priv->desc_free = desc->next;
 703         }
 704         return desc;
 705 }
 706
 707 static void cpdma_desc_free(struct cpsw_priv *priv, struct cpsw_desc *desc)
 708 {
 709         if (desc) {
 710                 desc_write(desc, hw_next, priv->desc_free->dma_desc);
 711                 cpdma_desc_put(desc);
 712                 desc->next = priv->desc_free;
 713                 priv->desc_free = desc;
 714         }
 715 }
 716
 717 static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
 718                         void *buffer, int len)
 719 {
 720         struct cpsw_desc *desc, *prev;
 721         u32 mode;
 722
 723         if (!buffer) {
 724                 printf("ERROR: %s() NULL buffer\n", __func__);
 725                 return -EINVAL;
 726         }
 727
 728         flush_dcache_range((u32)buffer, (u32)buffer + len);
 729
 730         desc = cpdma_desc_alloc(priv);
 731         if (!desc)
 732                 return -ENOMEM;
 733
 734         debug("%s@%d: %cX desc %p DMA %p\n", __func__, __LINE__,
 735                 chan == &priv->rx_chan ? 'R' : 'T', desc, desc->dma_desc);
 736         if (len < PKT_MIN)
 737                 len = PKT_MIN;
 738
 739         mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
 740
 741         desc->next = NULL;
 742         desc_write(desc, hw_next,   0);
 743         desc_write(desc, hw_buffer, buffer);
 744         desc_write(desc, hw_len,    len);
 745         desc_write(desc, hw_mode,   mode | len);
 746
 747         desc->sw_buffer = buffer;
 748
 749         cpdma_desc_put(desc);
 750         if (!chan->head) {
 751                 /* simple case - first packet enqueued */
 752                 chan->head = desc;
 753                 chan->tail = desc;
 754                 chan_write(chan, hdp, desc->dma_desc);
 755                 goto done;
 756         }
 757
 758         /* not the first packet - enqueue at the tail */
 759         prev = chan->tail;
 760
 761         prev->next = desc;
 762         cpdma_desc_get(prev);
 763         desc_write(prev, hw_next, desc->dma_desc);
 764         cpdma_desc_put(prev);
 765
 766         chan->tail = desc;
 767
 768         /* next check if EOQ has been triggered already */
 769         if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ)
 770                 chan_write(chan, hdp, desc->dma_desc);
 771
 772 done:
 773         if (chan->rxfree)
 774                 chan_write(chan, rxfree, 1);
 775         debug("%s@%d\n", __func__, __LINE__);
 776         return 0;
 777 }
 778
 779 static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
 780                          void **buffer, int *len)
 781 {
 782         struct cpsw_desc *desc = chan->head;
 783         u32 status;
 784
 785         if (!desc)
 786                 return -ENOENT;
 787
 788         cpdma_desc_get(desc);
 789
 790         status = desc_read(desc, hw_mode);
 791         if (status & CPDMA_DESC_OWNER)
 792                 return -EBUSY;
 793
 794         if (len)
 795                 *len = status & 0x7ff;
 796
 797         if (buffer)
 798                 *buffer = desc->sw_buffer;
 799         debug("%s@%d: buffer=%p\n", __func__, __LINE__, desc->sw_buffer);
 800
 801         chan->head = desc->next;
 802         chan_write(chan, cp, desc->dma_desc);
 803
 804         cpdma_desc_free(priv, desc);
 805         return 0;
 806 }
 807
 808 static int cpsw_init(struct eth_device *dev, bd_t *bis)
 809 {
 810         struct cpsw_priv        *priv = dev->priv;
 811         struct cpsw_slave       *slave;
 812         int i, ret;
 813
 814         debug("%s\n", __func__);
 815         /* soft reset the controller and initialize priv */
 816         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 817
 818         /* initialize and reset the address lookup engine */
 819         cpsw_ale_enable(priv, 1);
 820         cpsw_ale_clear(priv, 1);
 821         cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
 822
 823         /* setup host port priority mapping */
 824         __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
 825         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 826
 827         /* disable priority elevation and enable statistics on all ports */
 828         __raw_writel(0, &priv->regs->ptype);
 829
 830         /* enable statistics collection only on the host port */
 831         __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en);
 832         __raw_writel(0x7, &priv->regs->stat_port_en);
 833
 834         cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
 835
 836         cpsw_ale_add_ucast(priv, priv->dev->enetaddr, priv->host_port,
 837                            ALE_SECURE);
 838         cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port);
 839
 840         for_active_slave(slave, priv)
 841                 cpsw_slave_init(slave, priv);
 842
 843         cpsw_update_link(priv);
 844
 845         /* init descriptor pool */
 846         for (i = 0; i < NUM_DESCS; i++) {
 847                 struct cpsw_desc *next_desc = (i < (NUM_DESCS - 1)) ?
 848                         &priv->descs[i + 1] : NULL;
 849
 850                 priv->descs[i].next = next_desc;
 851                 desc_write(&priv->descs[i], hw_next,
 852                         next_desc ? next_desc->dma_desc : 0);
 853                 cpdma_desc_put(&priv->descs[i]);
 854         }
 855         priv->desc_free = &priv->descs[0];
 856
 857         /* initialize channels */
 858         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 859                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 860                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER2;
 861                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER2;
 862                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 863
 864                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 865                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER2;
 866                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER2;
 867         } else {
 868                 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
 869                 priv->rx_chan.hdp       = priv->dma_regs + CPDMA_RXHDP_VER1;
 870                 priv->rx_chan.cp        = priv->dma_regs + CPDMA_RXCP_VER1;
 871                 priv->rx_chan.rxfree    = priv->dma_regs + CPDMA_RXFREE;
 872
 873                 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
 874                 priv->tx_chan.hdp       = priv->dma_regs + CPDMA_TXHDP_VER1;
 875                 priv->tx_chan.cp        = priv->dma_regs + CPDMA_TXCP_VER1;
 876         }
 877
 878         /* clear dma state */
 879         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 880
 881         if (priv->data->version == CPSW_CTRL_VERSION_2) {
 882                 for (i = 0; i < priv->data->channels; i++) {
 883                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 * i);
 884                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
 885                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 * i);
 886                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 * i);
 887                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 * i);
 888                 }
 889         } else {
 890                 for (i = 0; i < priv->data->channels; i++) {
 891                         __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 * i);
 892                         __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
 893                         __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 * i);
 894                         __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 * i);
 895                         __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 * i);
 896
 897                 }
 898         }
 899
 900         __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL);
 901         __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL);
 902
 903         /* submit rx descs */
 904         for (i = 0; i < PKTBUFSRX; i++) {
 905                 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i],
 906                                    PKTSIZE);
 907                 if (ret < 0) {
 908                         printf("error %d submitting rx desc\n", ret);
 909                         break;
 910                 }
 911         }
 912
 913         return ret;
 914 }
 915
 916 static void cpsw_halt(struct eth_device *dev)
 917 {
 918         struct cpsw_priv        *priv = dev->priv;
 919         struct cpsw_slave       *slave;
 920         int idle = 0;
 921         int timeout = 1000000;
 922
 923         __raw_writel(DMACONTROL_CMD_IDLE, priv->dma_regs + CPDMA_DMACONTROL);
 924         while (!(__raw_readl(priv->dma_regs + CPDMA_DMASTATUS) &
 925                         DMASTATUS_IDLE) && (--timeout >= 0))
 926                 udelay(1);
 927
 928         timeout = 1000000;
 929         while (!idle) {
 930                 idle = 1;
 931                 for_each_slave(slave, priv) {
 932                         if (!(__raw_readl(&slave->sliver->mac_status) &
 933                                         MAC_STAT_IDLE)) {
 934                                 idle = 0;
 935                                 break;
 936                         }
 937                 }
 938                 if (idle || --timeout < 0)
 939                         break;
 940                 udelay(1);
 941         }
 942         if (!idle)
 943                 printf("CPSW: Aborting DMA transfers; packets may be lost\n");
 944
 945         writel(0, priv->dma_regs + CPDMA_TXCONTROL);
 946         writel(0, priv->dma_regs + CPDMA_RXCONTROL);
 947
 948         /* soft reset the controller and initialize priv */
 949         setbit_and_wait_for_clear32(&priv->regs->soft_reset);
 950
 951         /* clear dma state */
 952         setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET);
 953
 954         debug("%s\n", __func__);
 955         priv->data->control(0);
 956 }
 957
 958 static int cpsw_send(struct eth_device *dev, void *packet, int length)
 959 {
 960         struct cpsw_priv *priv = dev->priv;
 961         void *buffer;
 962         int len;
 963
 964
 965         /* first reap completed packets */
 966         while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) == 0)
 967                 /* NOP */;
 968
 969         return cpdma_submit(priv, &priv->tx_chan, packet, length);
 970 }
 971
 972 static int cpsw_recv(struct eth_device *dev)
 973 {
 974         struct cpsw_priv        *priv = dev->priv;
 975         void *buffer;
 976         int len;
 977
 978         while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) == 0) {
 979                 if (buffer) {
 980                         net_process_received_packet(buffer, len);
 981                         cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
 982                 } else {
 983                         printf("NULL buffer returned from cpdma_process\n");
 984                         return -EIO;
 985                 }
 986         }
 987
 988         return 0;
 989 }
 990
 991 static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
 992                             struct cpsw_priv *priv)
 993 {
 994         void                    *regs = priv->regs;
 995         struct cpsw_slave_data  *data = priv->data->slave_data + slave_num;
 996
 997         debug("%s@%d: slave[%d] %p\n", __func__, __LINE__,
 998                 slave_num, slave);
 999         slave->slave_num = slave_num;
1000         slave->data     = data;
1001         slave->regs     = regs + data->slave_reg_ofs;
1002         slave->sliver   = regs + data->sliver_reg_ofs;
1003 }
1004
1005 static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
1006 {
1007         struct cpsw_priv *priv = (struct cpsw_priv *)dev->priv;
1008         struct phy_device *phydev;
1009         u32 supported = PHY_GBIT_FEATURES;
1010
1011         if (slave->data->phy_addr < 0) {
1012                 u32 phy_addr;
1013
1014                 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
1015                         debug("Trying to connect to PHY @ addr %02x\n",
1016                                 phy_addr);
1017                         phydev = phy_connect(priv->bus, phy_addr,
1018                                         dev, slave->data->phy_if);
1019                         if (phydev)
1020                                 break;
1021                 }
1022         } else {
1023                 phydev = phy_connect(priv->bus,
1024                                 slave->data->phy_addr,
1025                                 dev,
1026                                 slave->data->phy_if);
1027         }
1028         if (!phydev) {
1029                 printf("Failed to connect to PHY\n");
1030                 return -EINVAL;
1031         }
1032
1033         if (!phydev)
1034                 return -1;
1035
1036         phydev->supported &= supported;
1037         phydev->advertising = phydev->supported;
1038
1039         priv->phydev = phydev;
1040         phy_config(phydev);
1041
1042         return 0;
1043 }
1044
1045 int cpsw_register(struct cpsw_platform_data *data)
1046 {
1047         int ret = 1;
1048         struct cpsw_priv        *priv;
1049         struct cpsw_slave       *slave;
1050         void                    *regs = (void *)data->cpsw_base;
1051         struct eth_device       *dev;
1052         int idx = 0;
1053
1054         debug("%s@%d\n", __func__, __LINE__);
1055
1056         dev = calloc(sizeof(*dev), 1);
1057         if (!dev)
1058                 return -ENOMEM;
1059
1060         priv = calloc(sizeof(*priv), 1);
1061         if (!priv) {
1062                 free(dev);
1063                 return -ENOMEM;
1064         }
1065
1066         priv->data = data;
1067         priv->dev = dev;
1068
1069         priv->slaves = calloc(sizeof(struct cpsw_slave), data->slaves);
1070         if (!priv->slaves) {
1071                 free(dev);
1072                 free(priv);
1073                 return -ENOMEM;
1074         }
1075
1076         priv->host_port         = data->host_port_num;
1077         priv->regs              = regs;
1078         priv->host_port_regs    = regs + data->host_port_reg_ofs;
1079         priv->dma_regs          = regs + data->cpdma_reg_ofs;
1080         priv->ale_regs          = regs + data->ale_reg_ofs;
1081
1082         for_each_slave(slave, priv) {
1083                 cpsw_slave_setup(slave, idx, priv);
1084                 idx = idx + 1;
1085         }
1086
1087         strcpy(dev->name, "cpsw");
1088         dev->iobase     = 0;
1089         dev->init       = cpsw_init;
1090         dev->halt       = cpsw_halt;
1091         dev->send       = cpsw_send;
1092         dev->recv       = cpsw_recv;
1093         dev->priv       = priv;
1094
1095         eth_register(dev);
1096
1097         cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div);
1098         priv->bus = miiphy_get_dev_by_name(dev->name);
1099         for_active_slave(slave, priv)
1100                 ret = cpsw_phy_init(dev, slave);
1101
1102         return ret;
1103 }