2 * @file IxNpeMhMacros_p.h
4 * @author Intel Corporation
7 * @brief This file contains the macros for the IxNpeMh component.
11 * IXP400 SW Release version 2.0
13 * -- Copyright Notice --
16 * Copyright 2001-2005, Intel Corporation.
17 * All rights reserved.
20 * SPDX-License-Identifier: BSD-3-Clause
22 * -- End of Copyright Notice --
26 * @defgroup IxNpeMhMacros_p IxNpeMhMacros_p
28 * @brief Macros for the IxNpeMh component.
33 #ifndef IXNPEMHMACROS_P_H
34 #define IXNPEMHMACROS_P_H
36 /* if we are running as a unit test */
39 #endif /* #ifdef IX_UNIT_TEST */
44 * #defines for function return types, etc.
47 #define IX_NPEMH_SHOW_TEXT_WIDTH (40) /**< text width for stats display */
48 #define IX_NPEMH_SHOW_STAT_WIDTH (10) /**< stat width for stats display */
53 * @brief Macro for displaying a stat preceded by a textual description.
56 #define IX_NPEMH_SHOW(TEXT, STAT) \
57 ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, \
58 "%-40s: %10d\n", (int) TEXT, (int) STAT, 0, 0, 0, 0)
61 * Prototypes for interface functions.
65 * @typedef IxNpeMhTraceTypes
67 * @brief Enumeration defining IxNpeMh trace levels
72 IX_NPEMH_TRACE_OFF = IX_OSAL_LOG_LVL_NONE, /**< no trace */
73 IX_NPEMH_WARNING = IX_OSAL_LOG_LVL_WARNING, /**< warning */
74 IX_NPEMH_DEBUG = IX_OSAL_LOG_LVL_MESSAGE, /**< debug */
75 IX_NPEMH_FN_ENTRY_EXIT = IX_OSAL_LOG_LVL_DEBUG3 /**< function entry/exit */
79 #define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_FN_ENTRY_EXIT) /**< trace level */
81 #define IX_NPEMH_TRACE_LEVEL (IX_NPEMH_TRACE_OFF) /**< trace level */
85 * @def IX_NPEMH_TRACE0
87 * @brief Trace macro taking 0 arguments.
90 #define IX_NPEMH_TRACE0(LEVEL, STR) \
91 IX_NPEMH_TRACE6(LEVEL, STR, 0, 0, 0, 0, 0, 0)
94 * @def IX_NPEMH_TRACE1
96 * @brief Trace macro taking 1 argument.
99 #define IX_NPEMH_TRACE1(LEVEL, STR, ARG1) \
100 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, 0, 0, 0, 0, 0)
103 * @def IX_NPEMH_TRACE2
105 * @brief Trace macro taking 2 arguments.
108 #define IX_NPEMH_TRACE2(LEVEL, STR, ARG1, ARG2) \
109 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, 0, 0, 0, 0)
112 * @def IX_NPEMH_TRACE3
114 * @brief Trace macro taking 3 arguments.
117 #define IX_NPEMH_TRACE3(LEVEL, STR, ARG1, ARG2, ARG3) \
118 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, 0, 0, 0)
121 * @def IX_NPEMH_TRACE4
123 * @brief Trace macro taking 4 arguments.
126 #define IX_NPEMH_TRACE4(LEVEL, STR, ARG1, ARG2, ARG3, ARG4) \
127 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, 0, 0)
130 * @def IX_NPEMH_TRACE5
132 * @brief Trace macro taking 5 arguments.
135 #define IX_NPEMH_TRACE5(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5) \
136 IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, 0)
139 * @def IX_NPEMH_TRACE6
141 * @brief Trace macro taking 6 arguments.
144 #define IX_NPEMH_TRACE6(LEVEL, STR, ARG1, ARG2, ARG3, ARG4, ARG5, ARG6) \
146 if (LEVEL <= IX_NPEMH_TRACE_LEVEL) \
148 (void) ixOsalLog (LEVEL, IX_OSAL_LOG_DEV_STDOUT, (STR), \
149 (int)(ARG1), (int)(ARG2), (int)(ARG3), \
150 (int)(ARG4), (int)(ARG5), (int)(ARG6)); \
155 * @def IX_NPEMH_ERROR_REPORT
157 * @brief Error reporting facility.
160 #define IX_NPEMH_ERROR_REPORT(STR) \
162 (void) ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, \
163 (STR), 0, 0, 0, 0, 0, 0); \
166 /* if we are running on XScale, i.e. real environment */
170 * @def IX_NPEMH_REGISTER_READ
172 * @brief This macro reads a memory-mapped register.
175 #define IX_NPEMH_REGISTER_READ(registerAddress, value) \
177 *value = IX_OSAL_READ_LONG(registerAddress); \
181 * @def IX_NPEMH_REGISTER_READ_BITS
183 * @brief This macro partially reads a memory-mapped register.
186 #define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
188 *value = (IX_OSAL_READ_LONG(registerAddress) & mask); \
192 * @def IX_NPEMH_REGISTER_WRITE
194 * @brief This macro writes a memory-mapped register.
197 #define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
199 IX_OSAL_WRITE_LONG(registerAddress, value); \
203 * @def IX_NPEMH_REGISTER_WRITE_BITS
205 * @brief This macro partially writes a memory-mapped register.
208 #define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
210 UINT32 orig = IX_OSAL_READ_LONG(registerAddress); \
212 orig |= (value & mask); \
213 IX_OSAL_WRITE_LONG(registerAddress, orig); \
217 /* if we are running as a unit test */
218 #else /* #if CPU==XSCALE */
220 #include "IxNpeMhTestRegister.h"
223 * @def IX_NPEMH_REGISTER_READ
225 * @brief This macro reads a memory-mapped register.
228 #define IX_NPEMH_REGISTER_READ(registerAddress, value) \
230 ixNpeMhTestRegisterRead (registerAddress, value); \
234 * @def IX_NPEMH_REGISTER_READ_BITS
236 * @brief This macro partially reads a memory-mapped register.
239 #define IX_NPEMH_REGISTER_READ_BITS(registerAddress, value, mask) \
241 ixNpeMhTestRegisterReadBits (registerAddress, value, mask); \
245 * @def IX_NPEMH_REGISTER_WRITE
247 * @brief This macro writes a memory-mapped register.
250 #define IX_NPEMH_REGISTER_WRITE(registerAddress, value) \
252 ixNpeMhTestRegisterWrite (registerAddress, value); \
256 * @def IX_NPEMH_REGISTER_WRITE_BITS
258 * @brief This macro partially writes a memory-mapped register.
261 #define IX_NPEMH_REGISTER_WRITE_BITS(registerAddress, value, mask) \
263 ixNpeMhTestRegisterWriteBits (registerAddress, value, mask); \
266 #endif /* #if CPU==XSCALE */
268 #endif /* IXNPEMHMACROS_P_H */
271 * @} defgroup IxNpeMhMacros_p