2 * @file IxQueueAssignments.h
4 * @author Intel Corporation
7 * @brief Central definition for queue assignments
10 * This file contains queue assignments used by Ethernet (EthAcc),
11 * HSS (HssAcc), ATM (atmdAcc) and DMA (dmaAcc) access libraries.
13 * Note: Ethernet QoS traffic class definitions are managed separately
14 * by EthDB in IxEthDBQoS.h.
17 * IXP400 SW Release version 2.0
19 * -- Copyright Notice --
22 * Copyright 2001-2005, Intel Corporation.
23 * All rights reserved.
26 * SPDX-License-Identifier: BSD-3-Clause
28 * -- End of Copyright Notice --
31 #ifndef IxQueueAssignments_H
32 #define IxQueueAssignments_H
36 /***************************************************************************
37 * Queue assignments for ATM
38 ***************************************************************************/
41 * @brief Global compiler switch to select between 3 possible NPE Modes
42 * Define this macro to enable MPHY mode
44 * Default(No Switch) = MultiPHY Utopia2
45 * IX_UTOPIAMODE = 1 for single Phy Utopia1
46 * IX_MPHYSINGLEPORT = 1 for single Phy Utopia2
48 #define IX_NPE_MPHYMULTIPORT 1
49 #if IX_UTOPIAMODE == 1
50 #undef IX_NPE_MPHYMULTIPORT
52 #if IX_MPHYSINGLEPORT == 1
53 #undef IX_NPE_MPHYMULTIPORT
57 * @def IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK
59 * @brief The NPE reserves the High Watermark for its operation. But it must be set by the Xscale
61 #define IX_NPE_A_TXDONE_QUEUE_HIGHWATERMARK 2
64 * @def IX_NPE_A_QMQ_ATM_TX_DONE
66 * @brief Queue ID for ATM Transmit Done queue
68 #define IX_NPE_A_QMQ_ATM_TX_DONE IX_QMGR_QUEUE_1
71 * @def IX_NPE_A_QMQ_ATM_TX0
73 * @brief Queue ID for ATM transmit Queue in a single phy configuration
75 #define IX_NPE_A_QMQ_ATM_TX0 IX_QMGR_QUEUE_2
79 * @def IX_NPE_A_QMQ_ATM_TXID_MIN
81 * @brief Queue Manager Queue ID for ATM transmit Queue with minimum number of queue
86 * @def IX_NPE_A_QMQ_ATM_TXID_MAX
88 * @brief Queue Manager Queue ID for ATM transmit Queue with maximum number of queue
93 * @def IX_NPE_A_QMQ_ATM_RX_HI
95 * @brief Queue Manager Queue ID for ATM Receive high Queue
100 * @def IX_NPE_A_QMQ_ATM_RX_LO
102 * @brief Queue Manager Queue ID for ATM Receive low Queue
105 #ifdef IX_NPE_MPHYMULTIPORT
107 * @def IX_NPE_A_QMQ_ATM_TX1
109 * @brief Queue ID for ATM transmit Queue Multiphy from 1 to 11
111 #define IX_NPE_A_QMQ_ATM_TX1 IX_NPE_A_QMQ_ATM_TX0+1
112 #define IX_NPE_A_QMQ_ATM_TX2 IX_NPE_A_QMQ_ATM_TX1+1
113 #define IX_NPE_A_QMQ_ATM_TX3 IX_NPE_A_QMQ_ATM_TX2+1
114 #define IX_NPE_A_QMQ_ATM_TX4 IX_NPE_A_QMQ_ATM_TX3+1
115 #define IX_NPE_A_QMQ_ATM_TX5 IX_NPE_A_QMQ_ATM_TX4+1
116 #define IX_NPE_A_QMQ_ATM_TX6 IX_NPE_A_QMQ_ATM_TX5+1
117 #define IX_NPE_A_QMQ_ATM_TX7 IX_NPE_A_QMQ_ATM_TX6+1
118 #define IX_NPE_A_QMQ_ATM_TX8 IX_NPE_A_QMQ_ATM_TX7+1
119 #define IX_NPE_A_QMQ_ATM_TX9 IX_NPE_A_QMQ_ATM_TX8+1
120 #define IX_NPE_A_QMQ_ATM_TX10 IX_NPE_A_QMQ_ATM_TX9+1
121 #define IX_NPE_A_QMQ_ATM_TX11 IX_NPE_A_QMQ_ATM_TX10+1
122 #define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
123 #define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX11
124 #define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_21
125 #define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_22
127 #define IX_NPE_A_QMQ_ATM_TXID_MIN IX_NPE_A_QMQ_ATM_TX0
128 #define IX_NPE_A_QMQ_ATM_TXID_MAX IX_NPE_A_QMQ_ATM_TX0
129 #define IX_NPE_A_QMQ_ATM_RX_HI IX_QMGR_QUEUE_10
130 #define IX_NPE_A_QMQ_ATM_RX_LO IX_QMGR_QUEUE_11
134 * @def IX_NPE_A_QMQ_ATM_FREE_VC0
136 * @brief Hardware QMgr Queue ID for ATM Free VC Queue.
138 * There are 32 Hardware QMgr Queue ID; from IX_NPE_A_QMQ_ATM_FREE_VC1 to
139 * IX_NPE_A_QMQ_ATM_FREE_VC30
141 #define IX_NPE_A_QMQ_ATM_FREE_VC0 IX_QMGR_QUEUE_32
142 #define IX_NPE_A_QMQ_ATM_FREE_VC1 IX_NPE_A_QMQ_ATM_FREE_VC0+1
143 #define IX_NPE_A_QMQ_ATM_FREE_VC2 IX_NPE_A_QMQ_ATM_FREE_VC1+1
144 #define IX_NPE_A_QMQ_ATM_FREE_VC3 IX_NPE_A_QMQ_ATM_FREE_VC2+1
145 #define IX_NPE_A_QMQ_ATM_FREE_VC4 IX_NPE_A_QMQ_ATM_FREE_VC3+1
146 #define IX_NPE_A_QMQ_ATM_FREE_VC5 IX_NPE_A_QMQ_ATM_FREE_VC4+1
147 #define IX_NPE_A_QMQ_ATM_FREE_VC6 IX_NPE_A_QMQ_ATM_FREE_VC5+1
148 #define IX_NPE_A_QMQ_ATM_FREE_VC7 IX_NPE_A_QMQ_ATM_FREE_VC6+1
149 #define IX_NPE_A_QMQ_ATM_FREE_VC8 IX_NPE_A_QMQ_ATM_FREE_VC7+1
150 #define IX_NPE_A_QMQ_ATM_FREE_VC9 IX_NPE_A_QMQ_ATM_FREE_VC8+1
151 #define IX_NPE_A_QMQ_ATM_FREE_VC10 IX_NPE_A_QMQ_ATM_FREE_VC9+1
152 #define IX_NPE_A_QMQ_ATM_FREE_VC11 IX_NPE_A_QMQ_ATM_FREE_VC10+1
153 #define IX_NPE_A_QMQ_ATM_FREE_VC12 IX_NPE_A_QMQ_ATM_FREE_VC11+1
154 #define IX_NPE_A_QMQ_ATM_FREE_VC13 IX_NPE_A_QMQ_ATM_FREE_VC12+1
155 #define IX_NPE_A_QMQ_ATM_FREE_VC14 IX_NPE_A_QMQ_ATM_FREE_VC13+1
156 #define IX_NPE_A_QMQ_ATM_FREE_VC15 IX_NPE_A_QMQ_ATM_FREE_VC14+1
157 #define IX_NPE_A_QMQ_ATM_FREE_VC16 IX_NPE_A_QMQ_ATM_FREE_VC15+1
158 #define IX_NPE_A_QMQ_ATM_FREE_VC17 IX_NPE_A_QMQ_ATM_FREE_VC16+1
159 #define IX_NPE_A_QMQ_ATM_FREE_VC18 IX_NPE_A_QMQ_ATM_FREE_VC17+1
160 #define IX_NPE_A_QMQ_ATM_FREE_VC19 IX_NPE_A_QMQ_ATM_FREE_VC18+1
161 #define IX_NPE_A_QMQ_ATM_FREE_VC20 IX_NPE_A_QMQ_ATM_FREE_VC19+1
162 #define IX_NPE_A_QMQ_ATM_FREE_VC21 IX_NPE_A_QMQ_ATM_FREE_VC20+1
163 #define IX_NPE_A_QMQ_ATM_FREE_VC22 IX_NPE_A_QMQ_ATM_FREE_VC21+1
164 #define IX_NPE_A_QMQ_ATM_FREE_VC23 IX_NPE_A_QMQ_ATM_FREE_VC22+1
165 #define IX_NPE_A_QMQ_ATM_FREE_VC24 IX_NPE_A_QMQ_ATM_FREE_VC23+1
166 #define IX_NPE_A_QMQ_ATM_FREE_VC25 IX_NPE_A_QMQ_ATM_FREE_VC24+1
167 #define IX_NPE_A_QMQ_ATM_FREE_VC26 IX_NPE_A_QMQ_ATM_FREE_VC25+1
168 #define IX_NPE_A_QMQ_ATM_FREE_VC27 IX_NPE_A_QMQ_ATM_FREE_VC26+1
169 #define IX_NPE_A_QMQ_ATM_FREE_VC28 IX_NPE_A_QMQ_ATM_FREE_VC27+1
170 #define IX_NPE_A_QMQ_ATM_FREE_VC29 IX_NPE_A_QMQ_ATM_FREE_VC28+1
171 #define IX_NPE_A_QMQ_ATM_FREE_VC30 IX_NPE_A_QMQ_ATM_FREE_VC29+1
172 #define IX_NPE_A_QMQ_ATM_FREE_VC31 IX_NPE_A_QMQ_ATM_FREE_VC30+1
175 * @def IX_NPE_A_QMQ_ATM_RXFREE_MIN
177 * @brief The minimum queue ID for FreeVC queue
179 #define IX_NPE_A_QMQ_ATM_RXFREE_MIN IX_NPE_A_QMQ_ATM_FREE_VC0
182 * @def IX_NPE_A_QMQ_ATM_RXFREE_MAX
184 * @brief The maximum queue ID for FreeVC queue
186 #define IX_NPE_A_QMQ_ATM_RXFREE_MAX IX_NPE_A_QMQ_ATM_FREE_VC31
189 * @def IX_NPE_A_QMQ_OAM_FREE_VC
190 * @brief OAM Rx Free queue ID
192 #ifdef IX_NPE_MPHYMULTIPORT
193 #define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_14
195 #define IX_NPE_A_QMQ_OAM_FREE_VC IX_QMGR_QUEUE_3
198 /****************************************************************************
199 * Queue assignments for HSS
200 ****************************************************************************/
202 /**** HSS Port 0 ****/
205 * @def IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG
207 * @brief Hardware QMgr Queue ID for HSS Port 0 Channelized Receive trigger
209 #define IX_NPE_A_QMQ_HSS0_CHL_RX_TRIG IX_QMGR_QUEUE_12
212 * @def IX_NPE_A_QMQ_HSS0_PKT_RX
214 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive
216 #define IX_NPE_A_QMQ_HSS0_PKT_RX IX_QMGR_QUEUE_13
219 * @def IX_NPE_A_QMQ_HSS0_PKT_TX0
221 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 0
223 #define IX_NPE_A_QMQ_HSS0_PKT_TX0 IX_QMGR_QUEUE_14
226 * @def IX_NPE_A_QMQ_HSS0_PKT_TX1
228 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 1
230 #define IX_NPE_A_QMQ_HSS0_PKT_TX1 IX_QMGR_QUEUE_15
233 * @def IX_NPE_A_QMQ_HSS0_PKT_TX2
235 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 2
237 #define IX_NPE_A_QMQ_HSS0_PKT_TX2 IX_QMGR_QUEUE_16
240 * @def IX_NPE_A_QMQ_HSS0_PKT_TX3
242 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit queue 3
244 #define IX_NPE_A_QMQ_HSS0_PKT_TX3 IX_QMGR_QUEUE_17
247 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0
249 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 0
251 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE0 IX_QMGR_QUEUE_18
254 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1
256 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 1
258 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE1 IX_QMGR_QUEUE_19
261 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2
263 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 2
265 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE2 IX_QMGR_QUEUE_20
268 * @def IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3
270 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Receive Free queue 3
272 #define IX_NPE_A_QMQ_HSS0_PKT_RX_FREE3 IX_QMGR_QUEUE_21
275 * @def IX_NPE_A_QMQ_HSS0_PKT_TX_DONE
277 * @brief Hardware QMgr Queue ID for HSS Port 0 Packetized Transmit Done queue
279 #define IX_NPE_A_QMQ_HSS0_PKT_TX_DONE IX_QMGR_QUEUE_22
281 /**** HSS Port 1 ****/
284 * @def IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG
286 * @brief Hardware QMgr Queue ID for HSS Port 1 Channelized Receive trigger
288 #define IX_NPE_A_QMQ_HSS1_CHL_RX_TRIG IX_QMGR_QUEUE_10
291 * @def IX_NPE_A_QMQ_HSS1_PKT_RX
293 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive
295 #define IX_NPE_A_QMQ_HSS1_PKT_RX IX_QMGR_QUEUE_0
298 * @def IX_NPE_A_QMQ_HSS1_PKT_TX0
300 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 0
302 #define IX_NPE_A_QMQ_HSS1_PKT_TX0 IX_QMGR_QUEUE_5
305 * @def IX_NPE_A_QMQ_HSS1_PKT_TX1
307 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 1
309 #define IX_NPE_A_QMQ_HSS1_PKT_TX1 IX_QMGR_QUEUE_6
312 * @def IX_NPE_A_QMQ_HSS1_PKT_TX2
314 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 2
316 #define IX_NPE_A_QMQ_HSS1_PKT_TX2 IX_QMGR_QUEUE_7
319 * @def IX_NPE_A_QMQ_HSS1_PKT_TX3
321 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit queue 3
323 #define IX_NPE_A_QMQ_HSS1_PKT_TX3 IX_QMGR_QUEUE_8
326 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0
328 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 0
330 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE0 IX_QMGR_QUEUE_1
333 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1
335 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 1
337 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE1 IX_QMGR_QUEUE_2
340 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2
342 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 2
344 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE2 IX_QMGR_QUEUE_3
347 * @def IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3
349 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Receive Free queue 3
351 #define IX_NPE_A_QMQ_HSS1_PKT_RX_FREE3 IX_QMGR_QUEUE_4
354 * @def IX_NPE_A_QMQ_HSS1_PKT_TX_DONE
356 * @brief Hardware QMgr Queue ID for HSS Port 1 Packetized Transmit Done queue
358 #define IX_NPE_A_QMQ_HSS1_PKT_TX_DONE IX_QMGR_QUEUE_9
360 /*****************************************************************************************
361 * Queue assignments for DMA
362 *****************************************************************************************/
364 #define IX_DMA_NPE_A_REQUEST_QID IX_QMGR_QUEUE_19 /**< Queue Id for NPE A DMA Request */
365 #define IX_DMA_NPE_A_DONE_QID IX_QMGR_QUEUE_20 /**< Queue Id for NPE A DMA Done */
366 #define IX_DMA_NPE_B_REQUEST_QID IX_QMGR_QUEUE_24 /**< Queue Id for NPE B DMA Request */
367 #define IX_DMA_NPE_B_DONE_QID IX_QMGR_QUEUE_26 /**< Queue Id for NPE B DMA Done */
368 #define IX_DMA_NPE_C_REQUEST_QID IX_QMGR_QUEUE_25 /**< Queue Id for NPE C DMA Request */
369 #define IX_DMA_NPE_C_DONE_QID IX_QMGR_QUEUE_27 /**< Queue Id for NPE C DMA Done */
372 /*****************************************************************************************
373 * Queue assignments for Ethernet
375 * Note: Rx queue definitions, which include QoS traffic class definitions
376 * are managed by EthDB and declared in IxEthDBQoS.h
377 *****************************************************************************************/
381 * @def IX_ETH_ACC_RX_FRAME_ETH_Q
383 * @brief Eth0/Eth1 NPE Frame Receive Q.
385 * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
388 #define IX_ETH_ACC_RX_FRAME_ETH_Q (IX_QMGR_QUEUE_4)
392 * @def IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q
394 * @brief Supply Rx Buffers Ethernet Q for NPEB - Eth 0 - Port 1
397 #define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q (IX_QMGR_QUEUE_27)
401 * @def IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q
403 * @brief Supply Rx Buffers Ethernet Q for NPEC - Eth 1 - Port 2
406 #define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q (IX_QMGR_QUEUE_28)
410 * @def IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q
412 * @brief Supply Rx Buffers Ethernet Q for NPEA - Eth 2 - Port 3
415 #define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q (IX_QMGR_QUEUE_26)
420 * @def IX_ETH_ACC_TX_FRAME_ENET0_Q
422 * @brief Submit frame Q for NPEB Eth 0 - Port 1
425 #define IX_ETH_ACC_TX_FRAME_ENET0_Q (IX_QMGR_QUEUE_24)
430 * @def IX_ETH_ACC_TX_FRAME_ENET1_Q
432 * @brief Submit frame Q for NPEC Eth 1 - Port 2
435 #define IX_ETH_ACC_TX_FRAME_ENET1_Q (IX_QMGR_QUEUE_25)
439 * @def IX_ETH_ACC_TX_FRAME_ENET2_Q
441 * @brief Submit frame Q for NPEA Eth 2 - Port 3
444 #define IX_ETH_ACC_TX_FRAME_ENET2_Q (IX_QMGR_QUEUE_23)
448 * @def IX_ETH_ACC_TX_FRAME_DONE_ETH_Q
450 * @brief Transmit complete Q for NPE Eth 0/1, Port 1&2
453 #define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q (IX_QMGR_QUEUE_31)
455 /*****************************************************************************************
456 * Queue assignments for Crypto
457 *****************************************************************************************/
459 /** Crypto Service Request Queue */
460 #define IX_CRYPTO_ACC_CRYPTO_REQ_Q (IX_QMGR_QUEUE_29)
462 /** Crypto Service Done Queue */
463 #define IX_CRYPTO_ACC_CRYPTO_DONE_Q (IX_QMGR_QUEUE_30)
465 /** Crypto Req Q CB tag */
466 #define IX_CRYPTO_ACC_CRYPTO_REQ_Q_CB_TAG (0)
468 /** Crypto Done Q CB tag */
469 #define IX_CRYPTO_ACC_CRYPTO_DONE_Q_CB_TAG (1)
471 /** WEP Service Request Queue */
472 #define IX_CRYPTO_ACC_WEP_REQ_Q (IX_QMGR_QUEUE_21)
474 /** WEP Service Done Queue */
475 #define IX_CRYPTO_ACC_WEP_DONE_Q (IX_QMGR_QUEUE_22)
477 /** WEP Req Q CB tag */
478 #define IX_CRYPTO_ACC_WEP_REQ_Q_CB_TAG (2)
480 /** WEP Done Q CB tag */
481 #define IX_CRYPTO_ACC_WEP_DONE_Q_CB_TAG (3)
483 /** Number of queues allocate to crypto hardware accelerator services */
484 #define IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q (2)
486 /** Number of queues allocate to WEP NPE services */
487 #define IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q (2)
489 /** Number of queues allocate to CryptoAcc component */
490 #define IX_CRYPTO_ACC_NUM_OF_Q (IX_CRYPTO_ACC_NUM_OF_CRYPTO_Q + IX_CRYPTO_ACC_NUM_OF_WEP_NPE_Q)
492 #endif /* IxQueueAssignments_H */