drivers/net/npe/miiphy.c

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0 ibm-pibs
   3  */
   4 /*-----------------------------------------------------------------------------+
   5   |
   6   |  File Name:  miiphy.c
   7   |
   8   |  Function:   This module has utilities for accessing the MII PHY through
   9   |            the EMAC3 macro.
  10   |
  11   |  Author:     Mark Wisner
  12   |
  13   |  Change Activity-
  14   |
  15   |  Date        Description of Change                                       BY
  16   |  ---------   ---------------------                                       ---
  17   |  05-May-99   Created                                                     MKW
  18   |  01-Jul-99   Changed clock setting of sta_reg from 66MHz to 50MHz to
  19   |              better match OPB speed. Also modified delay times.          JWB
  20   |  29-Jul-99   Added Full duplex support                                   MKW
  21   |  24-Aug-99   Removed printf from dp83843_duplex()                        JWB
  22   |  19-Jul-00   Ported to esd cpci405                                       sr
  23   |  23-Dec-03   Ported from miiphy.c to 440GX Travis Sawyer                 TBS
  24   |              <travis.sawyer@sandburst.com>
  25   |
  26   +-----------------------------------------------------------------------------*/
  27
  28 #include <common.h>
  29 #include <miiphy.h>
  30 #include "IxOsal.h"
  31 #include "IxEthAcc.h"
  32 #include "IxEthAcc_p.h"
  33 #include "IxEthAccMac_p.h"
  34 #include "IxEthAccMii_p.h"
  35
  36 /***********************************************************/
  37 /* Dump out to the screen PHY regs                         */
  38 /***********************************************************/
  39
  40 void miiphy_dump (char *devname, unsigned char addr)
  41 {
  42         unsigned long i;
  43         unsigned short data;
  44
  45
  46         for (i = 0; i < 0x1A; i++) {
  47                 if (miiphy_read (devname, addr, i, &data)) {
  48                         printf ("read error for reg %lx\n", i);
  49                         return;
  50                 }
  51                 printf ("Phy reg %lx ==> %4x\n", i, data);
  52
  53                 /* jump to the next set of regs */
  54                 if (i == 0x07)
  55                         i = 0x0f;
  56
  57         }                       /* end for loop */
  58 }                               /* end dump */
  59
  60
  61 /***********************************************************/
  62 /* (Re)start autonegotiation                               */
  63 /***********************************************************/
  64 int phy_setup_aneg (char *devname, unsigned char addr)
  65 {
  66         unsigned short ctl, adv;
  67
  68         /* Setup standard advertise */
  69         miiphy_read (devname, addr, MII_ADVERTISE, &adv);
  70         adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
  71                 LPA_100FULL | LPA_100HALF | LPA_10FULL |
  72                 LPA_10HALF);
  73         miiphy_write (devname, addr, MII_ADVERTISE, adv);
  74
  75         /* Start/Restart aneg */
  76         miiphy_read (devname, addr, MII_BMCR, &ctl);
  77         ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  78         miiphy_write (devname, addr, MII_BMCR, ctl);
  79
  80         return 0;
  81 }
  82
  83
  84 int npe_miiphy_read (const char *devname, unsigned char addr,
  85                      unsigned char reg, unsigned short *value)
  86 {
  87         u16 val;
  88
  89         ixEthAccMiiReadRtn(addr, reg, &val);
  90         *value = val;
  91
  92         return 0;
  93 }                               /* phy_read */
  94
  95
  96 int npe_miiphy_write (const char *devname, unsigned char addr,
  97                       unsigned char reg, unsigned short value)
  98 {
  99         ixEthAccMiiWriteRtn(addr, reg, value);
 100         return 0;
 101 }                               /* phy_write */