drivers/net/sh_eth.h

   1 /*
   2  * sh_eth.h - Driver for Renesas SuperH ethernet controler.
   3  *
   4  * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
   5  * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
   6  * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <netdev.h>
  12 #include <asm/types.h>
  13
  14 #define SHETHER_NAME "sh_eth"
  15
  16 #if defined(CONFIG_SH)
  17 /* Malloc returns addresses in the P1 area (cacheable). However we need to
  18    use area P2 (non-cacheable) */
  19 #define ADDR_TO_P2(addr)        ((((int)(addr) & ~0xe0000000) | 0xa0000000))
  20
  21 /* The ethernet controller needs to use physical addresses */
  22 #if defined(CONFIG_SH_32BIT)
  23 #define ADDR_TO_PHY(addr)       ((((int)(addr) & ~0xe0000000) | 0x40000000))
  24 #else
  25 #define ADDR_TO_PHY(addr)       ((int)(addr) & ~0xe0000000)
  26 #endif
  27 #elif defined(CONFIG_ARM)
  28 #define inl             readl
  29 #define outl    writel
  30 #define ADDR_TO_PHY(addr)       ((int)(addr))
  31 #define ADDR_TO_P2(addr)        (addr)
  32 #endif /* defined(CONFIG_SH) */
  33
  34 /* base padding size is 16 */
  35 #ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
  36 #define CONFIG_SH_ETHER_ALIGNE_SIZE 16
  37 #endif
  38
  39 /* Number of supported ports */
  40 #define MAX_PORT_NUM    2
  41
  42 /* Buffers must be big enough to hold the largest ethernet frame. Also, rx
  43    buffers must be a multiple of 32 bytes */
  44 #define MAX_BUF_SIZE    (48 * 32)
  45
  46 /* The number of tx descriptors must be large enough to point to 5 or more
  47    frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
  48    We use one descriptor per frame */
  49 #define NUM_TX_DESC             8
  50
  51 /* The size of the tx descriptor is determined by how much padding is used.
  52    4, 20, or 52 bytes of padding can be used */
  53 #define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  54 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
  55 #define TX_DESC_SIZE    (12 + TX_DESC_PADDING)
  56
  57 /* Tx descriptor. We always use 3 bytes of padding */
  58 struct tx_desc_s {
  59         volatile u32 td0;
  60         u32 td1;
  61         u32 td2;                /* Buffer start */
  62         u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
  63 };
  64
  65 /* There is no limitation in the number of rx descriptors */
  66 #define NUM_RX_DESC     8
  67
  68 /* The size of the rx descriptor is determined by how much padding is used.
  69    4, 20, or 52 bytes of padding can be used */
  70 #define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
  71 /* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
  72 #define RX_DESC_SIZE            (12 + RX_DESC_PADDING)
  73 /* aligned cache line size */
  74 #define RX_BUF_ALIGNE_SIZE      (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
  75
  76 /* Rx descriptor. We always use 4 bytes of padding */
  77 struct rx_desc_s {
  78         volatile u32 rd0;
  79         volatile u32 rd1;
  80         u32 rd2;                /* Buffer start */
  81         u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
  82 };
  83
  84 struct sh_eth_info {
  85         struct tx_desc_s *tx_desc_malloc;
  86         struct tx_desc_s *tx_desc_base;
  87         struct tx_desc_s *tx_desc_cur;
  88         struct rx_desc_s *rx_desc_malloc;
  89         struct rx_desc_s *rx_desc_base;
  90         struct rx_desc_s *rx_desc_cur;
  91         u8 *rx_buf_malloc;
  92         u8 *rx_buf_base;
  93         u8 mac_addr[6];
  94         u8 phy_addr;
  95         struct eth_device *dev;
  96         struct phy_device *phydev;
  97 };
  98
  99 struct sh_eth_dev {
 100         int port;
 101         struct sh_eth_info port_info[MAX_PORT_NUM];
 102 };
 103
 104 /* from linux/drivers/net/ethernet/renesas/sh_eth.h */
 105 enum {
 106         /* E-DMAC registers */
 107         EDSR = 0,
 108         EDMR,
 109         EDTRR,
 110         EDRRR,
 111         EESR,
 112         EESIPR,
 113         TDLAR,
 114         TDFAR,
 115         TDFXR,
 116         TDFFR,
 117         RDLAR,
 118         RDFAR,
 119         RDFXR,
 120         RDFFR,
 121         TRSCER,
 122         RMFCR,
 123         TFTR,
 124         FDR,
 125         RMCR,
 126         EDOCR,
 127         TFUCR,
 128         RFOCR,
 129         FCFTR,
 130         RPADIR,
 131         TRIMD,
 132         RBWAR,
 133         TBRAR,
 134
 135         /* Ether registers */
 136         ECMR,
 137         ECSR,
 138         ECSIPR,
 139         PIR,
 140         PSR,
 141         RDMLR,
 142         PIPR,
 143         RFLR,
 144         IPGR,
 145         APR,
 146         MPR,
 147         PFTCR,
 148         PFRCR,
 149         RFCR,
 150         RFCF,
 151         TPAUSER,
 152         TPAUSECR,
 153         BCFR,
 154         BCFRR,
 155         GECMR,
 156         BCULR,
 157         MAHR,
 158         MALR,
 159         TROCR,
 160         CDCR,
 161         LCCR,
 162         CNDCR,
 163         CEFCR,
 164         FRECR,
 165         TSFRCR,
 166         TLFRCR,
 167         CERCR,
 168         CEECR,
 169         RMIIMR, /* R8A7790 */
 170         MAFCR,
 171         RTRATE,
 172         CSMR,
 173         RMII_MII,
 174
 175         /* This value must be written at last. */
 176         SH_ETH_MAX_REGISTER_OFFSET,
 177 };
 178
 179 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 180         [EDSR]  = 0x0000,
 181         [EDMR]  = 0x0400,
 182         [EDTRR] = 0x0408,
 183         [EDRRR] = 0x0410,
 184         [EESR]  = 0x0428,
 185         [EESIPR]        = 0x0430,
 186         [TDLAR] = 0x0010,
 187         [TDFAR] = 0x0014,
 188         [TDFXR] = 0x0018,
 189         [TDFFR] = 0x001c,
 190         [RDLAR] = 0x0030,
 191         [RDFAR] = 0x0034,
 192         [RDFXR] = 0x0038,
 193         [RDFFR] = 0x003c,
 194         [TRSCER]        = 0x0438,
 195         [RMFCR] = 0x0440,
 196         [TFTR]  = 0x0448,
 197         [FDR]   = 0x0450,
 198         [RMCR]  = 0x0458,
 199         [RPADIR]        = 0x0460,
 200         [FCFTR] = 0x0468,
 201         [CSMR] = 0x04E4,
 202
 203         [ECMR]  = 0x0500,
 204         [ECSR]  = 0x0510,
 205         [ECSIPR]        = 0x0518,
 206         [PIR]   = 0x0520,
 207         [PSR]   = 0x0528,
 208         [PIPR]  = 0x052c,
 209         [RFLR]  = 0x0508,
 210         [APR]   = 0x0554,
 211         [MPR]   = 0x0558,
 212         [PFTCR] = 0x055c,
 213         [PFRCR] = 0x0560,
 214         [TPAUSER]       = 0x0564,
 215         [GECMR] = 0x05b0,
 216         [BCULR] = 0x05b4,
 217         [MAHR]  = 0x05c0,
 218         [MALR]  = 0x05c8,
 219         [TROCR] = 0x0700,
 220         [CDCR]  = 0x0708,
 221         [LCCR]  = 0x0710,
 222         [CEFCR] = 0x0740,
 223         [FRECR] = 0x0748,
 224         [TSFRCR]        = 0x0750,
 225         [TLFRCR]        = 0x0758,
 226         [RFCR]  = 0x0760,
 227         [CERCR] = 0x0768,
 228         [CEECR] = 0x0770,
 229         [MAFCR] = 0x0778,
 230         [RMII_MII] =  0x0790,
 231 };
 232
 233 #if defined(SH_ETH_TYPE_RZ)
 234 static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 235         [EDSR]  = 0x0000,
 236         [EDMR]  = 0x0400,
 237         [EDTRR] = 0x0408,
 238         [EDRRR] = 0x0410,
 239         [EESR]  = 0x0428,
 240         [EESIPR]        = 0x0430,
 241         [TDLAR] = 0x0010,
 242         [TDFAR] = 0x0014,
 243         [TDFXR] = 0x0018,
 244         [TDFFR] = 0x001c,
 245         [RDLAR] = 0x0030,
 246         [RDFAR] = 0x0034,
 247         [RDFXR] = 0x0038,
 248         [RDFFR] = 0x003c,
 249         [TRSCER]        = 0x0438,
 250         [RMFCR] = 0x0440,
 251         [TFTR]  = 0x0448,
 252         [FDR]   = 0x0450,
 253         [RMCR]  = 0x0458,
 254         [RPADIR]        = 0x0460,
 255         [FCFTR] = 0x0468,
 256         [CSMR] = 0x04E4,
 257
 258         [ECMR]  = 0x0500,
 259         [ECSR]  = 0x0510,
 260         [ECSIPR]        = 0x0518,
 261         [PSR]   = 0x0528,
 262         [PIPR]  = 0x052c,
 263         [RFLR]  = 0x0508,
 264         [APR]   = 0x0554,
 265         [MPR]   = 0x0558,
 266         [PFTCR] = 0x055c,
 267         [PFRCR] = 0x0560,
 268         [TPAUSER]       = 0x0564,
 269         [GECMR] = 0x05b0,
 270         [BCULR] = 0x05b4,
 271         [MAHR]  = 0x05c0,
 272         [MALR]  = 0x05c8,
 273         [TROCR] = 0x0700,
 274         [CDCR]  = 0x0708,
 275         [LCCR]  = 0x0710,
 276         [CEFCR] = 0x0740,
 277         [FRECR] = 0x0748,
 278         [TSFRCR]        = 0x0750,
 279         [TLFRCR]        = 0x0758,
 280         [RFCR]  = 0x0760,
 281         [CERCR] = 0x0768,
 282         [CEECR] = 0x0770,
 283         [MAFCR] = 0x0778,
 284         [RMII_MII] =  0x0790,
 285 };
 286 #endif
 287
 288 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 289         [ECMR]  = 0x0100,
 290         [RFLR]  = 0x0108,
 291         [ECSR]  = 0x0110,
 292         [ECSIPR]        = 0x0118,
 293         [PIR]   = 0x0120,
 294         [PSR]   = 0x0128,
 295         [RDMLR] = 0x0140,
 296         [IPGR]  = 0x0150,
 297         [APR]   = 0x0154,
 298         [MPR]   = 0x0158,
 299         [TPAUSER]       = 0x0164,
 300         [RFCF]  = 0x0160,
 301         [TPAUSECR]      = 0x0168,
 302         [BCFRR] = 0x016c,
 303         [MAHR]  = 0x01c0,
 304         [MALR]  = 0x01c8,
 305         [TROCR] = 0x01d0,
 306         [CDCR]  = 0x01d4,
 307         [LCCR]  = 0x01d8,
 308         [CNDCR] = 0x01dc,
 309         [CEFCR] = 0x01e4,
 310         [FRECR] = 0x01e8,
 311         [TSFRCR]        = 0x01ec,
 312         [TLFRCR]        = 0x01f0,
 313         [RFCR]  = 0x01f4,
 314         [MAFCR] = 0x01f8,
 315         [RTRATE]        = 0x01fc,
 316
 317         [EDMR]  = 0x0000,
 318         [EDTRR] = 0x0008,
 319         [EDRRR] = 0x0010,
 320         [TDLAR] = 0x0018,
 321         [RDLAR] = 0x0020,
 322         [EESR]  = 0x0028,
 323         [EESIPR]        = 0x0030,
 324         [TRSCER]        = 0x0038,
 325         [RMFCR] = 0x0040,
 326         [TFTR]  = 0x0048,
 327         [FDR]   = 0x0050,
 328         [RMCR]  = 0x0058,
 329         [TFUCR] = 0x0064,
 330         [RFOCR] = 0x0068,
 331         [RMIIMR] = 0x006C,
 332         [FCFTR] = 0x0070,
 333         [RPADIR]        = 0x0078,
 334         [TRIMD] = 0x007c,
 335         [RBWAR] = 0x00c8,
 336         [RDFAR] = 0x00cc,
 337         [TBRAR] = 0x00d4,
 338         [TDFAR] = 0x00d8,
 339 };
 340
 341 /* Register Address */
 342 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 343 #define SH_ETH_TYPE_GETHER
 344 #define BASE_IO_ADDR    0xfee00000
 345 #elif defined(CONFIG_CPU_SH7757) || \
 346         defined(CONFIG_CPU_SH7752) || \
 347         defined(CONFIG_CPU_SH7753)
 348 #if defined(CONFIG_SH_ETHER_USE_GETHER)
 349 #define SH_ETH_TYPE_GETHER
 350 #define BASE_IO_ADDR    0xfee00000
 351 #else
 352 #define SH_ETH_TYPE_ETHER
 353 #define BASE_IO_ADDR    0xfef00000
 354 #endif
 355 #elif defined(CONFIG_CPU_SH7724)
 356 #define SH_ETH_TYPE_ETHER
 357 #define BASE_IO_ADDR    0xA4600000
 358 #elif defined(CONFIG_R8A7740)
 359 #define SH_ETH_TYPE_GETHER
 360 #define BASE_IO_ADDR    0xE9A00000
 361 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
 362 #define SH_ETH_TYPE_ETHER
 363 #define BASE_IO_ADDR    0xEE700200
 364 #elif defined(CONFIG_R7S72100)
 365 #define SH_ETH_TYPE_RZ
 366 #define BASE_IO_ADDR    0xE8203000
 367 #endif
 368
 369 /*
 370  * Register's bits
 371  * Copy from Linux driver source code
 372  */
 373 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 374 /* EDSR */
 375 enum EDSR_BIT {
 376         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 377 };
 378 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 379 #endif
 380
 381 /* EDMR */
 382 enum DMAC_M_BIT {
 383         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 384 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 385         EDMR_SRST       = 0x03, /* Receive/Send reset */
 386         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 387         EDMR_EL         = 0x40, /* Litte endian */
 388 #elif defined(SH_ETH_TYPE_ETHER)
 389         EDMR_SRST       = 0x01,
 390         EMDR_DESC_R     = 0x30, /* Descriptor reserve size */
 391         EDMR_EL         = 0x40, /* Litte endian */
 392 #else
 393         EDMR_SRST = 0x01,
 394 #endif
 395 };
 396
 397 #if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
 398 # define EMDR_DESC EDMR_DL1
 399 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
 400 # define EMDR_DESC EDMR_DL0
 401 #elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
 402 # define EMDR_DESC 0
 403 #endif
 404
 405 /* RFLR */
 406 #define RFLR_RFL_MIN    0x05EE  /* Recv Frame length 1518 byte */
 407
 408 /* EDTRR */
 409 enum DMAC_T_BIT {
 410 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 411         EDTRR_TRNS = 0x03,
 412 #else
 413         EDTRR_TRNS = 0x01,
 414 #endif
 415 };
 416
 417 /* GECMR */
 418 enum GECMR_BIT {
 419 #if defined(CONFIG_CPU_SH7757) || \
 420         defined(CONFIG_CPU_SH7752) || \
 421         defined(CONFIG_CPU_SH7753)
 422         GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
 423 #else
 424         GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
 425 #endif
 426 };
 427
 428 /* EDRRR*/
 429 enum EDRRR_R_BIT {
 430         EDRRR_R = 0x01,
 431 };
 432
 433 /* TPAUSER */
 434 enum TPAUSER_BIT {
 435         TPAUSER_TPAUSE = 0x0000ffff,
 436         TPAUSER_UNLIMITED = 0,
 437 };
 438
 439 /* BCFR */
 440 enum BCFR_BIT {
 441         BCFR_RPAUSE = 0x0000ffff,
 442         BCFR_UNLIMITED = 0,
 443 };
 444
 445 /* PIR */
 446 enum PIR_BIT {
 447         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 448 };
 449
 450 /* PSR */
 451 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 452
 453 /* EESR */
 454 enum EESR_BIT {
 455 #if defined(SH_ETH_TYPE_ETHER)
 456         EESR_TWB  = 0x40000000,
 457 #else
 458         EESR_TWB  = 0xC0000000,
 459         EESR_TC1  = 0x20000000,
 460         EESR_TUC  = 0x10000000,
 461         EESR_ROC  = 0x80000000,
 462 #endif
 463         EESR_TABT = 0x04000000,
 464         EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
 465 #if defined(SH_ETH_TYPE_ETHER)
 466         EESR_ADE  = 0x00800000,
 467 #endif
 468         EESR_ECI  = 0x00400000,
 469         EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
 470         EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
 471         EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
 472 #if defined(SH_ETH_TYPE_ETHER)
 473         EESR_CND  = 0x00000800,
 474 #endif
 475         EESR_DLC  = 0x00000400,
 476         EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
 477         EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
 478         EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
 479         EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
 480         EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
 481 };
 482
 483
 484 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 485 # define TX_CHECK (EESR_TC1 | EESR_FTC)
 486 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 487                 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
 488 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
 489
 490 #else
 491 # define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
 492 # define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
 493                 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
 494 # define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
 495 #endif
 496
 497 /* EESIPR */
 498 enum DMAC_IM_BIT {
 499         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 500         DMAC_M_RABT = 0x02000000,
 501         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 502         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 503         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 504         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 505         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 506         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 507         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 508         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 509         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 510         DMAC_M_RINT1 = 0x00000001,
 511 };
 512
 513 /* Receive descriptor bit */
 514 enum RD_STS_BIT {
 515         RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
 516         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 517         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 518         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 519         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 520         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 521         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 522         RD_RFS1 = 0x00000001,
 523 };
 524 #define RDF1ST  RD_RFP1
 525 #define RDFEND  RD_RFP0
 526 #define RD_RFP  (RD_RFP1|RD_RFP0)
 527
 528 /* RDFFR*/
 529 enum RDFFR_BIT {
 530         RDFFR_RDLF = 0x01,
 531 };
 532
 533 /* FCFTR */
 534 enum FCFTR_BIT {
 535         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 536         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 537         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 538 };
 539 #define FIFO_F_D_RFF    (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
 540 #define FIFO_F_D_RFD    (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
 541
 542 /* Transfer descriptor bit */
 543 enum TD_STS_BIT {
 544 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
 545         defined(SH_ETH_TYPE_RZ)
 546         TD_TACT = 0x80000000,
 547 #else
 548         TD_TACT = 0x7fffffff,
 549 #endif
 550         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 551         TD_TFP0 = 0x10000000,
 552 };
 553 #define TDF1ST  TD_TFP1
 554 #define TDFEND  TD_TFP0
 555 #define TD_TFP  (TD_TFP1|TD_TFP0)
 556
 557 /* RMCR */
 558 enum RECV_RST_BIT { RMCR_RST = 0x01, };
 559 /* ECMR */
 560 enum FELIC_MODE_BIT {
 561 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 562         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 563         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 564 #endif
 565         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 566         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 567         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 568         ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
 569         ECMR_PRM = 0x00000001,
 570 #ifdef CONFIG_CPU_SH7724
 571         ECMR_RTM = 0x00000010,
 572 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
 573         ECMR_RTM = 0x00000004,
 574 #endif
 575
 576 };
 577
 578 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 579 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
 580                         ECMR_RXF | ECMR_TXF | ECMR_MCT)
 581 #elif defined(SH_ETH_TYPE_ETHER)
 582 #define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
 583 #else
 584 #define ECMR_CHG_DM     (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
 585 #endif
 586
 587 /* ECSR */
 588 enum ECSR_STATUS_BIT {
 589 #if defined(SH_ETH_TYPE_ETHER)
 590         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 591 #endif
 592         ECSR_LCHNG = 0x04,
 593         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 594 };
 595
 596 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 597 # define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
 598 #else
 599 # define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
 600                         ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
 601 #endif
 602
 603 /* ECSIPR */
 604 enum ECSIPR_STATUS_MASK_BIT {
 605 #if defined(SH_ETH_TYPE_ETHER)
 606         ECSIPR_BRCRXIP = 0x20,
 607         ECSIPR_PSRTOIP = 0x10,
 608 #elif defined(SH_ETY_TYPE_GETHER)
 609         ECSIPR_PSRTOIP = 0x10,
 610         ECSIPR_PHYIP = 0x08,
 611 #endif
 612         ECSIPR_LCHNGIP = 0x04,
 613         ECSIPR_MPDIP = 0x02,
 614         ECSIPR_ICDIP = 0x01,
 615 };
 616
 617 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 618 # define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 619 #else
 620 # define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
 621                                 ECSIPR_ICDIP | ECSIPR_MPDIP)
 622 #endif
 623
 624 /* APR */
 625 enum APR_BIT {
 626         APR_AP = 0x00000004,
 627 };
 628
 629 /* MPR */
 630 enum MPR_BIT {
 631         MPR_MP = 0x00000006,
 632 };
 633
 634 /* TRSCER */
 635 enum DESC_I_BIT {
 636         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 637         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 638         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 639         DESC_I_RINT1 = 0x0001,
 640 };
 641
 642 /* RPADIR */
 643 enum RPADIR_BIT {
 644         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 645         RPADIR_PADR = 0x0003f,
 646 };
 647
 648 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
 649 # define RPADIR_INIT (0x00)
 650 #else
 651 # define RPADIR_INIT (RPADIR_PADS1)
 652 #endif
 653
 654 /* FDR */
 655 enum FIFO_SIZE_BIT {
 656         FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
 657 };
 658
 659 static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
 660                                             int enum_index)
 661 {
 662 #if defined(SH_ETH_TYPE_GETHER)
 663         const u16 *reg_offset = sh_eth_offset_gigabit;
 664 #elif defined(SH_ETH_TYPE_ETHER)
 665         const u16 *reg_offset = sh_eth_offset_fast_sh4;
 666 #elif defined(SH_ETH_TYPE_RZ)
 667         const u16 *reg_offset = sh_eth_offset_rz;
 668 #else
 669 #error
 670 #endif
 671         return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
 672 }
 673
 674 static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
 675                                 int enum_index)
 676 {
 677         outl(data, sh_eth_reg_addr(eth, enum_index));
 678 }
 679
 680 static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
 681                                         int enum_index)
 682 {
 683         return inl(sh_eth_reg_addr(eth, enum_index));
 684 }