2 * SMSC LAN9[12]1[567] Network driver
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <linux/types.h>
30 #define DRIVERNAME "smc911x"
32 #if defined (CONFIG_SMC911X_32_BIT) && \
33 defined (CONFIG_SMC911X_16_BIT) && \
34 defined(CONFIG_SMC911X_CPLD)
35 #error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
36 CONFIG_SMC911X_16_BIT shall be set"
39 #if defined (CONFIG_SMC911X_32_BIT)
40 static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
42 return *(volatile u32*)(dev->iobase + offset);
44 u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
45 __attribute__((weak, alias("__smc911x_reg_read")));
47 static inline void __smc911x_reg_write(struct eth_device *dev,
50 *(volatile u32*)(dev->iobase + offset) = val;
52 void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
53 __attribute__((weak, alias("__smc911x_reg_write")));
54 #elif defined (CONFIG_SMC911X_16_BIT)
55 static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
57 volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
58 return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
60 static inline void smc911x_reg_write(struct eth_device *dev,
63 *(volatile u16 *)(dev->iobase + offset) = (u16)val;
64 *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
66 #elif defined(CONFIG_SMC911X_CPLD)
67 #include <asm/arch/imx_spi_cpld.h>
68 static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
70 return cpld_reg_xfer(offset, 0x0, 1) | \
71 (cpld_reg_xfer(offset + 0x2, 0x0, 1) << 16);
73 static void smc911x_reg_write(struct eth_device *dev,
76 cpld_reg_xfer(offset, val, 0);
77 cpld_reg_xfer(offset + 0x2, (val >> 16), 0);
80 #error "SMC911X: undefined bus width"
81 #endif /* CONFIG_SMC911X_16_BIT */
83 /* Below are the register offsets and bit definitions
84 * of the Lan911x memory space
86 #define RX_DATA_FIFO 0x00
88 #define TX_DATA_FIFO 0x20
89 #define TX_CMD_A_INT_ON_COMP 0x80000000
90 #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
91 #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
92 #define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
93 #define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
94 #define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
95 #define TX_CMD_A_INT_FIRST_SEG 0x00002000
96 #define TX_CMD_A_INT_LAST_SEG 0x00001000
97 #define TX_CMD_A_BUF_SIZE 0x000007FF
98 #define TX_CMD_B_PKT_TAG 0xFFFF0000
99 #define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
100 #define TX_CMD_B_DISABLE_PADDING 0x00001000
101 #define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
103 #define RX_STATUS_FIFO 0x40
104 #define RX_STS_PKT_LEN 0x3FFF0000
105 #define RX_STS_ES 0x00008000
106 #define RX_STS_BCST 0x00002000
107 #define RX_STS_LEN_ERR 0x00001000
108 #define RX_STS_RUNT_ERR 0x00000800
109 #define RX_STS_MCAST 0x00000400
110 #define RX_STS_TOO_LONG 0x00000080
111 #define RX_STS_COLL 0x00000040
112 #define RX_STS_ETH_TYPE 0x00000020
113 #define RX_STS_WDOG_TMT 0x00000010
114 #define RX_STS_MII_ERR 0x00000008
115 #define RX_STS_DRIBBLING 0x00000004
116 #define RX_STS_CRC_ERR 0x00000002
117 #define RX_STATUS_FIFO_PEEK 0x44
118 #define TX_STATUS_FIFO 0x48
119 #define TX_STS_TAG 0xFFFF0000
120 #define TX_STS_ES 0x00008000
121 #define TX_STS_LOC 0x00000800
122 #define TX_STS_NO_CARR 0x00000400
123 #define TX_STS_LATE_COLL 0x00000200
124 #define TX_STS_MANY_COLL 0x00000100
125 #define TX_STS_COLL_CNT 0x00000078
126 #define TX_STS_MANY_DEFER 0x00000004
127 #define TX_STS_UNDERRUN 0x00000002
128 #define TX_STS_DEFERRED 0x00000001
129 #define TX_STATUS_FIFO_PEEK 0x4C
131 #define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
132 #define ID_REV_REV_ID 0x0000FFFF /* RO */
135 #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
136 #define INT_CFG_INT_DEAS_CLR 0x00004000
137 #define INT_CFG_INT_DEAS_STS 0x00002000
138 #define INT_CFG_IRQ_INT 0x00001000 /* RO */
139 #define INT_CFG_IRQ_EN 0x00000100 /* R/W */
140 /* R/W Not Affected by SW Reset */
141 #define INT_CFG_IRQ_POL 0x00000010
142 /* R/W Not Affected by SW Reset */
143 #define INT_CFG_IRQ_TYPE 0x00000001
146 #define INT_STS_SW_INT 0x80000000 /* R/WC */
147 #define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
148 #define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
149 #define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
150 #define INT_STS_RXDF_INT 0x00400000 /* R/WC */
151 #define INT_STS_TX_IOC 0x00200000 /* R/WC */
152 #define INT_STS_RXD_INT 0x00100000 /* R/WC */
153 #define INT_STS_GPT_INT 0x00080000 /* R/WC */
154 #define INT_STS_PHY_INT 0x00040000 /* RO */
155 #define INT_STS_PME_INT 0x00020000 /* R/WC */
156 #define INT_STS_TXSO 0x00010000 /* R/WC */
157 #define INT_STS_RWT 0x00008000 /* R/WC */
158 #define INT_STS_RXE 0x00004000 /* R/WC */
159 #define INT_STS_TXE 0x00002000 /* R/WC */
160 /*#define INT_STS_ERX 0x00001000*/ /* R/WC */
161 #define INT_STS_TDFU 0x00000800 /* R/WC */
162 #define INT_STS_TDFO 0x00000400 /* R/WC */
163 #define INT_STS_TDFA 0x00000200 /* R/WC */
164 #define INT_STS_TSFF 0x00000100 /* R/WC */
165 #define INT_STS_TSFL 0x00000080 /* R/WC */
166 /*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
167 #define INT_STS_RDFO 0x00000040 /* R/WC */
168 #define INT_STS_RDFL 0x00000020 /* R/WC */
169 #define INT_STS_RSFF 0x00000010 /* R/WC */
170 #define INT_STS_RSFL 0x00000008 /* R/WC */
171 #define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
172 #define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
173 #define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
175 #define INT_EN_SW_INT_EN 0x80000000 /* R/W */
176 #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
177 #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
178 #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
179 /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
180 #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
181 #define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
182 #define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
183 #define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
184 #define INT_EN_PME_INT_EN 0x00020000 /* R/W */
185 #define INT_EN_TXSO_EN 0x00010000 /* R/W */
186 #define INT_EN_RWT_EN 0x00008000 /* R/W */
187 #define INT_EN_RXE_EN 0x00004000 /* R/W */
188 #define INT_EN_TXE_EN 0x00002000 /* R/W */
189 /*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
190 #define INT_EN_TDFU_EN 0x00000800 /* R/W */
191 #define INT_EN_TDFO_EN 0x00000400 /* R/W */
192 #define INT_EN_TDFA_EN 0x00000200 /* R/W */
193 #define INT_EN_TSFF_EN 0x00000100 /* R/W */
194 #define INT_EN_TSFL_EN 0x00000080 /* R/W */
195 /*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
196 #define INT_EN_RDFO_EN 0x00000040 /* R/W */
197 #define INT_EN_RDFL_EN 0x00000020 /* R/W */
198 #define INT_EN_RSFF_EN 0x00000010 /* R/W */
199 #define INT_EN_RSFL_EN 0x00000008 /* R/W */
200 #define INT_EN_GPIO2_INT 0x00000004 /* R/W */
201 #define INT_EN_GPIO1_INT 0x00000002 /* R/W */
202 #define INT_EN_GPIO0_INT 0x00000001 /* R/W */
204 #define BYTE_TEST 0x64
205 #define FIFO_INT 0x68
206 #define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
207 #define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
208 #define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
209 #define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
212 #define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
213 #define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
214 #define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
215 #define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
216 #define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
217 #define RX_CFG_RX_DUMP 0x00008000 /* R/W */
218 #define RX_CFG_RXDOFF 0x00001F00 /* R/W */
219 /*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
222 /*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
223 /* R/W Self Clearing */
224 /*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
225 #define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
226 #define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
227 #define TX_CFG_TXSAO 0x00000004 /* R/W */
228 #define TX_CFG_TX_ON 0x00000002 /* R/W */
229 #define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
232 #define HW_CFG_TTM 0x00200000 /* R/W */
233 #define HW_CFG_SF 0x00100000 /* R/W */
234 #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
235 #define HW_CFG_TR 0x00003000 /* R/W */
236 #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
237 #define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
238 #define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
239 #define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
240 #define HW_CFG_SMI_SEL 0x00000010 /* R/W */
241 #define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
242 #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
243 #define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
244 #define HW_CFG_SRST_TO 0x00000002 /* RO */
245 #define HW_CFG_SRST 0x00000001 /* Self Clearing */
247 #define RX_DP_CTRL 0x78
248 #define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
249 #define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
251 #define RX_FIFO_INF 0x7C
252 #define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
253 #define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
255 #define TX_FIFO_INF 0x80
256 #define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
257 #define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
259 #define PMT_CTRL 0x84
260 #define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
261 #define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
262 #define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
263 #define PMT_CTRL_ED_EN 0x00000100 /* R/W */
264 /* R/W Not Affected by SW Reset */
265 #define PMT_CTRL_PME_TYPE 0x00000040
266 #define PMT_CTRL_WUPS 0x00000030 /* R/WC */
267 #define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
268 #define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
269 #define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
270 #define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
271 #define PMT_CTRL_PME_IND 0x00000008 /* R/W */
272 #define PMT_CTRL_PME_POL 0x00000004 /* R/W */
273 /* R/W Not Affected by SW Reset */
274 #define PMT_CTRL_PME_EN 0x00000002
275 #define PMT_CTRL_READY 0x00000001 /* RO */
277 #define GPIO_CFG 0x88
278 #define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
279 #define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
280 #define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
281 #define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
282 #define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
283 #define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
284 #define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
285 #define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
286 #define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
287 #define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
288 #define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
289 #define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
290 #define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
291 #define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
292 #define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
293 #define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
294 #define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
295 #define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
298 #define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
299 #define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
302 #define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
305 #define FREE_RUN 0x9C
307 #define MAC_CSR_CMD 0xA4
308 #define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
309 #define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
310 #define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
312 #define MAC_CSR_DATA 0xA8
314 #define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
315 #define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
316 #define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
317 #define AFC_CFG_FCMULT 0x00000008 /* R/W */
318 #define AFC_CFG_FCBRD 0x00000004 /* R/W */
319 #define AFC_CFG_FCADD 0x00000002 /* R/W */
320 #define AFC_CFG_FCANY 0x00000001 /* R/W */
323 #define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
324 #define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
325 #define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
326 #define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
327 #define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
328 #define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
329 #define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
330 #define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
331 #define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
332 #define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
333 #define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
334 #define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
335 #define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
337 #define E2P_DATA 0xB4
338 #define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
339 /* end of LAN register offsets and bit definitions */
341 /* MAC Control and Status registers */
342 #define MAC_CR 0x01 /* R/W */
344 /* MAC_CR - MAC Control Register */
345 #define MAC_CR_RXALL 0x80000000
346 /* TODO: delete this bit? It is not described in the data sheet. */
347 #define MAC_CR_HBDIS 0x10000000
348 #define MAC_CR_RCVOWN 0x00800000
349 #define MAC_CR_LOOPBK 0x00200000
350 #define MAC_CR_FDPX 0x00100000
351 #define MAC_CR_MCPAS 0x00080000
352 #define MAC_CR_PRMS 0x00040000
353 #define MAC_CR_INVFILT 0x00020000
354 #define MAC_CR_PASSBAD 0x00010000
355 #define MAC_CR_HFILT 0x00008000
356 #define MAC_CR_HPFILT 0x00002000
357 #define MAC_CR_LCOLL 0x00001000
358 #define MAC_CR_BCAST 0x00000800
359 #define MAC_CR_DISRTY 0x00000400
360 #define MAC_CR_PADSTR 0x00000100
361 #define MAC_CR_BOLMT_MASK 0x000000C0
362 #define MAC_CR_DFCHK 0x00000020
363 #define MAC_CR_TXEN 0x00000008
364 #define MAC_CR_RXEN 0x00000004
366 #define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
367 #define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
368 #define HASHH 0x04 /* R/W */
369 #define HASHL 0x05 /* R/W */
371 #define MII_ACC 0x06 /* R/W */
372 #define MII_ACC_PHY_ADDR 0x0000F800
373 #define MII_ACC_MIIRINDA 0x000007C0
374 #define MII_ACC_MII_WRITE 0x00000002
375 #define MII_ACC_MII_BUSY 0x00000001
377 #define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
379 #define FLOW 0x08 /* R/W */
380 #define FLOW_FCPT 0xFFFF0000
381 #define FLOW_FCPASS 0x00000004
382 #define FLOW_FCEN 0x00000002
383 #define FLOW_FCBSY 0x00000001
385 #define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
386 #define VLAN1_VTI1 0x0000ffff
388 #define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
389 #define VLAN2_VTI2 0x0000ffff
391 #define WUFF 0x0B /* WO */
393 #define WUCSR 0x0C /* R/W */
394 #define WUCSR_GUE 0x00000200
395 #define WUCSR_WUFR 0x00000040
396 #define WUCSR_MPR 0x00000020
397 #define WUCSR_WAKE_EN 0x00000004
398 #define WUCSR_MPEN 0x00000002
401 #define CHIP_89218 0x218a
402 #define CHIP_9115 0x115
403 #define CHIP_9116 0x116
404 #define CHIP_9117 0x117
405 #define CHIP_9118 0x118
406 #define CHIP_9211 0x9211
407 #define CHIP_9215 0x115a
408 #define CHIP_9216 0x116a
409 #define CHIP_9217 0x117a
410 #define CHIP_9218 0x118a
411 #define CHIP_9220 0x9220
412 #define CHIP_9221 0x9221
419 static const struct chip_id chip_ids[] = {
420 { CHIP_89218, "LAN89218" },
421 { CHIP_9115, "LAN9115" },
422 { CHIP_9116, "LAN9116" },
423 { CHIP_9117, "LAN9117" },
424 { CHIP_9118, "LAN9118" },
425 { CHIP_9211, "LAN9211" },
426 { CHIP_9215, "LAN9215" },
427 { CHIP_9216, "LAN9216" },
428 { CHIP_9217, "LAN9217" },
429 { CHIP_9218, "LAN9218" },
430 { CHIP_9220, "LAN9220" },
431 { CHIP_9221, "LAN9221" },
435 static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
437 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
439 smc911x_reg_write(dev, MAC_CSR_CMD,
440 MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
441 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
444 return smc911x_reg_read(dev, MAC_CSR_DATA);
447 static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
449 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
451 smc911x_reg_write(dev, MAC_CSR_DATA, data);
452 smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
453 while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
457 static int smc911x_detect_chip(struct eth_device *dev)
459 unsigned long val, i;
461 val = smc911x_reg_read(dev, BYTE_TEST);
462 if (val == 0xffffffff) {
463 /* Special case -- no chip present */
465 } else if (val != 0x87654321) {
466 printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
470 val = smc911x_reg_read(dev, ID_REV) >> 16;
471 for (i = 0; chip_ids[i].id != 0; i++) {
472 if (chip_ids[i].id == val) break;
474 if (!chip_ids[i].id) {
475 printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
479 dev->priv = (void *)&chip_ids[i];
484 static void smc911x_reset(struct eth_device *dev)
489 * Take out of PM setting first
490 * Device is already wake up if PMT_CTRL_READY bit is set
492 if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
493 /* Write to the bytetest will take out of powerdown */
494 smc911x_reg_write(dev, BYTE_TEST, 0x0);
499 !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
503 ": timeout waiting for PM restore\n");
508 /* Disable interrupts */
509 smc911x_reg_write(dev, INT_EN, 0);
511 smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
514 while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
518 printf(DRIVERNAME ": reset timeout\n");
522 /* Reset the FIFO level and flow control settings */
523 smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
524 smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
526 /* Set to LED outputs */
527 smc911x_reg_write(dev, GPIO_CFG, 0x70070000);