drivers/spi/atmel_dataflash_spi.c

   1 /*
   2  * Driver for ATMEL DataFlash support
   3  * Author : Hamid Ikdoumi (Atmel)
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * This driver desperately needs rework:
  10  *
  11  * - use structure SoC access
  12  * - get rid of including asm/arch/at91_spi.h
  13  * - remove asm/arch/at91_spi.h
  14  * - get rid of all CONFIG_ATMEL_LEGACY defines and uses
  15  *
  16  * 02-Aug-2010 Reinhard Meyer <uboot@emk-elektronik.de>
  17  */
  18
  19 #include <common.h>
  20 #ifndef CONFIG_ATMEL_LEGACY
  21 # define CONFIG_ATMEL_LEGACY
  22 #endif
  23 #include <spi.h>
  24 #include <malloc.h>
  25
  26 #include <asm/io.h>
  27
  28 #include <asm/arch/clk.h>
  29 #include <asm/arch/hardware.h>
  30
  31 #include "atmel_spi.h"
  32
  33 #include <asm/arch/gpio.h>
  34 #include <asm/arch/at91_pio.h>
  35 #include <asm/arch/at91_spi.h>
  36
  37 #include <dataflash.h>
  38
  39 #define AT91_SPI_PCS0_DATAFLASH_CARD    0xE     /* Chip Select 0: NPCS0%1110 */
  40 #define AT91_SPI_PCS1_DATAFLASH_CARD    0xD     /* Chip Select 1: NPCS1%1101 */
  41 #define AT91_SPI_PCS2_DATAFLASH_CARD    0xB     /* Chip Select 2: NPCS2%1011 */
  42 #define AT91_SPI_PCS3_DATAFLASH_CARD    0x7     /* Chip Select 3: NPCS3%0111 */
  43
  44 void AT91F_SpiInit(void)
  45 {
  46         /* Reset the SPI */
  47         writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR);
  48
  49         /* Configure SPI in Master Mode with No CS selected !!! */
  50         writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
  51                ATMEL_BASE_SPI0 + AT91_SPI_MR);
  52
  53         /* Configure CS0 */
  54         writel(AT91_SPI_NCPHA |
  55                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  56                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  57                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  58                ATMEL_BASE_SPI0 + AT91_SPI_CSR(0));
  59
  60 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
  61         /* Configure CS1 */
  62         writel(AT91_SPI_NCPHA |
  63                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  64                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  65                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  66                ATMEL_BASE_SPI0 + AT91_SPI_CSR(1));
  67 #endif
  68 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
  69         /* Configure CS2 */
  70         writel(AT91_SPI_NCPHA |
  71                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  72                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  73                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  74                ATMEL_BASE_SPI0 + AT91_SPI_CSR(2));
  75 #endif
  76 #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
  77         /* Configure CS3 */
  78         writel(AT91_SPI_NCPHA |
  79                (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  80                (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  81                ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  82                ATMEL_BASE_SPI0 + AT91_SPI_CSR(3));
  83 #endif
  84
  85         /* SPI_Enable */
  86         writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
  87
  88         while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS))
  89                 ;
  90
  91         /*
  92          * Add tempo to get SPI in a safe state.
  93          * Should not be needed for new silicon (Rev B)
  94          */
  95         udelay(500000);
  96         readl(ATMEL_BASE_SPI0 + AT91_SPI_SR);
  97         readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR);
  98
  99 }
 100
 101 void AT91F_SpiEnable(int cs)
 102 {
 103         unsigned long mode;
 104
 105         switch (cs) {
 106         case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
 107                 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
 108                 mode &= 0xFFF0FFFF;
 109                 writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 110                        ATMEL_BASE_SPI0 + AT91_SPI_MR);
 111                 break;
 112         case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
 113                 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
 114                 mode &= 0xFFF0FFFF;
 115                 writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 116                        ATMEL_BASE_SPI0 + AT91_SPI_MR);
 117                 break;
 118         case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
 119                 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
 120                 mode &= 0xFFF0FFFF;
 121                 writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 122                        ATMEL_BASE_SPI0 + AT91_SPI_MR);
 123                 break;
 124         case 3:
 125                 mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
 126                 mode &= 0xFFF0FFFF;
 127                 writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 128                        ATMEL_BASE_SPI0 + AT91_SPI_MR);
 129                 break;
 130         }
 131
 132         /* SPI_Enable */
 133         writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
 134 }
 135
 136 unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
 137
 138 unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
 139 {
 140         unsigned int timeout;
 141         unsigned int timebase;
 142
 143         pDesc->state = BUSY;
 144
 145         writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
 146                 ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
 147
 148         /* Initialize the Transmit and Receive Pointer */
 149         writel((unsigned int)pDesc->rx_cmd_pt,
 150                 ATMEL_BASE_SPI0 + AT91_SPI_RPR);
 151         writel((unsigned int)pDesc->tx_cmd_pt,
 152                 ATMEL_BASE_SPI0 + AT91_SPI_TPR);
 153
 154         /* Intialize the Transmit and Receive Counters */
 155         writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR);
 156         writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR);
 157
 158         if (pDesc->tx_data_size != 0) {
 159                 /* Initialize the Next Transmit and Next Receive Pointer */
 160                 writel((unsigned int)pDesc->rx_data_pt,
 161                         ATMEL_BASE_SPI0 + AT91_SPI_RNPR);
 162                 writel((unsigned int)pDesc->tx_data_pt,
 163                         ATMEL_BASE_SPI0 + AT91_SPI_TNPR);
 164
 165                 /* Intialize the Next Transmit and Next Receive Counters */
 166                 writel(pDesc->rx_data_size,
 167                         ATMEL_BASE_SPI0 + AT91_SPI_RNCR);
 168                 writel(pDesc->tx_data_size,
 169                         ATMEL_BASE_SPI0 + AT91_SPI_TNCR);
 170         }
 171
 172         /* arm simple, non interrupt dependent timer */
 173         timebase = get_timer(0);
 174         timeout = 0;
 175
 176         writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN,
 177                 ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
 178         while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
 179                 ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT))
 180                 ;
 181         writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
 182                 ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
 183         pDesc->state = IDLE;
 184
 185         if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
 186                 printf("Error Timeout\n\r");
 187                 return DATAFLASH_ERROR;
 188         }
 189
 190         return DATAFLASH_OK;
 191 }