drivers/usb/host/ehci-hcd.c

   1 /*-
   2  * Copyright (c) 2007-2008, Juniper Networks, Inc.
   3  * Copyright (c) 2008, Excito Elektronik i Skåne AB
   4  * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
   5  *
   6  * All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation version 2 of
  11  * the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #include <common.h>
  24 #include <asm/byteorder.h>
  25 #include <asm/unaligned.h>
  26 #include <usb.h>
  27 #include <asm/io.h>
  28 #include <malloc.h>
  29 #include <watchdog.h>
  30
  31 #include "ehci.h"
  32
  33 int rootdev;
  34 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  35 volatile struct ehci_hcor *hcor;
  36
  37 static uint16_t portreset;
  38 DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
  39
  40 #define ALIGN_END_ADDR(type, ptr, size)                 \
  41         ((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
  42
  43 static struct descriptor {
  44         struct usb_hub_descriptor hub;
  45         struct usb_device_descriptor device;
  46         struct usb_linux_config_descriptor config;
  47         struct usb_linux_interface_descriptor interface;
  48         struct usb_endpoint_descriptor endpoint;
  49 }  __attribute__ ((packed)) descriptor = {
  50         {
  51                 0x8,            /* bDescLength */
  52                 0x29,           /* bDescriptorType: hub descriptor */
  53                 2,              /* bNrPorts -- runtime modified */
  54                 0,              /* wHubCharacteristics */
  55                 10,             /* bPwrOn2PwrGood */
  56                 0,              /* bHubCntrCurrent */
  57                 {},             /* Device removable */
  58                 {}              /* at most 7 ports! XXX */
  59         },
  60         {
  61                 0x12,           /* bLength */
  62                 1,              /* bDescriptorType: UDESC_DEVICE */
  63                 cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  64                 9,              /* bDeviceClass: UDCLASS_HUB */
  65                 0,              /* bDeviceSubClass: UDSUBCLASS_HUB */
  66                 1,              /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  67                 64,             /* bMaxPacketSize: 64 bytes */
  68                 0x0000,         /* idVendor */
  69                 0x0000,         /* idProduct */
  70                 cpu_to_le16(0x0100), /* bcdDevice */
  71                 1,              /* iManufacturer */
  72                 2,              /* iProduct */
  73                 0,              /* iSerialNumber */
  74                 1               /* bNumConfigurations: 1 */
  75         },
  76         {
  77                 0x9,
  78                 2,              /* bDescriptorType: UDESC_CONFIG */
  79                 cpu_to_le16(0x19),
  80                 1,              /* bNumInterface */
  81                 1,              /* bConfigurationValue */
  82                 0,              /* iConfiguration */
  83                 0x40,           /* bmAttributes: UC_SELF_POWER */
  84                 0               /* bMaxPower */
  85         },
  86         {
  87                 0x9,            /* bLength */
  88                 4,              /* bDescriptorType: UDESC_INTERFACE */
  89                 0,              /* bInterfaceNumber */
  90                 0,              /* bAlternateSetting */
  91                 1,              /* bNumEndpoints */
  92                 9,              /* bInterfaceClass: UICLASS_HUB */
  93                 0,              /* bInterfaceSubClass: UISUBCLASS_HUB */
  94                 0,              /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  95                 0               /* iInterface */
  96         },
  97         {
  98                 0x7,            /* bLength */
  99                 5,              /* bDescriptorType: UDESC_ENDPOINT */
 100                 0x81,           /* bEndpointAddress:
 101                                  * UE_DIR_IN | EHCI_INTR_ENDPT
 102                                  */
 103                 3,              /* bmAttributes: UE_INTERRUPT */
 104                 8,              /* wMaxPacketSize */
 105                 255             /* bInterval */
 106         },
 107 };
 108
 109 #if defined(CONFIG_EHCI_IS_TDI)
 110 #define ehci_is_TDI()   (1)
 111 #else
 112 #define ehci_is_TDI()   (0)
 113 #endif
 114
 115 void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 116 {
 117         mdelay(50);
 118 }
 119
 120 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 121         __attribute__((weak, alias("__ehci_powerup_fixup")));
 122
 123 static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
 124 {
 125         uint32_t result;
 126         do {
 127                 result = ehci_readl(ptr);
 128                 udelay(5);
 129                 if (result == ~(uint32_t)0)
 130                         return -1;
 131                 result &= mask;
 132                 if (result == done)
 133                         return 0;
 134                 usec--;
 135         } while (usec > 0);
 136         return -1;
 137 }
 138
 139 static int ehci_reset(void)
 140 {
 141         uint32_t cmd;
 142         uint32_t tmp;
 143         uint32_t *reg_ptr;
 144         int ret = 0;
 145
 146         cmd = ehci_readl(&hcor->or_usbcmd);
 147         cmd = (cmd & ~CMD_RUN) | CMD_RESET;
 148         ehci_writel(&hcor->or_usbcmd, cmd);
 149         ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
 150         if (ret < 0) {
 151                 printf("EHCI fail to reset\n");
 152                 goto out;
 153         }
 154
 155         if (ehci_is_TDI()) {
 156                 reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
 157                 tmp = ehci_readl(reg_ptr);
 158                 tmp |= USBMODE_CM_HC;
 159 #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
 160                 tmp |= USBMODE_BE;
 161 #endif
 162                 ehci_writel(reg_ptr, tmp);
 163         }
 164
 165 #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
 166         cmd = ehci_readl(&hcor->or_txfilltuning);
 167         cmd &= ~TXFIFO_THRESH_MASK;
 168         cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
 169         ehci_writel(&hcor->or_txfilltuning, cmd);
 170 #endif
 171 out:
 172         return ret;
 173 }
 174
 175 static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
 176 {
 177         uint32_t delta, next;
 178         uint32_t addr = (uint32_t)buf;
 179         int idx;
 180
 181         if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
 182                 debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
 183
 184         flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
 185
 186         idx = 0;
 187         while (idx < QT_BUFFER_CNT) {
 188                 td->qt_buffer[idx] = cpu_to_hc32(addr);
 189                 td->qt_buffer_hi[idx] = 0;
 190                 next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
 191                 delta = next - addr;
 192                 if (delta >= sz)
 193                         break;
 194                 sz -= delta;
 195                 addr = next;
 196                 idx++;
 197         }
 198
 199         if (idx == QT_BUFFER_CNT) {
 200                 printf("out of buffer pointers (%u bytes left)\n", sz);
 201                 return -1;
 202         }
 203
 204         return 0;
 205 }
 206
 207 static int
 208 ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
 209                    int length, struct devrequest *req)
 210 {
 211         ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
 212         struct qTD *qtd;
 213         int qtd_count = 0;
 214         int qtd_counter = 0;
 215
 216         volatile struct qTD *vtd;
 217         unsigned long ts;
 218         uint32_t *tdp;
 219         uint32_t endpt, maxpacket, token, usbsts;
 220         uint32_t c, toggle;
 221         uint32_t cmd;
 222         int timeout;
 223         int ret = 0;
 224
 225         debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
 226               buffer, length, req);
 227         if (req != NULL)
 228                 debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
 229                       req->request, req->request,
 230                       req->requesttype, req->requesttype,
 231                       le16_to_cpu(req->value), le16_to_cpu(req->value),
 232                       le16_to_cpu(req->index));
 233
 234 #define PKT_ALIGN       512
 235         /*
 236          * The USB transfer is split into qTD transfers. Eeach qTD transfer is
 237          * described by a transfer descriptor (the qTD). The qTDs form a linked
 238          * list with a queue head (QH).
 239          *
 240          * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
 241          * have its beginning in a qTD transfer and its end in the following
 242          * one, so the qTD transfer lengths have to be chosen accordingly.
 243          *
 244          * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
 245          * single pages. The first data buffer can start at any offset within a
 246          * page (not considering the cache-line alignment issues), while the
 247          * following buffers must be page-aligned. There is no alignment
 248          * constraint on the size of a qTD transfer.
 249          */
 250         if (req != NULL)
 251                 /* 1 qTD will be needed for SETUP, and 1 for ACK. */
 252                 qtd_count += 1 + 1;
 253         if (length > 0 || req == NULL) {
 254                 /*
 255                  * Determine the qTD transfer size that will be used for the
 256                  * data payload (not considering the first qTD transfer, which
 257                  * may be longer or shorter, and the final one, which may be
 258                  * shorter).
 259                  *
 260                  * In order to keep each packet within a qTD transfer, the qTD
 261                  * transfer size is aligned to PKT_ALIGN, which is a multiple of
 262                  * wMaxPacketSize (except in some cases for interrupt transfers,
 263                  * see comment in submit_int_msg()).
 264                  *
 265                  * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
 266                  * QT_BUFFER_CNT full pages will be used.
 267                  */
 268                 int xfr_sz = QT_BUFFER_CNT;
 269                 /*
 270                  * However, if the input buffer is not aligned to PKT_ALIGN, the
 271                  * qTD transfer size will be one page shorter, and the first qTD
 272                  * data buffer of each transfer will be page-unaligned.
 273                  */
 274                 if ((uint32_t)buffer & (PKT_ALIGN - 1))
 275                         xfr_sz--;
 276                 /* Convert the qTD transfer size to bytes. */
 277                 xfr_sz *= EHCI_PAGE_SIZE;
 278                 /*
 279                  * Approximate by excess the number of qTDs that will be
 280                  * required for the data payload. The exact formula is way more
 281                  * complicated and saves at most 2 qTDs, i.e. a total of 128
 282                  * bytes.
 283                  */
 284                 qtd_count += 2 + length / xfr_sz;
 285         }
 286 /*
 287  * Threshold value based on the worst-case total size of the allocated qTDs for
 288  * a mass-storage transfer of 65535 blocks of 512 bytes.
 289  */
 290 #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
 291 #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
 292 #endif
 293         qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
 294         if (qtd == NULL) {
 295                 printf("unable to allocate TDs\n");
 296                 return -1;
 297         }
 298
 299         memset(qh, 0, sizeof(struct QH));
 300         memset(qtd, 0, qtd_count * sizeof(*qtd));
 301
 302         toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
 303
 304         /*
 305          * Setup QH (3.6 in ehci-r10.pdf)
 306          *
 307          *   qh_link ................. 03-00 H
 308          *   qh_endpt1 ............... 07-04 H
 309          *   qh_endpt2 ............... 0B-08 H
 310          * - qh_curtd
 311          *   qh_overlay.qt_next ...... 13-10 H
 312          * - qh_overlay.qt_altnext
 313          */
 314         qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
 315         c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
 316         maxpacket = usb_maxpacket(dev, pipe);
 317         endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
 318                 QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
 319                 QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
 320                 QH_ENDPT1_EPS(usb_pipespeed(pipe)) |
 321                 QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
 322                 QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
 323         qh->qh_endpt1 = cpu_to_hc32(endpt);
 324         endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
 325                 QH_ENDPT2_HUBADDR(dev->parent->devnum) |
 326                 QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
 327         qh->qh_endpt2 = cpu_to_hc32(endpt);
 328         qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 329
 330         tdp = &qh->qh_overlay.qt_next;
 331
 332         if (req != NULL) {
 333                 /*
 334                  * Setup request qTD (3.5 in ehci-r10.pdf)
 335                  *
 336                  *   qt_next ................ 03-00 H
 337                  *   qt_altnext ............. 07-04 H
 338                  *   qt_token ............... 0B-08 H
 339                  *
 340                  *   [ buffer, buffer_hi ] loaded with "req".
 341                  */
 342                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 343                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 344                 token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
 345                         QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 346                         QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
 347                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 348                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 349                 if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
 350                         printf("unable to construct SETUP TD\n");
 351                         goto fail;
 352                 }
 353                 /* Update previous qTD! */
 354                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
 355                 tdp = &qtd[qtd_counter++].qt_next;
 356                 toggle = 1;
 357         }
 358
 359         if (length > 0 || req == NULL) {
 360                 uint8_t *buf_ptr = buffer;
 361                 int left_length = length;
 362
 363                 do {
 364                         /*
 365                          * Determine the size of this qTD transfer. By default,
 366                          * QT_BUFFER_CNT full pages can be used.
 367                          */
 368                         int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
 369                         /*
 370                          * However, if the input buffer is not page-aligned, the
 371                          * portion of the first page before the buffer start
 372                          * offset within that page is unusable.
 373                          */
 374                         xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
 375                         /*
 376                          * In order to keep each packet within a qTD transfer,
 377                          * align the qTD transfer size to PKT_ALIGN.
 378                          */
 379                         xfr_bytes &= ~(PKT_ALIGN - 1);
 380                         /*
 381                          * This transfer may be shorter than the available qTD
 382                          * transfer size that has just been computed.
 383                          */
 384                         xfr_bytes = min(xfr_bytes, left_length);
 385
 386                         /*
 387                          * Setup request qTD (3.5 in ehci-r10.pdf)
 388                          *
 389                          *   qt_next ................ 03-00 H
 390                          *   qt_altnext ............. 07-04 H
 391                          *   qt_token ............... 0B-08 H
 392                          *
 393                          *   [ buffer, buffer_hi ] loaded with "buffer".
 394                          */
 395                         qtd[qtd_counter].qt_next =
 396                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 397                         qtd[qtd_counter].qt_altnext =
 398                                         cpu_to_hc32(QT_NEXT_TERMINATE);
 399                         token = QT_TOKEN_DT(toggle) |
 400                                 QT_TOKEN_TOTALBYTES(xfr_bytes) |
 401                                 QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
 402                                 QT_TOKEN_CERR(3) |
 403                                 QT_TOKEN_PID(usb_pipein(pipe) ?
 404                                         QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
 405                                 QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 406                         qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 407                         if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
 408                                                 xfr_bytes)) {
 409                                 printf("unable to construct DATA TD\n");
 410                                 goto fail;
 411                         }
 412                         /* Update previous qTD! */
 413                         *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
 414                         tdp = &qtd[qtd_counter++].qt_next;
 415                         /*
 416                          * Data toggle has to be adjusted since the qTD transfer
 417                          * size is not always an even multiple of
 418                          * wMaxPacketSize.
 419                          */
 420                         if ((xfr_bytes / maxpacket) & 1)
 421                                 toggle ^= 1;
 422                         buf_ptr += xfr_bytes;
 423                         left_length -= xfr_bytes;
 424                 } while (left_length > 0);
 425         }
 426
 427         if (req != NULL) {
 428                 /*
 429                  * Setup request qTD (3.5 in ehci-r10.pdf)
 430                  *
 431                  *   qt_next ................ 03-00 H
 432                  *   qt_altnext ............. 07-04 H
 433                  *   qt_token ............... 0B-08 H
 434                  */
 435                 qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 436                 qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 437                 token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
 438                         QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
 439                         QT_TOKEN_PID(usb_pipein(pipe) ?
 440                                 QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
 441                         QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
 442                 qtd[qtd_counter].qt_token = cpu_to_hc32(token);
 443                 /* Update previous qTD! */
 444                 *tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
 445                 tdp = &qtd[qtd_counter++].qt_next;
 446         }
 447
 448         qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
 449
 450         /* Flush dcache */
 451         flush_dcache_range((uint32_t)qh_list,
 452                 ALIGN_END_ADDR(struct QH, qh_list, 1));
 453         flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
 454         flush_dcache_range((uint32_t)qtd,
 455                            ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 456
 457         /* Set async. queue head pointer. */
 458         ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
 459
 460         usbsts = ehci_readl(&hcor->or_usbsts);
 461         ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
 462
 463         /* Enable async. schedule. */
 464         cmd = ehci_readl(&hcor->or_usbcmd);
 465         cmd |= CMD_ASE;
 466         ehci_writel(&hcor->or_usbcmd, cmd);
 467
 468         ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS,
 469                         100 * 1000);
 470         if (ret < 0) {
 471                 printf("EHCI fail timeout STS_ASS set\n");
 472                 goto fail;
 473         }
 474
 475         /* Wait for TDs to be processed. */
 476         ts = get_timer(0);
 477         vtd = &qtd[qtd_counter - 1];
 478         timeout = USB_TIMEOUT_MS(pipe);
 479         do {
 480                 /* Invalidate dcache */
 481                 invalidate_dcache_range((uint32_t)qh_list,
 482                         ALIGN_END_ADDR(struct QH, qh_list, 1));
 483                 invalidate_dcache_range((uint32_t)qh,
 484                         ALIGN_END_ADDR(struct QH, qh, 1));
 485                 invalidate_dcache_range((uint32_t)qtd,
 486                         ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
 487
 488                 token = hc32_to_cpu(vtd->qt_token);
 489                 if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
 490                         break;
 491                 WATCHDOG_RESET();
 492         } while (get_timer(ts) < timeout);
 493
 494         /*
 495          * Invalidate the memory area occupied by buffer
 496          * Don't try to fix the buffer alignment, if it isn't properly
 497          * aligned it's upper layer's fault so let invalidate_dcache_range()
 498          * vow about it. But we have to fix the length as it's actual
 499          * transfer length and can be unaligned. This is potentially
 500          * dangerous operation, it's responsibility of the calling
 501          * code to make sure enough space is reserved.
 502          */
 503         invalidate_dcache_range((uint32_t)buffer,
 504                 ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
 505
 506         /* Check that the TD processing happened */
 507         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
 508                 printf("EHCI timed out on TD - token=%#x\n", token);
 509
 510         /* Disable async schedule. */
 511         cmd = ehci_readl(&hcor->or_usbcmd);
 512         cmd &= ~CMD_ASE;
 513         ehci_writel(&hcor->or_usbcmd, cmd);
 514
 515         ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0,
 516                         100 * 1000);
 517         if (ret < 0) {
 518                 printf("EHCI fail timeout STS_ASS reset\n");
 519                 goto fail;
 520         }
 521
 522         token = hc32_to_cpu(qh->qh_overlay.qt_token);
 523         if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
 524                 debug("TOKEN=%#x\n", token);
 525                 switch (QT_TOKEN_GET_STATUS(token) &
 526                         ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
 527                 case 0:
 528                         toggle = QT_TOKEN_GET_DT(token);
 529                         usb_settoggle(dev, usb_pipeendpoint(pipe),
 530                                        usb_pipeout(pipe), toggle);
 531                         dev->status = 0;
 532                         break;
 533                 case QT_TOKEN_STATUS_HALTED:
 534                         dev->status = USB_ST_STALLED;
 535                         break;
 536                 case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
 537                 case QT_TOKEN_STATUS_DATBUFERR:
 538                         dev->status = USB_ST_BUF_ERR;
 539                         break;
 540                 case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
 541                 case QT_TOKEN_STATUS_BABBLEDET:
 542                         dev->status = USB_ST_BABBLE_DET;
 543                         break;
 544                 default:
 545                         dev->status = USB_ST_CRC_ERR;
 546                         if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
 547                                 dev->status |= USB_ST_STALLED;
 548                         break;
 549                 }
 550                 dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
 551         } else {
 552                 dev->act_len = 0;
 553                 debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
 554                       dev->devnum, ehci_readl(&hcor->or_usbsts),
 555                       ehci_readl(&hcor->or_portsc[0]),
 556                       ehci_readl(&hcor->or_portsc[1]));
 557         }
 558
 559         free(qtd);
 560         return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
 561
 562 fail:
 563         free(qtd);
 564         return -1;
 565 }
 566
 567 static inline int min3(int a, int b, int c)
 568 {
 569
 570         if (b < a)
 571                 a = b;
 572         if (c < a)
 573                 a = c;
 574         return a;
 575 }
 576
 577 int
 578 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 579                  int length, struct devrequest *req)
 580 {
 581         uint8_t tmpbuf[4];
 582         u16 typeReq;
 583         void *srcptr = NULL;
 584         int len, srclen;
 585         uint32_t reg;
 586         uint32_t *status_reg;
 587
 588         if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
 589                 printf("The request port(%d) is not configured\n",
 590                         le16_to_cpu(req->index) - 1);
 591                 return -1;
 592         }
 593         status_reg = (uint32_t *)&hcor->or_portsc[
 594                                                 le16_to_cpu(req->index) - 1];
 595         srclen = 0;
 596
 597         debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
 598               req->request, req->request,
 599               req->requesttype, req->requesttype,
 600               le16_to_cpu(req->value), le16_to_cpu(req->index));
 601
 602         typeReq = req->request | req->requesttype << 8;
 603
 604         switch (typeReq) {
 605         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 606                 switch (le16_to_cpu(req->value) >> 8) {
 607                 case USB_DT_DEVICE:
 608                         debug("USB_DT_DEVICE request\n");
 609                         srcptr = &descriptor.device;
 610                         srclen = descriptor.device.bLength;
 611                         break;
 612                 case USB_DT_CONFIG:
 613                         debug("USB_DT_CONFIG config\n");
 614                         srcptr = &descriptor.config;
 615                         srclen = descriptor.config.bLength +
 616                                         descriptor.interface.bLength +
 617                                         descriptor.endpoint.bLength;
 618                         break;
 619                 case USB_DT_STRING:
 620                         debug("USB_DT_STRING config\n");
 621                         switch (le16_to_cpu(req->value) & 0xff) {
 622                         case 0: /* Language */
 623                                 srcptr = "\4\3\1\0";
 624                                 srclen = 4;
 625                                 break;
 626                         case 1: /* Vendor */
 627                                 srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
 628                                 srclen = 14;
 629                                 break;
 630                         case 2: /* Product */
 631                                 srcptr = "\52\3E\0H\0C\0I\0 "
 632                                          "\0H\0o\0s\0t\0 "
 633                                          "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
 634                                 srclen = 42;
 635                                 break;
 636                         default:
 637                                 debug("unknown value DT_STRING %x\n",
 638                                         le16_to_cpu(req->value));
 639                                 goto unknown;
 640                         }
 641                         break;
 642                 default:
 643                         debug("unknown value %x\n", le16_to_cpu(req->value));
 644                         goto unknown;
 645                 }
 646                 break;
 647         case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
 648                 switch (le16_to_cpu(req->value) >> 8) {
 649                 case USB_DT_HUB:
 650                         debug("USB_DT_HUB config\n");
 651                         srcptr = &descriptor.hub;
 652                         srclen = descriptor.hub.bLength;
 653                         break;
 654                 default:
 655                         debug("unknown value %x\n", le16_to_cpu(req->value));
 656                         goto unknown;
 657                 }
 658                 break;
 659         case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
 660                 debug("USB_REQ_SET_ADDRESS\n");
 661                 rootdev = le16_to_cpu(req->value);
 662                 break;
 663         case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
 664                 debug("USB_REQ_SET_CONFIGURATION\n");
 665                 /* Nothing to do */
 666                 break;
 667         case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
 668                 tmpbuf[0] = 1;  /* USB_STATUS_SELFPOWERED */
 669                 tmpbuf[1] = 0;
 670                 srcptr = tmpbuf;
 671                 srclen = 2;
 672                 break;
 673         case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 674                 memset(tmpbuf, 0, 4);
 675                 reg = ehci_readl(status_reg);
 676                 if (reg & EHCI_PS_CS)
 677                         tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
 678                 if (reg & EHCI_PS_PE)
 679                         tmpbuf[0] |= USB_PORT_STAT_ENABLE;
 680                 if (reg & EHCI_PS_SUSP)
 681                         tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
 682                 if (reg & EHCI_PS_OCA)
 683                         tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
 684                 if (reg & EHCI_PS_PR)
 685                         tmpbuf[0] |= USB_PORT_STAT_RESET;
 686                 if (reg & EHCI_PS_PP)
 687                         tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
 688
 689                 if (ehci_is_TDI()) {
 690                         switch (PORTSC_PSPD(reg)) {
 691                         case PORTSC_PSPD_FS:
 692                                 break;
 693                         case PORTSC_PSPD_LS:
 694                                 tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
 695                                 break;
 696                         case PORTSC_PSPD_HS:
 697                         default:
 698                                 tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 699                                 break;
 700                         }
 701                 } else {
 702                         tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 703                 }
 704
 705                 if (reg & EHCI_PS_CSC)
 706                         tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
 707                 if (reg & EHCI_PS_PEC)
 708                         tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
 709                 if (reg & EHCI_PS_OCC)
 710                         tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
 711                 if (portreset & (1 << le16_to_cpu(req->index)))
 712                         tmpbuf[2] |= USB_PORT_STAT_C_RESET;
 713
 714                 srcptr = tmpbuf;
 715                 srclen = 4;
 716                 break;
 717         case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 718                 reg = ehci_readl(status_reg);
 719                 reg &= ~EHCI_PS_CLEAR;
 720                 switch (le16_to_cpu(req->value)) {
 721                 case USB_PORT_FEAT_ENABLE:
 722                         reg |= EHCI_PS_PE;
 723                         ehci_writel(status_reg, reg);
 724                         break;
 725                 case USB_PORT_FEAT_POWER:
 726                         if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
 727                                 reg |= EHCI_PS_PP;
 728                                 ehci_writel(status_reg, reg);
 729                         }
 730                         break;
 731                 case USB_PORT_FEAT_RESET:
 732                         if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
 733                             !ehci_is_TDI() &&
 734                             EHCI_PS_IS_LOWSPEED(reg)) {
 735                                 /* Low speed device, give up ownership. */
 736                                 debug("port %d low speed --> companion\n",
 737                                       req->index - 1);
 738                                 reg |= EHCI_PS_PO;
 739                                 ehci_writel(status_reg, reg);
 740                                 break;
 741                         } else {
 742                                 int ret;
 743
 744                                 reg |= EHCI_PS_PR;
 745                                 reg &= ~EHCI_PS_PE;
 746                                 ehci_writel(status_reg, reg);
 747                                 /*
 748                                  * caller must wait, then call GetPortStatus
 749                                  * usb 2.0 specification say 50 ms resets on
 750                                  * root
 751                                  */
 752                                 ehci_powerup_fixup(status_reg, &reg);
 753
 754                                 ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 755                                 /*
 756                                  * A host controller must terminate the reset
 757                                  * and stabilize the state of the port within
 758                                  * 2 milliseconds
 759                                  */
 760                                 ret = handshake(status_reg, EHCI_PS_PR, 0,
 761                                                 2 * 1000);
 762                                 if (!ret)
 763                                         portreset |=
 764                                                 1 << le16_to_cpu(req->index);
 765                                 else
 766                                         printf("port(%d) reset error\n",
 767                                         le16_to_cpu(req->index) - 1);
 768                         }
 769                         break;
 770                 default:
 771                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 772                         goto unknown;
 773                 }
 774                 /* unblock posted writes */
 775                 (void) ehci_readl(&hcor->or_usbcmd);
 776                 break;
 777         case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
 778                 reg = ehci_readl(status_reg);
 779                 switch (le16_to_cpu(req->value)) {
 780                 case USB_PORT_FEAT_ENABLE:
 781                         reg &= ~EHCI_PS_PE;
 782                         break;
 783                 case USB_PORT_FEAT_C_ENABLE:
 784                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
 785                         break;
 786                 case USB_PORT_FEAT_POWER:
 787                         if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
 788                                 reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
 789                 case USB_PORT_FEAT_C_CONNECTION:
 790                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
 791                         break;
 792                 case USB_PORT_FEAT_OVER_CURRENT:
 793                         reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
 794                         break;
 795                 case USB_PORT_FEAT_C_RESET:
 796                         portreset &= ~(1 << le16_to_cpu(req->index));
 797                         break;
 798                 default:
 799                         debug("unknown feature %x\n", le16_to_cpu(req->value));
 800                         goto unknown;
 801                 }
 802                 ehci_writel(status_reg, reg);
 803                 /* unblock posted write */
 804                 (void) ehci_readl(&hcor->or_usbcmd);
 805                 break;
 806         default:
 807                 debug("Unknown request\n");
 808                 goto unknown;
 809         }
 810
 811         mdelay(1);
 812         len = min3(srclen, le16_to_cpu(req->length), length);
 813         if (srcptr != NULL && len > 0)
 814                 memcpy(buffer, srcptr, len);
 815         else
 816                 debug("Len is 0\n");
 817
 818         dev->act_len = len;
 819         dev->status = 0;
 820         return 0;
 821
 822 unknown:
 823         debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
 824               req->requesttype, req->request, le16_to_cpu(req->value),
 825               le16_to_cpu(req->index), le16_to_cpu(req->length));
 826
 827         dev->act_len = 0;
 828         dev->status = USB_ST_STALLED;
 829         return -1;
 830 }
 831
 832 int usb_lowlevel_stop(void)
 833 {
 834         return ehci_hcd_stop();
 835 }
 836
 837 int usb_lowlevel_init(void)
 838 {
 839         uint32_t reg;
 840         uint32_t cmd;
 841
 842         if (ehci_hcd_init())
 843                 return -1;
 844
 845         /* EHCI spec section 4.1 */
 846         if (ehci_reset())
 847                 return -1;
 848
 849 #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
 850         if (ehci_hcd_init())
 851                 return -1;
 852 #endif
 853
 854         /* Set head of reclaim list */
 855         memset(qh_list, 0, sizeof(*qh_list));
 856         qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
 857         qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
 858                                                 QH_ENDPT1_EPS(USB_SPEED_HIGH));
 859         qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
 860         qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
 861         qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
 862         qh_list->qh_overlay.qt_token =
 863                         cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
 864
 865         reg = ehci_readl(&hccr->cr_hcsparams);
 866         descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
 867         printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
 868         /* Port Indicators */
 869         if (HCS_INDICATOR(reg))
 870                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
 871                                 | 0x80, &descriptor.hub.wHubCharacteristics);
 872         /* Port Power Control */
 873         if (HCS_PPC(reg))
 874                 put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
 875                                 | 0x01, &descriptor.hub.wHubCharacteristics);
 876
 877         /* Start the host controller. */
 878         cmd = ehci_readl(&hcor->or_usbcmd);
 879         /*
 880          * Philips, Intel, and maybe others need CMD_RUN before the
 881          * root hub will detect new devices (why?); NEC doesn't
 882          */
 883         cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 884         cmd |= CMD_RUN;
 885         ehci_writel(&hcor->or_usbcmd, cmd);
 886
 887         /* take control over the ports */
 888         cmd = ehci_readl(&hcor->or_configflag);
 889         cmd |= FLAG_CF;
 890         ehci_writel(&hcor->or_configflag, cmd);
 891         /* unblock posted write */
 892         cmd = ehci_readl(&hcor->or_usbcmd);
 893         mdelay(5);
 894         reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
 895         printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
 896
 897         rootdev = 0;
 898
 899         return 0;
 900 }
 901
 902 int
 903 submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 904                 int length)
 905 {
 906
 907         if (usb_pipetype(pipe) != PIPE_BULK) {
 908                 debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
 909                 return -1;
 910         }
 911         return ehci_submit_async(dev, pipe, buffer, length, NULL);
 912 }
 913
 914 int
 915 submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 916                    int length, struct devrequest *setup)
 917 {
 918
 919         if (usb_pipetype(pipe) != PIPE_CONTROL) {
 920                 debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
 921                 return -1;
 922         }
 923
 924         if (usb_pipedevice(pipe) == rootdev) {
 925                 if (!rootdev)
 926                         dev->speed = USB_SPEED_HIGH;
 927                 return ehci_submit_root(dev, pipe, buffer, length, setup);
 928         }
 929         return ehci_submit_async(dev, pipe, buffer, length, setup);
 930 }
 931
 932 int
 933 submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 934                int length, int interval)
 935 {
 936         debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
 937               dev, pipe, buffer, length, interval);
 938
 939         /*
 940          * Interrupt transfers requiring several transactions are not supported
 941          * because bInterval is ignored.
 942          *
 943          * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
 944          * <= PKT_ALIGN if several qTDs are required, while the USB
 945          * specification does not constrain this for interrupt transfers. That
 946          * means that ehci_submit_async() would support interrupt transfers
 947          * requiring several transactions only as long as the transfer size does
 948          * not require more than a single qTD.
 949          */
 950         if (length > usb_maxpacket(dev, pipe)) {
 951                 printf("%s: Interrupt transfers requiring several transactions "
 952                         "are not supported.\n", __func__);
 953                 return -1;
 954         }
 955         return ehci_submit_async(dev, pipe, buffer, length, NULL);
 956 }