drivers/video/ipu_common.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver
   8  *
   9  * (C) Copyright 2005-2011 Freescale Semiconductor, Inc.
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 /* #define DEBUG */
  15 #include <common.h>
  16 #include <ipu.h>
  17 #include <linux/types.h>
  18 #include <linux/err.h>
  19 #include <asm/io.h>
  20 #include <asm/errno.h>
  21 #include <asm/arch/imx-regs.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <asm/arch/clock.h>
  24
  25 #include "ipu_regs.h"
  26
  27 static struct mxc_ccm_reg __maybe_unused *mxc_ccm = (void *)CCM_BASE_ADDR;
  28
  29 struct ipu_ch_param_word {
  30         uint32_t data[5];
  31         uint32_t res[3];
  32 };
  33
  34 struct ipu_ch_param {
  35         struct ipu_ch_param_word word[2];
  36 };
  37
  38 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
  39
  40 #define _param_word(base, w) \
  41         (((struct ipu_ch_param *)(base))->word[w].data)
  42
  43 #define ipu_ch_param_set_field(base, w, bit, size, v) {                 \
  44         int i = (bit) / 32;                                             \
  45         int off = (bit) % 32;                                           \
  46         _param_word(base, w)[i] |= (v) << off;                          \
  47         if (((bit) + (size) - 1) / 32 > i) {                            \
  48                 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
  49         }                                                               \
  50 }
  51
  52 #define ipu_ch_param_mod_field(base, w, bit, size, v) {         \
  53         int i = (bit) / 32;                                     \
  54         int off = (bit) % 32;                                   \
  55         u32 mask = (1UL << size) - 1;                           \
  56         u32 temp = _param_word(base, w)[i];                     \
  57         temp &= ~(mask << off);                                 \
  58         _param_word(base, w)[i] = temp | (v) << off;            \
  59         if (((bit) + (size) - 1) / 32 > i) {                    \
  60                 temp = _param_word(base, w)[i + 1];             \
  61                 temp &= ~(mask >> (32 - off));                  \
  62                 _param_word(base, w)[i + 1] =                   \
  63                         temp | ((v) >> (off ? (32 - off) : 0)); \
  64         }                                                       \
  65 }
  66
  67 #define ipu_ch_param_read_field(base, w, bit, size) ({          \
  68         u32 temp2;                                              \
  69         int i = (bit) / 32;                                     \
  70         int off = (bit) % 32;                                   \
  71         u32 mask = (1UL << size) - 1;                           \
  72         u32 temp1 = _param_word(base, w)[i];                    \
  73         temp1 = mask & (temp1 >> off);                          \
  74         if (((bit)+(size) - 1) / 32 > i) {                      \
  75                 temp2 = _param_word(base, w)[i + 1];            \
  76                 temp2 &= mask >> (off ? (32 - off) : 0);        \
  77                 temp1 |= temp2 << (off ? (32 - off) : 0);       \
  78         }                                                       \
  79         temp1;                                                  \
  80 })
  81
  82 #define IPU_SW_RST_TOUT_USEC    (10000)
  83
  84 static int clk_ipu_enable(struct clk *clk)
  85 {
  86         ipu_clk_enable();
  87         return 0;
  88 }
  89
  90 static void clk_ipu_disable(struct clk *clk)
  91 {
  92         ipu_clk_disable();
  93 }
  94
  95 static struct clk ipu_clk = {
  96         .name = "ipu_clk",
  97         .rate = CONFIG_IPUV3_CLK,
  98 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
  99         .enable_reg = (u32 *)(CCM_BASE_ADDR +
 100                 offsetof(struct mxc_ccm_reg, CCGR5)),
 101         .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
 102 #else
 103         .enable_reg = (u32 *)(CCM_BASE_ADDR +
 104                 offsetof(struct mxc_ccm_reg, CCGR3)),
 105         .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
 106 #endif
 107         .enable = clk_ipu_enable,
 108         .disable = clk_ipu_disable,
 109 };
 110
 111 static struct clk ldb_clk = {
 112         .name = "ldb_clk",
 113         .rate = 65000000,
 114 };
 115
 116 /* Globals */
 117 struct clk *g_ipu_clk;
 118 struct clk *g_ldb_clk;
 119 struct clk *g_di_clk[2];
 120 struct clk *g_pixel_clk[2];
 121 unsigned char g_dc_di_assignment[10];
 122 int g_ipu_clk_enabled;
 123 u32 *ipu_dc_tmpl_reg;
 124
 125 static uint32_t g_channel_init_mask;
 126 static uint32_t g_channel_enable_mask;
 127 static int ipu_dc_use_count;
 128 static int ipu_dp_use_count;
 129 static int ipu_dmfc_use_count;
 130 static int ipu_di_use_count[2];
 131
 132 static u32 *ipu_cpmem_base;
 133
 134 /* Static functions */
 135
 136 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
 137 {
 138         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
 139 };
 140
 141 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
 142 {
 143         return ((uint32_t) ch >> (6 * type)) & 0x3F;
 144 };
 145
 146 /* Either DP BG or DP FG can be graphic window */
 147 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
 148 {
 149         return (dma_chan == 23 || dma_chan == 27);
 150 }
 151
 152 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
 153 {
 154         return ((dma_chan >= 23) && (dma_chan <= 29));
 155 }
 156
 157
 158 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
 159                                             dma_addr_t phyaddr)
 160 {
 161         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
 162                                phyaddr / 8);
 163 };
 164
 165 #define idma_is_valid(ch)       (ch != NO_DMA)
 166 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 167 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
 168
 169 static void ipu_pixel_clk_recalc(struct clk *clk)
 170 {
 171         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
 172         if (div == 0)
 173                 clk->rate = 0;
 174         else
 175                 clk->rate = (clk->parent->rate * 16) / div;
 176 }
 177
 178 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
 179         unsigned long rate)
 180 {
 181         u32 div, div1;
 182         u64 tmp;
 183         /*
 184          * Calculate divider
 185          * Fractional part is 4 bits,
 186          * so simply multiply by 2^4 to get fractional part.
 187          */
 188         tmp = (u64)clk->parent->rate * 16;
 189         div = tmp / rate;
 190
 191         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 192                 div = 0x10;
 193         if (div & ~0xFEF)
 194                 div &= 0xFF8;
 195         else {
 196                 div1 = div & 0xFE0;
 197                 if ((tmp/div1 - tmp/div) < rate / 4)
 198                         div = div1;
 199                 else
 200                         div &= 0xFF8;
 201         }
 202         tmp /= div;
 203 #if 1
 204         debug("%s: requested rate: %lu.%03luMHz parent_rate: %lu.%03luMHz actual rate: %llu.%03lluMHz div: %u.%u\n", __func__,
 205                 rate / 1000000, rate / 1000 % 1000,
 206                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 207                 tmp / 1000000, tmp / 1000 % 1000, div / 16, div % 16);
 208 #endif
 209         return tmp;
 210 }
 211
 212 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 213 {
 214         u32 div = ((u64)clk->parent->rate * 16) / rate;
 215
 216         debug("%s: parent_rate: %lu.%03luMHz actual rate: %lu.%03luMHz div: %u.%u\n", __func__,
 217                 clk->parent->rate / 1000000, clk->parent->rate / 1000 % 1000,
 218                 rate / 1000000, rate / 1000 % 1000, div / 16, div % 16);
 219
 220         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 221
 222         /* Setup pixel clock timing */
 223         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 224
 225         clk->rate = ((u64)clk->parent->rate * 16) / div;
 226         debug("%s: pix_clk=%lu.%03luMHz\n", __func__,
 227                 clk->rate / 1000000, clk->rate / 1000 % 1000);
 228         return 0;
 229 }
 230
 231 static int ipu_pixel_clk_enable(struct clk *clk)
 232 {
 233         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 234         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 235         __raw_writel(disp_gen, IPU_DISP_GEN);
 236
 237         return 0;
 238 }
 239
 240 static void ipu_pixel_clk_disable(struct clk *clk)
 241 {
 242         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 243         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 244         __raw_writel(disp_gen, IPU_DISP_GEN);
 245 }
 246
 247 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 248 {
 249         int ret;
 250         u32 di_gen;
 251
 252         ret = clk_enable(clk);
 253         if (ret)
 254                 return ret;
 255
 256         di_gen = __raw_readl(DI_GENERAL(clk->id));
 257
 258         if (parent == g_ipu_clk)
 259                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 260         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
 261                 di_gen |= DI_GEN_DI_CLK_EXT;
 262         else
 263                 goto err;
 264
 265         ret = clk_enable(parent);
 266         if (ret)
 267                 goto err;
 268         __raw_writel(di_gen, DI_GENERAL(clk->id));
 269 debug("%s@%d:\n", __func__, __LINE__);
 270         ipu_pixel_clk_recalc(clk);
 271         clk->disable(clk->parent);
 272         clk->parent = parent;
 273 err:
 274         clk_disable(clk);
 275         return ret;
 276 }
 277
 278 static struct clk pixel_clk[] = {
 279         {
 280                 .name = "pixel_clk",
 281                 .id = 0,
 282                 .recalc = ipu_pixel_clk_recalc,
 283                 .set_rate = ipu_pixel_clk_set_rate,
 284                 .round_rate = ipu_pixel_clk_round_rate,
 285                 .set_parent = ipu_pixel_clk_set_parent,
 286                 .enable = ipu_pixel_clk_enable,
 287                 .disable = ipu_pixel_clk_disable,
 288         },
 289         {
 290                 .name = "pixel_clk",
 291                 .id = 1,
 292                 .recalc = ipu_pixel_clk_recalc,
 293                 .set_rate = ipu_pixel_clk_set_rate,
 294                 .round_rate = ipu_pixel_clk_round_rate,
 295                 .set_parent = ipu_pixel_clk_set_parent,
 296                 .enable = ipu_pixel_clk_enable,
 297                 .disable = ipu_pixel_clk_disable,
 298         },
 299 };
 300
 301 static struct clk di_clk[] = {
 302         {
 303                 .name = "ipu_di_clk",
 304                 .id = 0,
 305         },
 306         {
 307                 .name = "ipu_di_clk",
 308                 .id = 1,
 309         },
 310 };
 311
 312 /*
 313  * This function resets IPU
 314  */
 315 void ipu_reset(void)
 316 {
 317         u32 *reg;
 318         u32 value;
 319         int timeout = IPU_SW_RST_TOUT_USEC;
 320
 321         reg = (u32 *)SRC_BASE_ADDR;
 322         value = __raw_readl(reg);
 323         value = value | SW_IPU_RST;
 324         __raw_writel(value, reg);
 325
 326         while (__raw_readl(reg) & SW_IPU_RST) {
 327                 udelay(1);
 328                 if (!(timeout--)) {
 329                         printf("ipu software reset timeout\n");
 330                         break;
 331                 }
 332         };
 333 }
 334
 335 /*
 336  * This function is called by the driver framework to initialize the IPU
 337  * hardware.
 338  *
 339  * @param       dev     The device structure for the IPU passed in by the
 340  *                      driver framework.
 341  *
 342  * @return      Returns 0 on success or negative error code on error
 343  */
 344 int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
 345 {
 346         int ret;
 347         void *ipu_base;
 348         unsigned long start;
 349 #if defined CONFIG_MX51
 350         u32 temp;
 351         u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
 352         u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
 353
 354          __raw_writel(0xF00, reg_hsc_mcd);
 355
 356         /* CSI mode reserved */
 357         temp = __raw_readl(reg_hsc_mxt_conf);
 358          __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
 359
 360         temp = __raw_readl(reg_hsc_mxt_conf);
 361         __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
 362 #endif
 363         ipu_base = (void *)IPU_SOC_BASE_ADDR;
 364         /* base fixup */
 365         if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3H) /* IPUv3H */
 366                 ipu_base += IPUV3H_REG_BASE;
 367         else if (gd->arch.ipu_hw_rev == IPUV3_HW_REV_IPUV3M)    /* IPUv3M */
 368                 ipu_base += IPUV3M_REG_BASE;
 369         else                    /* IPUv3D, v3E, v3EX */
 370                 ipu_base += IPUV3DEX_REG_BASE;
 371         ipu_cpmem_base = ipu_base + IPU_CPMEM_REG_BASE;
 372         ipu_dc_tmpl_reg = ipu_base + IPU_DC_TMPL_REG_BASE;
 373
 374         printf("IPU HW Rev: %d\n", gd->arch.ipu_hw_rev);
 375
 376         g_pixel_clk[0] = &pixel_clk[0];
 377         g_pixel_clk[1] = &pixel_clk[1];
 378
 379         g_di_clk[0] = &di_clk[0];
 380         g_di_clk[1] = &di_clk[1];
 381         g_di_clk[di]->rate = di_clk_val;
 382
 383         g_ipu_clk = &ipu_clk;
 384         debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
 385
 386         g_ldb_clk = &ldb_clk;
 387         debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
 388
 389         ret = clk_enable(g_ipu_clk);
 390         if (ret)
 391                 return ret;
 392         ipu_reset();
 393
 394         if (di_clk_parent == DI_PCLK_LDB) {
 395                 clk_set_parent(g_pixel_clk[di], g_ldb_clk);
 396         } else {
 397                 clk_set_parent(g_pixel_clk[0], g_ipu_clk);
 398                 clk_set_parent(g_pixel_clk[1], g_ipu_clk);
 399         }
 400
 401         __raw_writel(0x807FFFFF, IPU_MEM_RST);
 402         start = get_timer_masked();
 403         while (__raw_readl(IPU_MEM_RST) & 0x80000000) {
 404                 if (get_timer(start) > CONFIG_SYS_HZ)
 405                         return -ETIME;
 406         }
 407
 408         ipu_init_dc_mappings();
 409
 410         __raw_writel(0, IPU_INT_CTRL(5));
 411         __raw_writel(0, IPU_INT_CTRL(6));
 412         __raw_writel(0, IPU_INT_CTRL(9));
 413         __raw_writel(0, IPU_INT_CTRL(10));
 414
 415         /* DMFC Init */
 416         ipu_dmfc_init(DMFC_NORMAL, 1);
 417
 418         /* Set sync refresh channels as high priority */
 419         __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
 420
 421         /* Set MCU_T to divide MCU access window into 2 */
 422         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 423
 424         clk_disable(g_ipu_clk);
 425
 426         return 0;
 427 }
 428
 429 void ipu_dump_registers(void)
 430 {
 431         debug("IPU_CONF             0x%08X\n", __raw_readl(IPU_CONF));
 432         debug("IDMAC_CONF           0x%08X\n", __raw_readl(IDMAC_CONF));
 433         debug("IDMAC_CHA_EN1        0x%08X\n",
 434                __raw_readl(IDMAC_CHA_EN(0)));
 435         debug("IDMAC_CHA_EN2        0x%08X\n",
 436                __raw_readl(IDMAC_CHA_EN(32)));
 437         debug("IDMAC_CHA_PRI1       0x%08X\n",
 438                __raw_readl(IDMAC_CHA_PRI(0)));
 439         debug("IDMAC_CHA_PRI2       0x%08X\n",
 440                __raw_readl(IDMAC_CHA_PRI(32)));
 441         debug("IPU_CHA_DB_MODE_SEL0 0x%08X\n",
 442                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
 443         debug("IPU_CHA_DB_MODE_SEL1 0x%08X\n",
 444                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
 445         debug("DMFC_WR_CHAN         0x%08X\n",
 446                __raw_readl(DMFC_WR_CHAN));
 447         debug("DMFC_WR_CHAN_DEF     0x%08X\n",
 448                __raw_readl(DMFC_WR_CHAN_DEF));
 449         debug("DMFC_DP_CHAN         0x%08X\n",
 450                __raw_readl(DMFC_DP_CHAN));
 451         debug("DMFC_DP_CHAN_DEF     0x%08X\n",
 452                __raw_readl(DMFC_DP_CHAN_DEF));
 453         debug("DMFC_IC_CTRL         0x%08X\n",
 454                __raw_readl(DMFC_IC_CTRL));
 455         debug("IPU_FS_PROC_FLOW1    0x%08X\n",
 456                __raw_readl(IPU_FS_PROC_FLOW1));
 457         debug("IPU_FS_PROC_FLOW2    0x%08X\n",
 458                __raw_readl(IPU_FS_PROC_FLOW2));
 459         debug("IPU_FS_PROC_FLOW3    0x%08X\n",
 460                __raw_readl(IPU_FS_PROC_FLOW3));
 461         debug("IPU_FS_DISP_FLOW1    0x%08X\n",
 462                __raw_readl(IPU_FS_DISP_FLOW1));
 463 }
 464
 465 /*
 466  * This function is called to initialize a logical IPU channel.
 467  *
 468  * @param       channel Input parameter for the logical channel ID to init.
 469  *
 470  * @param       params  Input parameter containing union of channel
 471  *                      initialization parameters.
 472  *
 473  * @return      Returns 0 on success or negative error code on fail
 474  */
 475 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 476 {
 477         int ret = 0;
 478         uint32_t ipu_conf;
 479
 480         debug("init channel = %d\n", IPU_CHAN_ID(channel));
 481
 482         if (g_ipu_clk_enabled == 0) {
 483                 g_ipu_clk_enabled = 1;
 484                 clk_enable(g_ipu_clk);
 485         }
 486
 487
 488         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 489                 printf("Warning: channel already initialized %d\n",
 490                         IPU_CHAN_ID(channel));
 491         }
 492
 493         ipu_conf = __raw_readl(IPU_CONF);
 494
 495         switch (channel) {
 496         case MEM_DC_SYNC:
 497                 if (params->mem_dc_sync.di > 1) {
 498                         ret = -EINVAL;
 499                         goto err;
 500                 }
 501
 502                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
 503                 ipu_dc_init(1, params->mem_dc_sync.di,
 504                              params->mem_dc_sync.interlaced);
 505                 ipu_di_use_count[params->mem_dc_sync.di]++;
 506                 ipu_dc_use_count++;
 507                 ipu_dmfc_use_count++;
 508                 break;
 509         case MEM_BG_SYNC:
 510                 if (params->mem_dp_bg_sync.di > 1) {
 511                         ret = -EINVAL;
 512                         goto err;
 513                 }
 514
 515                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 516                 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 517                              params->mem_dp_bg_sync.out_pixel_fmt);
 518                 ipu_dc_init(5, params->mem_dp_bg_sync.di,
 519                              params->mem_dp_bg_sync.interlaced);
 520                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 521                 ipu_dc_use_count++;
 522                 ipu_dp_use_count++;
 523                 ipu_dmfc_use_count++;
 524                 break;
 525         case MEM_FG_SYNC:
 526                 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
 527                              params->mem_dp_fg_sync.out_pixel_fmt);
 528
 529                 ipu_dc_use_count++;
 530                 ipu_dp_use_count++;
 531                 ipu_dmfc_use_count++;
 532                 break;
 533         default:
 534                 printf("Missing channel initialization\n");
 535         }
 536
 537         /* Enable IPU sub module */
 538         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 539         if (ipu_dc_use_count == 1)
 540                 ipu_conf |= IPU_CONF_DC_EN;
 541         if (ipu_dp_use_count == 1)
 542                 ipu_conf |= IPU_CONF_DP_EN;
 543         if (ipu_dmfc_use_count == 1)
 544                 ipu_conf |= IPU_CONF_DMFC_EN;
 545         if (ipu_di_use_count[0] == 1) {
 546                 ipu_conf |= IPU_CONF_DI0_EN;
 547         }
 548         if (ipu_di_use_count[1] == 1) {
 549                 ipu_conf |= IPU_CONF_DI1_EN;
 550         }
 551
 552         __raw_writel(ipu_conf, IPU_CONF);
 553
 554 err:
 555         return ret;
 556 }
 557
 558 /*
 559  * This function is called to uninitialize a logical IPU channel.
 560  *
 561  * @param       channel Input parameter for the logical channel ID to uninit.
 562  */
 563 void ipu_uninit_channel(ipu_channel_t channel)
 564 {
 565         uint32_t reg;
 566         uint32_t in_dma, out_dma = 0;
 567         uint32_t ipu_conf;
 568
 569         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 570                 debug("Channel already uninitialized %d\n",
 571                         IPU_CHAN_ID(channel));
 572                 return;
 573         }
 574
 575         /*
 576          * Make sure channel is disabled
 577          * Get input and output dma channels
 578          */
 579         in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 580         out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 581
 582         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 583             idma_is_set(IDMAC_CHA_EN, out_dma)) {
 584                 printf("Channel %d is not disabled, disable first\n",
 585                         IPU_CHAN_ID(channel));
 586                 return;
 587         }
 588
 589         ipu_conf = __raw_readl(IPU_CONF);
 590
 591         /* Reset the double buffer */
 592         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
 593         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 594         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 595         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 596
 597         switch (channel) {
 598         case MEM_DC_SYNC:
 599                 ipu_dc_uninit(1);
 600                 ipu_di_use_count[g_dc_di_assignment[1]]--;
 601                 ipu_dc_use_count--;
 602                 ipu_dmfc_use_count--;
 603                 break;
 604         case MEM_BG_SYNC:
 605                 ipu_dp_uninit(channel);
 606                 ipu_dc_uninit(5);
 607                 ipu_di_use_count[g_dc_di_assignment[5]]--;
 608                 ipu_dc_use_count--;
 609                 ipu_dp_use_count--;
 610                 ipu_dmfc_use_count--;
 611                 break;
 612         case MEM_FG_SYNC:
 613                 ipu_dp_uninit(channel);
 614                 ipu_dc_use_count--;
 615                 ipu_dp_use_count--;
 616                 ipu_dmfc_use_count--;
 617                 break;
 618         default:
 619                 break;
 620         }
 621
 622         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
 623
 624         if (ipu_dc_use_count == 0)
 625                 ipu_conf &= ~IPU_CONF_DC_EN;
 626         if (ipu_dp_use_count == 0)
 627                 ipu_conf &= ~IPU_CONF_DP_EN;
 628         if (ipu_dmfc_use_count == 0)
 629                 ipu_conf &= ~IPU_CONF_DMFC_EN;
 630         if (ipu_di_use_count[0] == 0) {
 631                 ipu_conf &= ~IPU_CONF_DI0_EN;
 632         }
 633         if (ipu_di_use_count[1] == 0) {
 634                 ipu_conf &= ~IPU_CONF_DI1_EN;
 635         }
 636
 637         __raw_writel(ipu_conf, IPU_CONF);
 638
 639         /* clear interrupt status */
 640         __raw_writel(__raw_readl(IPU_STAT), IPU_STAT);
 641
 642         if (ipu_conf == 0) {
 643                 clk_disable(g_ipu_clk);
 644                 g_ipu_clk_enabled = 0;
 645         }
 646 }
 647
 648 static inline void ipu_ch_param_dump(int ch)
 649 {
 650 #ifdef DEBUG
 651         struct ipu_ch_param *p = ipu_ch_param_addr(ch);
 652         debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
 653                  p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
 654                  p->word[0].data[3], p->word[0].data[4]);
 655         debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
 656                  p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
 657                  p->word[1].data[3], p->word[1].data[4]);
 658         debug("PFS 0x%x, ",
 659                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
 660         debug("BPP 0x%x, ",
 661                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
 662         debug("NPB 0x%x\n",
 663                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
 664
 665         debug("FW %d, ",
 666                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
 667         debug("FH %d, ",
 668                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
 669         debug("Stride %d\n",
 670                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
 671
 672         debug("Width0 %d+1, ",
 673                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
 674         debug("Width1 %d+1, ",
 675                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
 676         debug("Width2 %d+1, ",
 677                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
 678         debug("Width3 %d+1, ",
 679                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
 680         debug("Offset0 %d, ",
 681                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
 682         debug("Offset1 %d, ",
 683                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
 684         debug("Offset2 %d, ",
 685                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
 686         debug("Offset3 %d\n",
 687                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
 688 #endif
 689 }
 690
 691 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
 692                                               int red_width, int red_offset,
 693                                               int green_width, int green_offset,
 694                                               int blue_width, int blue_offset,
 695                                               int alpha_width, int alpha_offset)
 696 {
 697         /* Setup red width and offset */
 698         ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
 699         ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
 700         /* Setup green width and offset */
 701         ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
 702         ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
 703         /* Setup blue width and offset */
 704         ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
 705         ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
 706         /* Setup alpha width and offset */
 707         ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
 708         ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
 709 }
 710
 711 static void ipu_ch_param_init(int ch,
 712                               uint32_t pixel_fmt, uint32_t width,
 713                               uint32_t height, uint32_t stride,
 714                               uint32_t u, uint32_t v,
 715                               uint32_t uv_stride, dma_addr_t addr0,
 716                               dma_addr_t addr1)
 717 {
 718         uint32_t u_offset = 0;
 719         uint32_t v_offset = 0;
 720
 721         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 125, 13, width - 1);
 722
 723         if ((ch == 8) || (ch == 9) || (ch == 10)) {
 724                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, (height / 2) - 1);
 725                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, (stride * 2) - 1);
 726         } else {
 727                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 138, 12, height - 1);
 728                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 102, 14, stride - 1);
 729         }
 730
 731         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 0, 29, addr0 >> 3);
 732         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 29, 29, addr1 >> 3);
 733
 734         switch (pixel_fmt) {
 735         case IPU_PIX_FMT_GENERIC:
 736                 /*Represents 8-bit Generic data */
 737                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 5);    /* bits/pixel */
 738                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 6);     /* pix format */
 739                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 63);    /* burst size */
 740
 741                 break;
 742         case IPU_PIX_FMT_GENERIC_32:
 743                 /*Represents 32-bit Generic data */
 744                 break;
 745         case IPU_PIX_FMT_RGB565:
 746                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 747                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 748                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 749
 750                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 5, 0, 6, 5, 5, 11, 8, 16);
 751                 break;
 752         case IPU_PIX_FMT_BGR24:
 753                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 754                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 755                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 756
 757                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 758                 break;
 759         case IPU_PIX_FMT_RGB24:
 760         case IPU_PIX_FMT_YUV444:
 761                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 1);    /* bits/pixel */
 762                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 763                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 19);    /* burst size */
 764
 765                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 16, 8, 8, 8, 0, 8, 24);
 766                 break;
 767         case IPU_PIX_FMT_BGRA32:
 768         case IPU_PIX_FMT_BGR32:
 769                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 770                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 771                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 772
 773                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 8, 8, 16, 8, 24, 8, 0);
 774                 break;
 775         case IPU_PIX_FMT_RGBA32:
 776         case IPU_PIX_FMT_RGB32:
 777                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 778                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 779                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 780
 781                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 24, 8, 16, 8, 8, 8, 0);
 782                 break;
 783         case IPU_PIX_FMT_ABGR32:
 784                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 0);    /* bits/pixel */
 785                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 7);     /* pix format */
 786
 787                 ipu_ch_params_set_packing(ipu_ch_param_addr(ch), 8, 0, 8, 8, 8, 16, 8, 24);
 788                 break;
 789         case IPU_PIX_FMT_UYVY:
 790                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 791                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0xA);   /* pix format */
 792                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);    /* burst size */
 793                 break;
 794         case IPU_PIX_FMT_YUYV:
 795                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 107, 3, 3);    /* bits/pixel */
 796                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 0x8);   /* pix format */
 797                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 798                 break;
 799         case IPU_PIX_FMT_YUV420P2:
 800         case IPU_PIX_FMT_YUV420P:
 801                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 2);     /* pix format */
 802
 803                 if (uv_stride < stride / 2)
 804                         uv_stride = stride / 2;
 805
 806                 u_offset = stride * height;
 807                 v_offset = u_offset + (uv_stride * height / 2);
 808                 /* burst size */
 809                 if ((ch == 8) || (ch == 9) || (ch == 10)) {
 810                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 15);
 811                         uv_stride = uv_stride*2;
 812                 } else {
 813                         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);
 814                 }
 815                 break;
 816         case IPU_PIX_FMT_YVU422P:
 817                 /* BPP & pixel format */
 818                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 819                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 820
 821                 if (uv_stride < stride / 2)
 822                         uv_stride = stride / 2;
 823
 824                 v_offset = (v == 0) ? stride * height : v;
 825                 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
 826                 break;
 827         case IPU_PIX_FMT_YUV422P:
 828                 /* BPP & pixel format */
 829                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 1);     /* pix format */
 830                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 831
 832                 if (uv_stride < stride / 2)
 833                         uv_stride = stride / 2;
 834
 835                 u_offset = (u == 0) ? stride * height : u;
 836                 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
 837                 break;
 838         case IPU_PIX_FMT_NV12:
 839                 /* BPP & pixel format */
 840                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 85, 4, 4);     /* pix format */
 841                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 78, 7, 31);    /* burst size */
 842                 uv_stride = stride;
 843                 u_offset = (u == 0) ? stride * height : u;
 844                 break;
 845         default:
 846                 printf("mxc ipu: unimplemented pixel format: %08x\n",
 847                         pixel_fmt);
 848         }
 849
 850
 851         if (uv_stride)
 852                 ipu_ch_param_set_field(ipu_ch_param_addr(ch), 1, 128, 14, uv_stride - 1);
 853
 854         /* Get the uv offset from user when need cropping */
 855         if (u || v) {
 856                 u_offset = u;
 857                 v_offset = v;
 858         }
 859
 860         /* UBO and VBO are 22-bit */
 861         if (u_offset/8 > 0x3fffff)
 862                 puts("The value of U offset exceeds IPU limitation\n");
 863         if (v_offset/8 > 0x3fffff)
 864                 puts("The value of V offset exceeds IPU limitation\n");
 865
 866         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 46, 22, u_offset / 8);
 867         ipu_ch_param_set_field(ipu_ch_param_addr(ch), 0, 68, 22, v_offset / 8);
 868
 869         debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
 870 };
 871
 872 /*
 873  * This function is called to initialize a buffer for logical IPU channel.
 874  *
 875  * @param       channel         Input parameter for the logical channel ID.
 876  *
 877  * @param       type            Input parameter which buffer to initialize.
 878  *
 879  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 880  *                              Pixel format is a FOURCC ASCII code.
 881  *
 882  * @param       width           Input parameter for width of buffer in pixels.
 883  *
 884  * @param       height          Input parameter for height of buffer in pixels.
 885  *
 886  * @param       stride          Input parameter for stride length of buffer
 887  *                              in pixels.
 888  *
 889  * @param       phyaddr_0       Input parameter buffer 0 physical address.
 890  *
 891  * @param       phyaddr_1       Input parameter buffer 1 physical address.
 892  *                              Setting this to a value other than NULL enables
 893  *                              double buffering mode.
 894  *
 895  * @param       u               private u offset for additional cropping,
 896  *                              zero if not used.
 897  *
 898  * @param       v               private v offset for additional cropping,
 899  *                              zero if not used.
 900  *
 901  * @return      Returns 0 on success or negative error code on fail
 902  */
 903 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 904                                 uint32_t pixel_fmt,
 905                                 uint16_t width, uint16_t height,
 906                                 uint32_t stride,
 907                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 908                                 uint32_t u, uint32_t v)
 909 {
 910         uint32_t reg;
 911         uint32_t dma_chan;
 912
 913         dma_chan = channel_2_dma(channel, type);
 914         if (!idma_is_valid(dma_chan))
 915                 return -EINVAL;
 916
 917         if (stride < width * bytes_per_pixel(pixel_fmt))
 918                 stride = width * bytes_per_pixel(pixel_fmt);
 919
 920         if (stride % 4) {
 921                 printf("Stride %d not 32-bit aligned\n", stride);
 922                 return -EINVAL;
 923         }
 924         /* Build parameter memory data for DMA channel */
 925         ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
 926                            phyaddr_0, phyaddr_1);
 927
 928         if (ipu_is_dmfc_chan(dma_chan)) {
 929                 ipu_dmfc_set_wait4eot(dma_chan, width);
 930         }
 931
 932         if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
 933                 ipu_ch_param_set_high_priority(dma_chan);
 934
 935         ipu_ch_param_dump(dma_chan);
 936
 937         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
 938         if (phyaddr_1)
 939                 reg |= idma_mask(dma_chan);
 940         else
 941                 reg &= ~idma_mask(dma_chan);
 942         __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
 943
 944         /* Reset to buffer 0 */
 945         __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
 946
 947         return 0;
 948 }
 949
 950 /*
 951  * This function enables a logical channel.
 952  *
 953  * @param       channel         Input parameter for the logical channel ID.
 954  *
 955  * @return      This function returns 0 on success or negative error code on
 956  *              fail.
 957  */
 958 int32_t ipu_enable_channel(ipu_channel_t channel)
 959 {
 960         uint32_t reg;
 961         uint32_t in_dma;
 962         uint32_t out_dma;
 963
 964         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
 965                 printf("Warning: channel already enabled %d\n",
 966                         IPU_CHAN_ID(channel));
 967         }
 968
 969         /* Get input and output dma channels */
 970         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 971         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 972
 973         if (idma_is_valid(in_dma)) {
 974                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
 975                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
 976         }
 977         if (idma_is_valid(out_dma)) {
 978                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
 979                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
 980         }
 981
 982         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
 983             (channel == MEM_FG_SYNC)) {
 984                 reg = __raw_readl(IDMAC_WM_EN(in_dma));
 985                 __raw_writel(reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
 986
 987                 ipu_dp_dc_enable(channel);
 988         }
 989
 990         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
 991
 992         return 0;
 993 }
 994
 995 /*
 996  * This function clear buffer ready for a logical channel.
 997  *
 998  * @param       channel         Input parameter for the logical channel ID.
 999  *
1000  * @param       type            Input parameter which buffer to clear.
1001  *
1002  * @param       bufNum          Input parameter for which buffer number clear
1003  *                              ready state.
1004  *
1005  */
1006 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1007                 uint32_t bufNum)
1008 {
1009         uint32_t dma_ch = channel_2_dma(channel, type);
1010
1011         if (!idma_is_valid(dma_ch))
1012                 return;
1013
1014         __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1015         if (bufNum == 0) {
1016                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1017                         __raw_writel(idma_mask(dma_ch),
1018                                         IPU_CHA_BUF0_RDY(dma_ch));
1019                 }
1020         } else {
1021                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1022                         __raw_writel(idma_mask(dma_ch),
1023                                         IPU_CHA_BUF1_RDY(dma_ch));
1024                 }
1025         }
1026         __raw_writel(0x0, IPU_GPR); /* write one to set */
1027 }
1028
1029 /*
1030  * This function disables a logical channel.
1031  *
1032  * @param       channel         Input parameter for the logical channel ID.
1033  *
1034  * @param       wait_for_stop   Flag to set whether to wait for channel end
1035  *                              of frame or return immediately.
1036  *
1037  * @return      This function returns 0 on success or negative error code on
1038  *              fail.
1039  */
1040 int32_t ipu_disable_channel(ipu_channel_t channel)
1041 {
1042         uint32_t reg;
1043         uint32_t in_dma;
1044         uint32_t out_dma;
1045
1046         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1047                 debug("Channel already disabled %d\n",
1048                         IPU_CHAN_ID(channel));
1049                 return 0;
1050         }
1051
1052         /* Get input and output dma channels */
1053         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1054         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1055
1056         if ((idma_is_valid(in_dma) &&
1057                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1058                 && (idma_is_valid(out_dma) &&
1059                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1060                 return -EINVAL;
1061
1062         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1063             (channel == MEM_DC_SYNC)) {
1064                 ipu_dp_dc_disable(channel, 0);
1065         }
1066
1067         /* Disable DMA channel(s) */
1068         if (idma_is_valid(in_dma)) {
1069                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1070                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1071                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1072         }
1073         if (idma_is_valid(out_dma)) {
1074                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1075                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1076                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1077         }
1078
1079         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1080
1081         /* Set channel buffers NOT to be ready */
1082         if (idma_is_valid(in_dma)) {
1083                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1084                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1085         }
1086         if (idma_is_valid(out_dma)) {
1087                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1088                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1089         }
1090
1091         return 0;
1092 }
1093
1094 uint32_t bytes_per_pixel(uint32_t fmt)
1095 {
1096         switch (fmt) {
1097         case IPU_PIX_FMT_GENERIC:       /* generic data */
1098         case IPU_PIX_FMT_RGB332:
1099         case IPU_PIX_FMT_YUV420P:
1100         case IPU_PIX_FMT_YUV422P:
1101                 return 1;
1102         case IPU_PIX_FMT_RGB565:
1103         case IPU_PIX_FMT_YUYV:
1104         case IPU_PIX_FMT_UYVY:
1105                 return 2;
1106         case IPU_PIX_FMT_BGR24:
1107         case IPU_PIX_FMT_RGB24:
1108                 return 3;
1109         case IPU_PIX_FMT_GENERIC_32:    /* generic data */
1110         case IPU_PIX_FMT_BGR32:
1111         case IPU_PIX_FMT_BGRA32:
1112         case IPU_PIX_FMT_RGB32:
1113         case IPU_PIX_FMT_RGBA32:
1114         case IPU_PIX_FMT_ABGR32:
1115                 return 4;
1116         default:
1117                 return 1;
1118         }
1119         return 0;
1120 }
1121
1122 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1123 {
1124         switch (fmt) {
1125         case IPU_PIX_FMT_RGB666:
1126         case IPU_PIX_FMT_RGB565:
1127         case IPU_PIX_FMT_BGR24:
1128         case IPU_PIX_FMT_RGB24:
1129         case IPU_PIX_FMT_BGR32:
1130         case IPU_PIX_FMT_BGRA32:
1131         case IPU_PIX_FMT_RGB32:
1132         case IPU_PIX_FMT_RGBA32:
1133         case IPU_PIX_FMT_ABGR32:
1134         case IPU_PIX_FMT_LVDS666:
1135         case IPU_PIX_FMT_LVDS888:
1136                 return RGB;
1137
1138         default:
1139                 return YCbCr;
1140         }
1141         return RGB;
1142 }