drivers/video/ipu_common.c

   1 /*
   2  * Porting to u-boot:
   3  *
   4  * (C) Copyright 2010
   5  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   6  *
   7  * Linux IPU driver for MX51:
   8  *
   9  * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 /* #define DEBUG */
  31 #include <common.h>
  32 #include <linux/types.h>
  33 #include <linux/err.h>
  34 #include <asm/io.h>
  35 #include <asm/errno.h>
  36 #include <asm/arch/imx-regs.h>
  37 #include <asm/arch/crm_regs.h>
  38 #include "ipu.h"
  39 #include "ipu_regs.h"
  40
  41 extern struct mxc_ccm_reg *mxc_ccm;
  42 extern u32 *ipu_cpmem_base;
  43
  44 struct ipu_ch_param_word {
  45         uint32_t data[5];
  46         uint32_t res[3];
  47 };
  48
  49 struct ipu_ch_param {
  50         struct ipu_ch_param_word word[2];
  51 };
  52
  53 #define ipu_ch_param_addr(ch) (((struct ipu_ch_param *)ipu_cpmem_base) + (ch))
  54
  55 #define _param_word(base, w) \
  56         (((struct ipu_ch_param *)(base))->word[(w)].data)
  57
  58 #define ipu_ch_param_set_field(base, w, bit, size, v) { \
  59         int i = (bit) / 32; \
  60         int off = (bit) % 32; \
  61         _param_word(base, w)[i] |= (v) << off; \
  62         if (((bit) + (size) - 1) / 32 > i) { \
  63                 _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
  64         } \
  65 }
  66
  67 #define ipu_ch_param_mod_field(base, w, bit, size, v) { \
  68         int i = (bit) / 32; \
  69         int off = (bit) % 32; \
  70         u32 mask = (1UL << size) - 1; \
  71         u32 temp = _param_word(base, w)[i]; \
  72         temp &= ~(mask << off); \
  73         _param_word(base, w)[i] = temp | (v) << off; \
  74         if (((bit) + (size) - 1) / 32 > i) { \
  75                 temp = _param_word(base, w)[i + 1]; \
  76                 temp &= ~(mask >> (32 - off)); \
  77                 _param_word(base, w)[i + 1] = \
  78                         temp | ((v) >> (off ? (32 - off) : 0)); \
  79         } \
  80 }
  81
  82 #define ipu_ch_param_read_field(base, w, bit, size) ({ \
  83         u32 temp2; \
  84         int i = (bit) / 32; \
  85         int off = (bit) % 32; \
  86         u32 mask = (1UL << size) - 1; \
  87         u32 temp1 = _param_word(base, w)[i]; \
  88         temp1 = mask & (temp1 >> off); \
  89         if (((bit)+(size) - 1) / 32 > i) { \
  90                 temp2 = _param_word(base, w)[i + 1]; \
  91                 temp2 &= mask >> (off ? (32 - off) : 0); \
  92                 temp1 |= temp2 << (off ? (32 - off) : 0); \
  93         } \
  94         temp1; \
  95 })
  96
  97
  98 void clk_enable(struct clk *clk)
  99 {
 100         if (clk) {
 101                 if (clk->usecount++ == 0) {
 102                         clk->enable(clk);
 103                 }
 104         }
 105 }
 106
 107 void clk_disable(struct clk *clk)
 108 {
 109         if (clk) {
 110                 if (!(--clk->usecount)) {
 111                         if (clk->disable)
 112                                 clk->disable(clk);
 113                 }
 114         }
 115 }
 116
 117 int clk_get_usecount(struct clk *clk)
 118 {
 119         if (clk == NULL)
 120                 return 0;
 121
 122         return clk->usecount;
 123 }
 124
 125 u32 clk_get_rate(struct clk *clk)
 126 {
 127         if (!clk)
 128                 return 0;
 129
 130         return clk->rate;
 131 }
 132
 133 struct clk *clk_get_parent(struct clk *clk)
 134 {
 135         if (!clk)
 136                 return 0;
 137
 138         return clk->parent;
 139 }
 140
 141 int clk_set_rate(struct clk *clk, unsigned long rate)
 142 {
 143         if (clk && clk->set_rate)
 144                 clk->set_rate(clk, rate);
 145         return clk->rate;
 146 }
 147
 148 long clk_round_rate(struct clk *clk, unsigned long rate)
 149 {
 150         if (clk == NULL || !clk->round_rate)
 151                 return 0;
 152
 153         return clk->round_rate(clk, rate);
 154 }
 155
 156 int clk_set_parent(struct clk *clk, struct clk *parent)
 157 {
 158         clk->parent = parent;
 159         if (clk->set_parent)
 160                 return clk->set_parent(clk, parent);
 161         return 0;
 162 }
 163
 164 static int clk_ipu_enable(struct clk *clk)
 165 {
 166 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 167         u32 reg;
 168
 169         reg = __raw_readl(clk->enable_reg);
 170         reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
 171         __raw_writel(reg, clk->enable_reg);
 172
 173         /* Handshake with IPU when certain clock rates are changed. */
 174         reg = __raw_readl(&mxc_ccm->ccdr);
 175         reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
 176         __raw_writel(reg, &mxc_ccm->ccdr);
 177
 178         /* Handshake with IPU when LPM is entered as its enabled. */
 179         reg = __raw_readl(&mxc_ccm->clpcr);
 180         reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
 181         __raw_writel(reg, &mxc_ccm->clpcr);
 182 #endif
 183         return 0;
 184 }
 185
 186 static void clk_ipu_disable(struct clk *clk)
 187 {
 188 #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 189         u32 reg;
 190
 191         reg = __raw_readl(clk->enable_reg);
 192         reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
 193         __raw_writel(reg, clk->enable_reg);
 194
 195         /*
 196          * No handshake with IPU whe dividers are changed
 197          * as its not enabled.
 198          */
 199         reg = __raw_readl(&mxc_ccm->ccdr);
 200         reg |= MXC_CCM_CCDR_IPU_HS_MASK;
 201         __raw_writel(reg, &mxc_ccm->ccdr);
 202
 203         /* No handshake with IPU when LPM is entered as its not enabled. */
 204         reg = __raw_readl(&mxc_ccm->clpcr);
 205         reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
 206         __raw_writel(reg, &mxc_ccm->clpcr);
 207 #endif
 208 }
 209
 210
 211 static struct clk ipu_clk = {
 212         .name = "ipu_clk",
 213         .rate = CONFIG_IPUV3_CLK,
 214         .enable_reg = (u32 *)(CCM_BASE_ADDR +
 215                 offsetof(struct mxc_ccm_reg, CCGR5)),
 216         .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
 217         .enable = clk_ipu_enable,
 218         .disable = clk_ipu_disable,
 219         .usecount = 0,
 220 };
 221
 222 /* Globals */
 223 struct clk *g_ipu_clk;
 224 unsigned char g_ipu_clk_enabled;
 225 struct clk *g_di_clk[2];
 226 struct clk *g_pixel_clk[2];
 227 unsigned char g_dc_di_assignment[10];
 228 uint32_t g_channel_init_mask;
 229 uint32_t g_channel_enable_mask;
 230
 231 static int ipu_dc_use_count;
 232 static int ipu_dp_use_count;
 233 static int ipu_dmfc_use_count;
 234 static int ipu_di_use_count[2];
 235
 236 u32 *ipu_cpmem_base;
 237 u32 *ipu_dc_tmpl_reg;
 238
 239 /* Static functions */
 240
 241 static inline void ipu_ch_param_set_high_priority(uint32_t ch)
 242 {
 243         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
 244 };
 245
 246 static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
 247 {
 248         return ((uint32_t) ch >> (6 * type)) & 0x3F;
 249 };
 250
 251 /* Either DP BG or DP FG can be graphic window */
 252 static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
 253 {
 254         return (dma_chan == 23 || dma_chan == 27);
 255 }
 256
 257 static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
 258 {
 259         return ((dma_chan >= 23) && (dma_chan <= 29));
 260 }
 261
 262
 263 static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
 264                                             dma_addr_t phyaddr)
 265 {
 266         ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
 267                                phyaddr / 8);
 268 };
 269
 270 #define idma_is_valid(ch)       (ch != NO_DMA)
 271 #define idma_mask(ch)           (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
 272 #define idma_is_set(reg, dma)   (__raw_readl(reg(dma)) & idma_mask(dma))
 273
 274 static void ipu_pixel_clk_recalc(struct clk *clk)
 275 {
 276         u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
 277         if (div == 0)
 278                 clk->rate = 0;
 279         else
 280                 clk->rate = (clk->parent->rate * 16) / div;
 281 }
 282
 283 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
 284         unsigned long rate)
 285 {
 286         u32 div, div1;
 287         u32 tmp;
 288         /*
 289          * Calculate divider
 290          * Fractional part is 4 bits,
 291          * so simply multiply by 2^4 to get fractional part.
 292          */
 293         tmp = (clk->parent->rate * 16);
 294         div = tmp / rate;
 295
 296         if (div < 0x10)            /* Min DI disp clock divider is 1 */
 297                 div = 0x10;
 298         if (div & ~0xFEF)
 299                 div &= 0xFF8;
 300         else {
 301                 div1 = div & 0xFE0;
 302                 if ((tmp/div1 - tmp/div) < rate / 4)
 303                         div = div1;
 304                 else
 305                         div &= 0xFF8;
 306         }
 307         return (clk->parent->rate * 16) / div;
 308 }
 309
 310 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 311 {
 312         u32 div = (clk->parent->rate * 16) / rate;
 313
 314         __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 315
 316         /* Setup pixel clock timing */
 317         __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 318
 319         clk->rate = (clk->parent->rate * 16) / div;
 320         return 0;
 321 }
 322
 323 static int ipu_pixel_clk_enable(struct clk *clk)
 324 {
 325         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 326         disp_gen |= clk->id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
 327         __raw_writel(disp_gen, IPU_DISP_GEN);
 328
 329         return 0;
 330 }
 331
 332 static void ipu_pixel_clk_disable(struct clk *clk)
 333 {
 334         u32 disp_gen = __raw_readl(IPU_DISP_GEN);
 335         disp_gen &= clk->id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
 336         __raw_writel(disp_gen, IPU_DISP_GEN);
 337
 338 }
 339
 340 static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 341 {
 342         u32 di_gen = __raw_readl(DI_GENERAL(clk->id));
 343
 344         if (parent == g_ipu_clk)
 345                 di_gen &= ~DI_GEN_DI_CLK_EXT;
 346         else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
 347                 di_gen |= DI_GEN_DI_CLK_EXT;
 348         else
 349                 return -EINVAL;
 350
 351         __raw_writel(di_gen, DI_GENERAL(clk->id));
 352         ipu_pixel_clk_recalc(clk);
 353         return 0;
 354 }
 355
 356 static struct clk pixel_clk[] = {
 357         {
 358         .name = "pixel_clk",
 359         .id = 0,
 360         .recalc = ipu_pixel_clk_recalc,
 361         .set_rate = ipu_pixel_clk_set_rate,
 362         .round_rate = ipu_pixel_clk_round_rate,
 363         .set_parent = ipu_pixel_clk_set_parent,
 364         .enable = ipu_pixel_clk_enable,
 365         .disable = ipu_pixel_clk_disable,
 366         .usecount = 0,
 367         },
 368         {
 369         .name = "pixel_clk",
 370         .id = 1,
 371         .recalc = ipu_pixel_clk_recalc,
 372         .set_rate = ipu_pixel_clk_set_rate,
 373         .round_rate = ipu_pixel_clk_round_rate,
 374         .set_parent = ipu_pixel_clk_set_parent,
 375         .enable = ipu_pixel_clk_enable,
 376         .disable = ipu_pixel_clk_disable,
 377         .usecount = 0,
 378         },
 379 };
 380
 381 /*
 382  * This function resets IPU
 383  */
 384 void ipu_reset(void)
 385 {
 386         u32 *reg;
 387         u32 value;
 388
 389         reg = (u32 *)SRC_BASE_ADDR;
 390         value = __raw_readl(reg);
 391         value = value | SW_IPU_RST;
 392         __raw_writel(value, reg);
 393 }
 394
 395 /*
 396  * This function is called by the driver framework to initialize the IPU
 397  * hardware.
 398  *
 399  * @param       dev     The device structure for the IPU passed in by the
 400  *                      driver framework.
 401  *
 402  * @return      Returns 0 on success or negative error code on error
 403  */
 404 int ipu_probe(void)
 405 {
 406         unsigned long ipu_base;
 407 #if defined CONFIG_MX51
 408         u32 temp;
 409
 410         u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
 411         u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
 412
 413          __raw_writel(0xF00, reg_hsc_mcd);
 414
 415         /* CSI mode reserved*/
 416         temp = __raw_readl(reg_hsc_mxt_conf);
 417          __raw_writel(temp | 0x0FF, reg_hsc_mxt_conf);
 418
 419         temp = __raw_readl(reg_hsc_mxt_conf);
 420         __raw_writel(temp | 0x10000, reg_hsc_mxt_conf);
 421 #endif
 422
 423         ipu_base = IPU_CTRL_BASE_ADDR;
 424         ipu_cpmem_base = (u32 *)(ipu_base + IPU_CPMEM_REG_BASE);
 425         ipu_dc_tmpl_reg = (u32 *)(ipu_base + IPU_DC_TMPL_REG_BASE);
 426
 427         g_pixel_clk[0] = &pixel_clk[0];
 428         g_pixel_clk[1] = &pixel_clk[1];
 429
 430         g_ipu_clk = &ipu_clk;
 431         debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
 432
 433         ipu_reset();
 434
 435         clk_set_parent(g_pixel_clk[0], g_ipu_clk);
 436         clk_set_parent(g_pixel_clk[1], g_ipu_clk);
 437         clk_enable(g_ipu_clk);
 438
 439         g_di_clk[0] = NULL;
 440         g_di_clk[1] = NULL;
 441
 442         __raw_writel(0x807FFFFF, IPU_MEM_RST);
 443         while (__raw_readl(IPU_MEM_RST) & 0x80000000)
 444                 ;
 445
 446         ipu_init_dc_mappings();
 447
 448         __raw_writel(0, IPU_INT_CTRL(5));
 449         __raw_writel(0, IPU_INT_CTRL(6));
 450         __raw_writel(0, IPU_INT_CTRL(9));
 451         __raw_writel(0, IPU_INT_CTRL(10));
 452
 453         /* DMFC Init */
 454         ipu_dmfc_init(DMFC_NORMAL, 1);
 455
 456         /* Set sync refresh channels as high priority */
 457         __raw_writel(0x18800000L, IDMAC_CHA_PRI(0));
 458
 459         /* Set MCU_T to divide MCU access window into 2 */
 460         __raw_writel(0x00400000L | (IPU_MCU_T_DEFAULT << 18), IPU_DISP_GEN);
 461
 462         clk_disable(g_ipu_clk);
 463
 464         return 0;
 465 }
 466
 467 void ipu_dump_registers(void)
 468 {
 469         debug("IPU_CONF = \t0x%08X\n", __raw_readl(IPU_CONF));
 470         debug("IDMAC_CONF = \t0x%08X\n", __raw_readl(IDMAC_CONF));
 471         debug("IDMAC_CHA_EN1 = \t0x%08X\n",
 472                __raw_readl(IDMAC_CHA_EN(0)));
 473         debug("IDMAC_CHA_EN2 = \t0x%08X\n",
 474                __raw_readl(IDMAC_CHA_EN(32)));
 475         debug("IDMAC_CHA_PRI1 = \t0x%08X\n",
 476                __raw_readl(IDMAC_CHA_PRI(0)));
 477         debug("IDMAC_CHA_PRI2 = \t0x%08X\n",
 478                __raw_readl(IDMAC_CHA_PRI(32)));
 479         debug("IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
 480                __raw_readl(IPU_CHA_DB_MODE_SEL(0)));
 481         debug("IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
 482                __raw_readl(IPU_CHA_DB_MODE_SEL(32)));
 483         debug("DMFC_WR_CHAN = \t0x%08X\n",
 484                __raw_readl(DMFC_WR_CHAN));
 485         debug("DMFC_WR_CHAN_DEF = \t0x%08X\n",
 486                __raw_readl(DMFC_WR_CHAN_DEF));
 487         debug("DMFC_DP_CHAN = \t0x%08X\n",
 488                __raw_readl(DMFC_DP_CHAN));
 489         debug("DMFC_DP_CHAN_DEF = \t0x%08X\n",
 490                __raw_readl(DMFC_DP_CHAN_DEF));
 491         debug("DMFC_IC_CTRL = \t0x%08X\n",
 492                __raw_readl(DMFC_IC_CTRL));
 493         debug("IPU_FS_PROC_FLOW1 = \t0x%08X\n",
 494                __raw_readl(IPU_FS_PROC_FLOW1));
 495         debug("IPU_FS_PROC_FLOW2 = \t0x%08X\n",
 496                __raw_readl(IPU_FS_PROC_FLOW2));
 497         debug("IPU_FS_PROC_FLOW3 = \t0x%08X\n",
 498                __raw_readl(IPU_FS_PROC_FLOW3));
 499         debug("IPU_FS_DISP_FLOW1 = \t0x%08X\n",
 500                __raw_readl(IPU_FS_DISP_FLOW1));
 501 }
 502
 503 /*
 504  * This function is called to initialize a logical IPU channel.
 505  *
 506  * @param       channel Input parameter for the logical channel ID to init.
 507  *
 508  * @param       params  Input parameter containing union of channel
 509  *                      initialization parameters.
 510  *
 511  * @return      Returns 0 on success or negative error code on fail
 512  */
 513 int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
 514 {
 515         int ret = 0;
 516         uint32_t ipu_conf;
 517
 518         debug("init channel = %d\n", IPU_CHAN_ID(channel));
 519
 520         if (g_ipu_clk_enabled == 0) {
 521                 g_ipu_clk_enabled = 1;
 522                 clk_enable(g_ipu_clk);
 523         }
 524
 525
 526         if (g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
 527                 printf("Warning: channel already initialized %d\n",
 528                         IPU_CHAN_ID(channel));
 529         }
 530
 531         ipu_conf = __raw_readl(IPU_CONF);
 532
 533         switch (channel) {
 534         case MEM_DC_SYNC:
 535                 if (params->mem_dc_sync.di > 1) {
 536                         ret = -EINVAL;
 537                         goto err;
 538                 }
 539
 540                 g_dc_di_assignment[1] = params->mem_dc_sync.di;
 541                 ipu_dc_init(1, params->mem_dc_sync.di,
 542                              params->mem_dc_sync.interlaced);
 543                 ipu_di_use_count[params->mem_dc_sync.di]++;
 544                 ipu_dc_use_count++;
 545                 ipu_dmfc_use_count++;
 546                 break;
 547         case MEM_BG_SYNC:
 548                 if (params->mem_dp_bg_sync.di > 1) {
 549                         ret = -EINVAL;
 550                         goto err;
 551                 }
 552
 553                 g_dc_di_assignment[5] = params->mem_dp_bg_sync.di;
 554                 ipu_dp_init(channel, params->mem_dp_bg_sync.in_pixel_fmt,
 555                              params->mem_dp_bg_sync.out_pixel_fmt);
 556                 ipu_dc_init(5, params->mem_dp_bg_sync.di,
 557                              params->mem_dp_bg_sync.interlaced);
 558                 ipu_di_use_count[params->mem_dp_bg_sync.di]++;
 559                 ipu_dc_use_count++;
 560                 ipu_dp_use_count++;
 561                 ipu_dmfc_use_count++;
 562                 break;
 563         case MEM_FG_SYNC:
 564                 ipu_dp_init(channel, params->mem_dp_fg_sync.in_pixel_fmt,
 565                              params->mem_dp_fg_sync.out_pixel_fmt);
 566
 567                 ipu_dc_use_count++;
 568                 ipu_dp_use_count++;
 569                 ipu_dmfc_use_count++;
 570                 break;
 571         default:
 572                 printf("Missing channel initialization\n");
 573                 break;
 574         }
 575
 576         /* Enable IPU sub module */
 577         g_channel_init_mask |= 1L << IPU_CHAN_ID(channel);
 578         if (ipu_dc_use_count == 1)
 579                 ipu_conf |= IPU_CONF_DC_EN;
 580         if (ipu_dp_use_count == 1)
 581                 ipu_conf |= IPU_CONF_DP_EN;
 582         if (ipu_dmfc_use_count == 1)
 583                 ipu_conf |= IPU_CONF_DMFC_EN;
 584         if (ipu_di_use_count[0] == 1) {
 585                 ipu_conf |= IPU_CONF_DI0_EN;
 586         }
 587         if (ipu_di_use_count[1] == 1) {
 588                 ipu_conf |= IPU_CONF_DI1_EN;
 589         }
 590
 591         __raw_writel(ipu_conf, IPU_CONF);
 592
 593 err:
 594         return ret;
 595 }
 596
 597 /*
 598  * This function is called to uninitialize a logical IPU channel.
 599  *
 600  * @param       channel Input parameter for the logical channel ID to uninit.
 601  */
 602 void ipu_uninit_channel(ipu_channel_t channel)
 603 {
 604         uint32_t reg;
 605         uint32_t in_dma, out_dma = 0;
 606         uint32_t ipu_conf;
 607
 608         if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
 609                 debug("Channel already uninitialized %d\n",
 610                         IPU_CHAN_ID(channel));
 611                 return;
 612         }
 613
 614         /*
 615          * Make sure channel is disabled
 616          * Get input and output dma channels
 617          */
 618         in_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
 619         out_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
 620
 621         if (idma_is_set(IDMAC_CHA_EN, in_dma) ||
 622             idma_is_set(IDMAC_CHA_EN, out_dma)) {
 623                 printf(
 624                         "Channel %d is not disabled, disable first\n",
 625                         IPU_CHAN_ID(channel));
 626                 return;
 627         }
 628
 629         ipu_conf = __raw_readl(IPU_CONF);
 630
 631         /* Reset the double buffer */
 632         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(in_dma));
 633         __raw_writel(reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
 634         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(out_dma));
 635         __raw_writel(reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
 636
 637         switch (channel) {
 638         case MEM_DC_SYNC:
 639                 ipu_dc_uninit(1);
 640                 ipu_di_use_count[g_dc_di_assignment[1]]--;
 641                 ipu_dc_use_count--;
 642                 ipu_dmfc_use_count--;
 643                 break;
 644         case MEM_BG_SYNC:
 645                 ipu_dp_uninit(channel);
 646                 ipu_dc_uninit(5);
 647                 ipu_di_use_count[g_dc_di_assignment[5]]--;
 648                 ipu_dc_use_count--;
 649                 ipu_dp_use_count--;
 650                 ipu_dmfc_use_count--;
 651                 break;
 652         case MEM_FG_SYNC:
 653                 ipu_dp_uninit(channel);
 654                 ipu_dc_use_count--;
 655                 ipu_dp_use_count--;
 656                 ipu_dmfc_use_count--;
 657                 break;
 658         default:
 659                 break;
 660         }
 661
 662         g_channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
 663
 664         if (ipu_dc_use_count == 0)
 665                 ipu_conf &= ~IPU_CONF_DC_EN;
 666         if (ipu_dp_use_count == 0)
 667                 ipu_conf &= ~IPU_CONF_DP_EN;
 668         if (ipu_dmfc_use_count == 0)
 669                 ipu_conf &= ~IPU_CONF_DMFC_EN;
 670         if (ipu_di_use_count[0] == 0) {
 671                 ipu_conf &= ~IPU_CONF_DI0_EN;
 672         }
 673         if (ipu_di_use_count[1] == 0) {
 674                 ipu_conf &= ~IPU_CONF_DI1_EN;
 675         }
 676
 677         __raw_writel(ipu_conf, IPU_CONF);
 678
 679         if (ipu_conf == 0) {
 680                 clk_disable(g_ipu_clk);
 681                 g_ipu_clk_enabled = 0;
 682         }
 683
 684 }
 685
 686 static inline void ipu_ch_param_dump(int ch)
 687 {
 688 #ifdef DEBUG
 689         struct ipu_ch_param *p = ipu_ch_param_addr(ch);
 690         debug("ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
 691                  p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
 692                  p->word[0].data[3], p->word[0].data[4]);
 693         debug("ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
 694                  p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
 695                  p->word[1].data[3], p->word[1].data[4]);
 696         debug("PFS 0x%x, ",
 697                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 85, 4));
 698         debug("BPP 0x%x, ",
 699                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 107, 3));
 700         debug("NPB 0x%x\n",
 701                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 78, 7));
 702
 703         debug("FW %d, ",
 704                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 125, 13));
 705         debug("FH %d, ",
 706                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 0, 138, 12));
 707         debug("Stride %d\n",
 708                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 102, 14));
 709
 710         debug("Width0 %d+1, ",
 711                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 116, 3));
 712         debug("Width1 %d+1, ",
 713                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 119, 3));
 714         debug("Width2 %d+1, ",
 715                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 122, 3));
 716         debug("Width3 %d+1, ",
 717                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 125, 3));
 718         debug("Offset0 %d, ",
 719                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 128, 5));
 720         debug("Offset1 %d, ",
 721                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 133, 5));
 722         debug("Offset2 %d, ",
 723                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 138, 5));
 724         debug("Offset3 %d\n",
 725                  ipu_ch_param_read_field(ipu_ch_param_addr(ch), 1, 143, 5));
 726 #endif
 727 }
 728
 729 static inline void ipu_ch_params_set_packing(struct ipu_ch_param *p,
 730                                               int red_width, int red_offset,
 731                                               int green_width, int green_offset,
 732                                               int blue_width, int blue_offset,
 733                                               int alpha_width, int alpha_offset)
 734 {
 735         /* Setup red width and offset */
 736         ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
 737         ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
 738         /* Setup green width and offset */
 739         ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
 740         ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
 741         /* Setup blue width and offset */
 742         ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
 743         ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
 744         /* Setup alpha width and offset */
 745         ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
 746         ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
 747 }
 748
 749 static void ipu_ch_param_init(int ch,
 750                               uint32_t pixel_fmt, uint32_t width,
 751                               uint32_t height, uint32_t stride,
 752                               uint32_t u, uint32_t v,
 753                               uint32_t uv_stride, dma_addr_t addr0,
 754                               dma_addr_t addr1)
 755 {
 756         uint32_t u_offset = 0;
 757         uint32_t v_offset = 0;
 758         struct ipu_ch_param params;
 759
 760         memset(&params, 0, sizeof(params));
 761
 762         ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
 763
 764         if ((ch == 8) || (ch == 9) || (ch == 10)) {
 765                 ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
 766                 ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
 767         } else {
 768                 ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
 769                 ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
 770         }
 771
 772         ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
 773         ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
 774
 775         switch (pixel_fmt) {
 776         case IPU_PIX_FMT_GENERIC:
 777                 /*Represents 8-bit Generic data */
 778                 ipu_ch_param_set_field(&params, 0, 107, 3, 5);  /* bits/pixel */
 779                 ipu_ch_param_set_field(&params, 1, 85, 4, 6);   /* pix format */
 780                 ipu_ch_param_set_field(&params, 1, 78, 7, 63);  /* burst size */
 781
 782                 break;
 783         case IPU_PIX_FMT_GENERIC_32:
 784                 /*Represents 32-bit Generic data */
 785                 break;
 786         case IPU_PIX_FMT_RGB565:
 787                 ipu_ch_param_set_field(&params, 0, 107, 3, 3);  /* bits/pixel */
 788                 ipu_ch_param_set_field(&params, 1, 85, 4, 7);   /* pix format */
 789                 ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
 790
 791                 ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
 792                 break;
 793         case IPU_PIX_FMT_BGR24:
 794                 ipu_ch_param_set_field(&params, 0, 107, 3, 1);  /* bits/pixel */
 795                 ipu_ch_param_set_field(&params, 1, 85, 4, 7);   /* pix format */
 796                 ipu_ch_param_set_field(&params, 1, 78, 7, 19);  /* burst size */
 797
 798                 ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
 799                 break;
 800         case IPU_PIX_FMT_RGB24:
 801         case IPU_PIX_FMT_YUV444:
 802                 ipu_ch_param_set_field(&params, 0, 107, 3, 1);  /* bits/pixel */
 803                 ipu_ch_param_set_field(&params, 1, 85, 4, 7);   /* pix format */
 804                 ipu_ch_param_set_field(&params, 1, 78, 7, 19);  /* burst size */
 805
 806                 ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
 807                 break;
 808         case IPU_PIX_FMT_BGRA32:
 809         case IPU_PIX_FMT_BGR32:
 810                 ipu_ch_param_set_field(&params, 0, 107, 3, 0);  /* bits/pixel */
 811                 ipu_ch_param_set_field(&params, 1, 85, 4, 7);   /* pix format */
 812                 ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
 813
 814                 ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
 815                 break;
 816         case IPU_PIX_FMT_RGBA32:
 817         case IPU_PIX_FMT_RGB32:
 818                 ipu_ch_param_set_field(&params, 0, 107, 3, 0);  /* bits/pixel */
 819                 ipu_ch_param_set_field(&params, 1, 85, 4, 7);   /* pix format */
 820                 ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
 821
 822                 ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
 823                 break;
 824         case IPU_PIX_FMT_ABGR32:
 825                 ipu_ch_param_set_field(&params, 0, 107, 3, 0);  /* bits/pixel */
 826                 ipu_ch_param_set_field(&params, 1, 85, 4, 7);   /* pix format */
 827
 828                 ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
 829                 break;
 830         case IPU_PIX_FMT_UYVY:
 831                 ipu_ch_param_set_field(&params, 0, 107, 3, 3);  /* bits/pixel */
 832                 ipu_ch_param_set_field(&params, 1, 85, 4, 0xA); /* pix format */
 833                 ipu_ch_param_set_field(&params, 1, 78, 7, 15);  /* burst size */
 834                 break;
 835         case IPU_PIX_FMT_YUYV:
 836                 ipu_ch_param_set_field(&params, 0, 107, 3, 3);  /* bits/pixel */
 837                 ipu_ch_param_set_field(&params, 1, 85, 4, 0x8); /* pix format */
 838                 ipu_ch_param_set_field(&params, 1, 78, 7, 31);  /* burst size */
 839                 break;
 840         case IPU_PIX_FMT_YUV420P2:
 841         case IPU_PIX_FMT_YUV420P:
 842                 ipu_ch_param_set_field(&params, 1, 85, 4, 2);   /* pix format */
 843
 844                 if (uv_stride < stride / 2)
 845                         uv_stride = stride / 2;
 846
 847                 u_offset = stride * height;
 848                 v_offset = u_offset + (uv_stride * height / 2);
 849                 /* burst size */
 850                 if ((ch == 8) || (ch == 9) || (ch == 10)) {
 851                         ipu_ch_param_set_field(&params, 1, 78, 7, 15);
 852                         uv_stride = uv_stride*2;
 853                 } else {
 854                         ipu_ch_param_set_field(&params, 1, 78, 7, 31);
 855                 }
 856                 break;
 857         case IPU_PIX_FMT_YVU422P:
 858                 /* BPP & pixel format */
 859                 ipu_ch_param_set_field(&params, 1, 85, 4, 1);   /* pix format */
 860                 ipu_ch_param_set_field(&params, 1, 78, 7, 31);  /* burst size */
 861
 862                 if (uv_stride < stride / 2)
 863                         uv_stride = stride / 2;
 864
 865                 v_offset = (v == 0) ? stride * height : v;
 866                 u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
 867                 break;
 868         case IPU_PIX_FMT_YUV422P:
 869                 /* BPP & pixel format */
 870                 ipu_ch_param_set_field(&params, 1, 85, 4, 1);   /* pix format */
 871                 ipu_ch_param_set_field(&params, 1, 78, 7, 31);  /* burst size */
 872
 873                 if (uv_stride < stride / 2)
 874                         uv_stride = stride / 2;
 875
 876                 u_offset = (u == 0) ? stride * height : u;
 877                 v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
 878                 break;
 879         case IPU_PIX_FMT_NV12:
 880                 /* BPP & pixel format */
 881                 ipu_ch_param_set_field(&params, 1, 85, 4, 4);   /* pix format */
 882                 ipu_ch_param_set_field(&params, 1, 78, 7, 31);  /* burst size */
 883                 uv_stride = stride;
 884                 u_offset = (u == 0) ? stride * height : u;
 885                 break;
 886         default:
 887                 puts("mxc ipu: unimplemented pixel format\n");
 888                 break;
 889         }
 890
 891
 892         if (uv_stride)
 893                 ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
 894
 895         /* Get the uv offset from user when need cropping */
 896         if (u || v) {
 897                 u_offset = u;
 898                 v_offset = v;
 899         }
 900
 901         /* UBO and VBO are 22-bit */
 902         if (u_offset/8 > 0x3fffff)
 903                 puts("The value of U offset exceeds IPU limitation\n");
 904         if (v_offset/8 > 0x3fffff)
 905                 puts("The value of V offset exceeds IPU limitation\n");
 906
 907         ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
 908         ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
 909
 910         debug("initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ch));
 911         memcpy(ipu_ch_param_addr(ch), &params, sizeof(params));
 912 };
 913
 914 /*
 915  * This function is called to initialize a buffer for logical IPU channel.
 916  *
 917  * @param       channel         Input parameter for the logical channel ID.
 918  *
 919  * @param       type            Input parameter which buffer to initialize.
 920  *
 921  * @param       pixel_fmt       Input parameter for pixel format of buffer.
 922  *                              Pixel format is a FOURCC ASCII code.
 923  *
 924  * @param       width           Input parameter for width of buffer in pixels.
 925  *
 926  * @param       height          Input parameter for height of buffer in pixels.
 927  *
 928  * @param       stride          Input parameter for stride length of buffer
 929  *                              in pixels.
 930  *
 931  * @param       phyaddr_0       Input parameter buffer 0 physical address.
 932  *
 933  * @param       phyaddr_1       Input parameter buffer 1 physical address.
 934  *                              Setting this to a value other than NULL enables
 935  *                              double buffering mode.
 936  *
 937  * @param       u               private u offset for additional cropping,
 938  *                              zero if not used.
 939  *
 940  * @param       v               private v offset for additional cropping,
 941  *                              zero if not used.
 942  *
 943  * @return      Returns 0 on success or negative error code on fail
 944  */
 945 int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 946                                 uint32_t pixel_fmt,
 947                                 uint16_t width, uint16_t height,
 948                                 uint32_t stride,
 949                                 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 950                                 uint32_t u, uint32_t v)
 951 {
 952         uint32_t reg;
 953         uint32_t dma_chan;
 954
 955         dma_chan = channel_2_dma(channel, type);
 956         if (!idma_is_valid(dma_chan))
 957                 return -EINVAL;
 958
 959         if (stride < width * bytes_per_pixel(pixel_fmt))
 960                 stride = width * bytes_per_pixel(pixel_fmt);
 961
 962         if (stride % 4) {
 963                 printf(
 964                         "Stride not 32-bit aligned, stride = %d\n", stride);
 965                 return -EINVAL;
 966         }
 967         /* Build parameter memory data for DMA channel */
 968         ipu_ch_param_init(dma_chan, pixel_fmt, width, height, stride, u, v, 0,
 969                            phyaddr_0, phyaddr_1);
 970
 971         if (ipu_is_dmfc_chan(dma_chan)) {
 972                 ipu_dmfc_set_wait4eot(dma_chan, width);
 973         }
 974
 975         if (idma_is_set(IDMAC_CHA_PRI, dma_chan))
 976                 ipu_ch_param_set_high_priority(dma_chan);
 977
 978         ipu_ch_param_dump(dma_chan);
 979
 980         reg = __raw_readl(IPU_CHA_DB_MODE_SEL(dma_chan));
 981         if (phyaddr_1)
 982                 reg |= idma_mask(dma_chan);
 983         else
 984                 reg &= ~idma_mask(dma_chan);
 985         __raw_writel(reg, IPU_CHA_DB_MODE_SEL(dma_chan));
 986
 987         /* Reset to buffer 0 */
 988         __raw_writel(idma_mask(dma_chan), IPU_CHA_CUR_BUF(dma_chan));
 989
 990         return 0;
 991 }
 992
 993 /*
 994  * This function enables a logical channel.
 995  *
 996  * @param       channel         Input parameter for the logical channel ID.
 997  *
 998  * @return      This function returns 0 on success or negative error code on
 999  *              fail.
1000  */
1001 int32_t ipu_enable_channel(ipu_channel_t channel)
1002 {
1003         uint32_t reg;
1004         uint32_t in_dma;
1005         uint32_t out_dma;
1006
1007         if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
1008                 printf("Warning: channel already enabled %d\n",
1009                         IPU_CHAN_ID(channel));
1010         }
1011
1012         /* Get input and output dma channels */
1013         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1014         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1015
1016         if (idma_is_valid(in_dma)) {
1017                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1018                 __raw_writel(reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1019         }
1020         if (idma_is_valid(out_dma)) {
1021                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1022                 __raw_writel(reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1023         }
1024
1025         if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
1026             (channel == MEM_FG_SYNC))
1027                 ipu_dp_dc_enable(channel);
1028
1029         g_channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
1030
1031         return 0;
1032 }
1033
1034 /*
1035  * This function clear buffer ready for a logical channel.
1036  *
1037  * @param       channel         Input parameter for the logical channel ID.
1038  *
1039  * @param       type            Input parameter which buffer to clear.
1040  *
1041  * @param       bufNum          Input parameter for which buffer number clear
1042  *                              ready state.
1043  *
1044  */
1045 void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
1046                 uint32_t bufNum)
1047 {
1048         uint32_t dma_ch = channel_2_dma(channel, type);
1049
1050         if (!idma_is_valid(dma_ch))
1051                 return;
1052
1053         __raw_writel(0xF0000000, IPU_GPR); /* write one to clear */
1054         if (bufNum == 0) {
1055                 if (idma_is_set(IPU_CHA_BUF0_RDY, dma_ch)) {
1056                         __raw_writel(idma_mask(dma_ch),
1057                                         IPU_CHA_BUF0_RDY(dma_ch));
1058                 }
1059         } else {
1060                 if (idma_is_set(IPU_CHA_BUF1_RDY, dma_ch)) {
1061                         __raw_writel(idma_mask(dma_ch),
1062                                         IPU_CHA_BUF1_RDY(dma_ch));
1063                 }
1064         }
1065         __raw_writel(0x0, IPU_GPR); /* write one to set */
1066 }
1067
1068 /*
1069  * This function disables a logical channel.
1070  *
1071  * @param       channel         Input parameter for the logical channel ID.
1072  *
1073  * @param       wait_for_stop   Flag to set whether to wait for channel end
1074  *                              of frame or return immediately.
1075  *
1076  * @return      This function returns 0 on success or negative error code on
1077  *              fail.
1078  */
1079 int32_t ipu_disable_channel(ipu_channel_t channel)
1080 {
1081         uint32_t reg;
1082         uint32_t in_dma;
1083         uint32_t out_dma;
1084
1085         if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
1086                 debug("Channel already disabled %d\n",
1087                         IPU_CHAN_ID(channel));
1088                 return 0;
1089         }
1090
1091         /* Get input and output dma channels */
1092         out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
1093         in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
1094
1095         if ((idma_is_valid(in_dma) &&
1096                 !idma_is_set(IDMAC_CHA_EN, in_dma))
1097                 && (idma_is_valid(out_dma) &&
1098                 !idma_is_set(IDMAC_CHA_EN, out_dma)))
1099                 return -EINVAL;
1100
1101         if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
1102             (channel == MEM_DC_SYNC)) {
1103                 ipu_dp_dc_disable(channel, 0);
1104         }
1105
1106         /* Disable DMA channel(s) */
1107         if (idma_is_valid(in_dma)) {
1108                 reg = __raw_readl(IDMAC_CHA_EN(in_dma));
1109                 __raw_writel(reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
1110                 __raw_writel(idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
1111         }
1112         if (idma_is_valid(out_dma)) {
1113                 reg = __raw_readl(IDMAC_CHA_EN(out_dma));
1114                 __raw_writel(reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
1115                 __raw_writel(idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
1116         }
1117
1118         g_channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
1119
1120         /* Set channel buffers NOT to be ready */
1121         if (idma_is_valid(in_dma)) {
1122                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 0);
1123                 ipu_clear_buffer_ready(channel, IPU_VIDEO_IN_BUFFER, 1);
1124         }
1125         if (idma_is_valid(out_dma)) {
1126                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 0);
1127                 ipu_clear_buffer_ready(channel, IPU_OUTPUT_BUFFER, 1);
1128         }
1129
1130         return 0;
1131 }
1132
1133 uint32_t bytes_per_pixel(uint32_t fmt)
1134 {
1135         switch (fmt) {
1136         case IPU_PIX_FMT_GENERIC:       /*generic data */
1137         case IPU_PIX_FMT_RGB332:
1138         case IPU_PIX_FMT_YUV420P:
1139         case IPU_PIX_FMT_YUV422P:
1140                 return 1;
1141                 break;
1142         case IPU_PIX_FMT_RGB565:
1143         case IPU_PIX_FMT_YUYV:
1144         case IPU_PIX_FMT_UYVY:
1145                 return 2;
1146                 break;
1147         case IPU_PIX_FMT_BGR24:
1148         case IPU_PIX_FMT_RGB24:
1149                 return 3;
1150                 break;
1151         case IPU_PIX_FMT_GENERIC_32:    /*generic data */
1152         case IPU_PIX_FMT_BGR32:
1153         case IPU_PIX_FMT_BGRA32:
1154         case IPU_PIX_FMT_RGB32:
1155         case IPU_PIX_FMT_RGBA32:
1156         case IPU_PIX_FMT_ABGR32:
1157                 return 4;
1158                 break;
1159         default:
1160                 return 1;
1161                 break;
1162         }
1163         return 0;
1164 }
1165
1166 ipu_color_space_t format_to_colorspace(uint32_t fmt)
1167 {
1168         switch (fmt) {
1169         case IPU_PIX_FMT_RGB666:
1170         case IPU_PIX_FMT_RGB565:
1171         case IPU_PIX_FMT_BGR24:
1172         case IPU_PIX_FMT_RGB24:
1173         case IPU_PIX_FMT_BGR32:
1174         case IPU_PIX_FMT_BGRA32:
1175         case IPU_PIX_FMT_RGB32:
1176         case IPU_PIX_FMT_RGBA32:
1177         case IPU_PIX_FMT_ABGR32:
1178         case IPU_PIX_FMT_LVDS666:
1179         case IPU_PIX_FMT_LVDS888:
1180                 return RGB;
1181                 break;
1182
1183         default:
1184                 return YCbCr;
1185                 break;
1186         }
1187         return RGB;
1188 }