drivers/video/pxa_lcd.c

   1 /*
   2  * PXA LCD Controller
   3  *
   4  * (C) Copyright 2001-2002
   5  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /************************************************************************/
  11 /* ** HEADER FILES                                                      */
  12 /************************************************************************/
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <version.h>
  17 #include <stdarg.h>
  18 #include <linux/types.h>
  19 #include <stdio_dev.h>
  20 #include <lcd.h>
  21 #include <asm/arch/pxa-regs.h>
  22 #include <asm/io.h>
  23
  24 /* #define DEBUG */
  25
  26 #ifdef CONFIG_LCD
  27
  28 /*----------------------------------------------------------------------*/
  29 /*
  30  * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  31  * your display.
  32  */
  33
  34 #ifdef CONFIG_PXA_VGA
  35 /* LCD outputs connected to a video DAC  */
  36 # define LCD_BPP        LCD_COLOR8
  37
  38 /* you have to set lccr0 and lccr3 (including pcd) */
  39 # define REG_LCCR0      0x003008f8
  40 # define REG_LCCR3      0x0300FF01
  41
  42 /* 640x480x16 @ 61 Hz */
  43 vidinfo_t panel_info = {
  44         .vl_col         = 640,
  45         .vl_row         = 480,
  46         .vl_width       = 640,
  47         .vl_height      = 480,
  48         .vl_clkp        = CONFIG_SYS_HIGH,
  49         .vl_oep         = CONFIG_SYS_HIGH,
  50         .vl_hsp         = CONFIG_SYS_HIGH,
  51         .vl_vsp         = CONFIG_SYS_HIGH,
  52         .vl_dp          = CONFIG_SYS_HIGH,
  53         .vl_bpix        = LCD_BPP,
  54         .vl_lbw         = 0,
  55         .vl_splt        = 0,
  56         .vl_clor        = 0,
  57         .vl_tft         = 1,
  58         .vl_hpw         = 40,
  59         .vl_blw         = 56,
  60         .vl_elw         = 56,
  61         .vl_vpw         = 20,
  62         .vl_bfw         = 8,
  63         .vl_efw         = 8,
  64 };
  65 #endif /* CONFIG_PXA_VIDEO */
  66
  67 /*----------------------------------------------------------------------*/
  68 #ifdef CONFIG_SHARP_LM8V31
  69
  70 # define LCD_BPP        LCD_COLOR8
  71 # define LCD_INVERT_COLORS      /* Needed for colors to be correct, but why?    */
  72
  73 /* you have to set lccr0 and lccr3 (including pcd) */
  74 # define REG_LCCR0      0x0030087C
  75 # define REG_LCCR3      0x0340FF08
  76
  77 vidinfo_t panel_info = {
  78         .vl_col         = 640,
  79         .vl_row         = 480,
  80         .vl_width       = 157,
  81         .vl_height      = 118,
  82         .vl_clkp        = CONFIG_SYS_HIGH,
  83         .vl_oep         = CONFIG_SYS_HIGH,
  84         .vl_hsp         = CONFIG_SYS_HIGH,
  85         .vl_vsp         = CONFIG_SYS_HIGH,
  86         .vl_dp          = CONFIG_SYS_HIGH,
  87         .vl_bpix        = LCD_BPP,
  88         .vl_lbw         = 0,
  89         .vl_splt        = 1,
  90         .vl_clor        = 1,
  91         .vl_tft         = 0,
  92         .vl_hpw         = 1,
  93         .vl_blw         = 3,
  94         .vl_elw         = 3,
  95         .vl_vpw         = 1,
  96         .vl_bfw         = 0,
  97         .vl_efw         = 0,
  98 };
  99 #endif /* CONFIG_SHARP_LM8V31 */
 100 /*----------------------------------------------------------------------*/
 101 #ifdef CONFIG_VOIPAC_LCD
 102
 103 # define LCD_BPP        LCD_COLOR8
 104 # define LCD_INVERT_COLORS
 105
 106 /* you have to set lccr0 and lccr3 (including pcd) */
 107 # define REG_LCCR0      0x043008f8
 108 # define REG_LCCR3      0x0340FF08
 109
 110 vidinfo_t panel_info = {
 111         .vl_col         = 640,
 112         .vl_row         = 480,
 113         .vl_width       = 157,
 114         .vl_height      = 118,
 115         .vl_clkp        = CONFIG_SYS_HIGH,
 116         .vl_oep         = CONFIG_SYS_HIGH,
 117         .vl_hsp         = CONFIG_SYS_HIGH,
 118         .vl_vsp         = CONFIG_SYS_HIGH,
 119         .vl_dp          = CONFIG_SYS_HIGH,
 120         .vl_bpix        = LCD_BPP,
 121         .vl_lbw         = 0,
 122         .vl_splt        = 1,
 123         .vl_clor        = 1,
 124         .vl_tft         = 1,
 125         .vl_hpw         = 32,
 126         .vl_blw         = 144,
 127         .vl_elw         = 32,
 128         .vl_vpw         = 2,
 129         .vl_bfw         = 13,
 130         .vl_efw         = 30,
 131 };
 132 #endif /* CONFIG_VOIPAC_LCD */
 133
 134 /*----------------------------------------------------------------------*/
 135 #ifdef CONFIG_HITACHI_SX14
 136 /* Hitachi SX14Q004-ZZA color STN LCD */
 137 #define LCD_BPP         LCD_COLOR8
 138
 139 /* you have to set lccr0 and lccr3 (including pcd) */
 140 #define REG_LCCR0       0x00301079
 141 #define REG_LCCR3       0x0340FF20
 142
 143 vidinfo_t panel_info = {
 144         .vl_col         = 320,
 145         .vl_row         = 240,
 146         .vl_width       = 167,
 147         .vl_height      = 109,
 148         .vl_clkp        = CONFIG_SYS_HIGH,
 149         .vl_oep         = CONFIG_SYS_HIGH,
 150         .vl_hsp         = CONFIG_SYS_HIGH,
 151         .vl_vsp         = CONFIG_SYS_HIGH,
 152         .vl_dp          = CONFIG_SYS_HIGH,
 153         .vl_bpix        = LCD_BPP,
 154         .vl_lbw         = 1,
 155         .vl_splt        = 0,
 156         .vl_clor        = 1,
 157         .vl_tft         = 0,
 158         .vl_hpw         = 1,
 159         .vl_blw         = 1,
 160         .vl_elw         = 1,
 161         .vl_vpw         = 7,
 162         .vl_bfw         = 0,
 163         .vl_efw         = 0,
 164 };
 165 #endif /* CONFIG_HITACHI_SX14 */
 166
 167 /*----------------------------------------------------------------------*/
 168 #ifdef CONFIG_LMS283GF05
 169
 170 # define LCD_BPP        LCD_COLOR8
 171 /*# define LCD_INVERT_COLORS*/
 172
 173 /* you have to set lccr0 and lccr3 (including pcd) */
 174 # define REG_LCCR0      0x043008f8
 175 # define REG_LCCR3      0x03b00009
 176
 177 vidinfo_t panel_info = {
 178         .vl_col         = 240,
 179         .vl_row         = 320,
 180         .vl_width       = 240,
 181         .vl_height      = 320,
 182         .vl_clkp        = CONFIG_SYS_HIGH,
 183         .vl_oep         = CONFIG_SYS_LOW,
 184         .vl_hsp         = CONFIG_SYS_LOW,
 185         .vl_vsp         = CONFIG_SYS_LOW,
 186         .vl_dp          = CONFIG_SYS_HIGH,
 187         .vl_bpix        = LCD_BPP,
 188         .vl_lbw         = 0,
 189         .vl_splt        = 1,
 190         .vl_clor        = 1,
 191         .vl_tft         = 1,
 192         .vl_hpw         = 4,
 193         .vl_blw         = 4,
 194         .vl_elw         = 8,
 195         .vl_vpw         = 4,
 196         .vl_bfw         = 4,
 197         .vl_efw         = 8,
 198 };
 199 #endif /* CONFIG_LMS283GF05 */
 200
 201 /*----------------------------------------------------------------------*/
 202
 203 #ifdef CONFIG_ACX517AKN
 204
 205 # define LCD_BPP        LCD_COLOR8
 206
 207 /* you have to set lccr0 and lccr3 (including pcd) */
 208 # define REG_LCCR0      0x003008f9
 209 # define REG_LCCR3      0x03700006
 210
 211 vidinfo_t panel_info = {
 212         .vl_col         = 320,
 213         .vl_row         = 320,
 214         .vl_width       = 320,
 215         .vl_height      = 320,
 216         .vl_clkp        = CONFIG_SYS_HIGH,
 217         .vl_oep         = CONFIG_SYS_LOW,
 218         .vl_hsp         = CONFIG_SYS_LOW,
 219         .vl_vsp         = CONFIG_SYS_LOW,
 220         .vl_dp          = CONFIG_SYS_HIGH,
 221         .vl_bpix        = LCD_BPP,
 222         .vl_lbw         = 0,
 223         .vl_splt        = 1,
 224         .vl_clor        = 1,
 225         .vl_tft         = 1,
 226         .vl_hpw         = 0x04,
 227         .vl_blw         = 0x1c,
 228         .vl_elw         = 0x08,
 229         .vl_vpw         = 0x01,
 230         .vl_bfw         = 0x07,
 231         .vl_efw         = 0x08,
 232 };
 233 #endif /* CONFIG_ACX517AKN */
 234
 235 #ifdef CONFIG_ACX544AKN
 236
 237 # define LCD_BPP        LCD_COLOR16
 238
 239 /* you have to set lccr0 and lccr3 (including pcd) */
 240 # define REG_LCCR0      0x003008f9
 241 # define REG_LCCR3      0x04700007 /* 16bpp */
 242
 243 vidinfo_t panel_info = {
 244         .vl_col         = 320,
 245         .vl_row         = 320,
 246         .vl_width       = 320,
 247         .vl_height      = 320,
 248         .vl_clkp        = CONFIG_SYS_LOW,
 249         .vl_oep         = CONFIG_SYS_LOW,
 250         .vl_hsp         = CONFIG_SYS_LOW,
 251         .vl_vsp         = CONFIG_SYS_LOW,
 252         .vl_dp          = CONFIG_SYS_LOW,
 253         .vl_bpix        = LCD_BPP,
 254         .vl_lbw         = 0,
 255         .vl_splt        = 0,
 256         .vl_clor        = 1,
 257         .vl_tft         = 1,
 258         .vl_hpw         = 0x05,
 259         .vl_blw         = 0x13,
 260         .vl_elw         = 0x08,
 261         .vl_vpw         = 0x02,
 262         .vl_bfw         = 0x07,
 263         .vl_efw         = 0x05,
 264 };
 265 #endif /* CONFIG_ACX544AKN */
 266
 267 /*----------------------------------------------------------------------*/
 268
 269 #ifdef CONFIG_LQ038J7DH53
 270
 271 # define LCD_BPP        LCD_COLOR8
 272
 273 /* you have to set lccr0 and lccr3 (including pcd) */
 274 # define REG_LCCR0      0x003008f9
 275 # define REG_LCCR3      0x03700004
 276
 277 vidinfo_t panel_info = {
 278         .vl_col         = 320,
 279         .vl_row         = 480,
 280         .vl_width       = 320,
 281         .vl_height      = 480,
 282         .vl_clkp        = CONFIG_SYS_HIGH,
 283         .vl_oep         = CONFIG_SYS_LOW,
 284         .vl_hsp         = CONFIG_SYS_LOW,
 285         .vl_vsp         = CONFIG_SYS_LOW,
 286         .vl_dp          = CONFIG_SYS_HIGH,
 287         .vl_bpix        = LCD_BPP,
 288         .vl_lbw         = 0,
 289         .vl_splt        = 1,
 290         .vl_clor        = 1,
 291         .vl_tft         = 1,
 292         .vl_hpw         = 0x04,
 293         .vl_blw         = 0x20,
 294         .vl_elw         = 0x01,
 295         .vl_vpw         = 0x01,
 296         .vl_bfw         = 0x04,
 297         .vl_efw         = 0x01,
 298 };
 299 #endif /* CONFIG_ACX517AKN */
 300
 301 /*----------------------------------------------------------------------*/
 302
 303 #ifdef CONFIG_LITTLETON_LCD
 304 # define LCD_BPP        LCD_COLOR8
 305
 306 /* you have to set lccr0 and lccr3 (including pcd) */
 307 # define REG_LCCR0      0x003008f8
 308 # define REG_LCCR3      0x0300FF04
 309
 310 vidinfo_t panel_info = {
 311         .vl_col         = 480,
 312         .vl_row         = 640,
 313         .vl_width       = 480,
 314         .vl_height      = 640,
 315         .vl_clkp        = CONFIG_SYS_HIGH,
 316         .vl_oep         = CONFIG_SYS_HIGH,
 317         .vl_hsp         = CONFIG_SYS_HIGH,
 318         .vl_vsp         = CONFIG_SYS_HIGH,
 319         .vl_dp          = CONFIG_SYS_HIGH,
 320         .vl_bpix        = LCD_BPP,
 321         .vl_lbw         = 0,
 322         .vl_splt        = 0,
 323         .vl_clor        = 0,
 324         .vl_tft         = 1,
 325         .vl_hpw         = 9,
 326         .vl_blw         = 8,
 327         .vl_elw         = 24,
 328         .vl_vpw         = 2,
 329         .vl_bfw         = 2,
 330         .vl_efw         = 4,
 331 };
 332 #endif /* CONFIG_LITTLETON_LCD */
 333
 334 /*----------------------------------------------------------------------*/
 335
 336 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
 337 static void pxafb_setup_gpio (vidinfo_t *vid);
 338 static void pxafb_enable_controller (vidinfo_t *vid);
 339 static int pxafb_init (vidinfo_t *vid);
 340
 341 /************************************************************************/
 342 /* ---------------  PXA chipset specific functions  ------------------- */
 343 /************************************************************************/
 344
 345 void lcd_ctrl_init (void *lcdbase)
 346 {
 347         pxafb_init_mem(lcdbase, &panel_info);
 348         pxafb_init(&panel_info);
 349         pxafb_setup_gpio(&panel_info);
 350         pxafb_enable_controller(&panel_info);
 351 }
 352
 353 /*----------------------------------------------------------------------*/
 354 #if LCD_BPP == LCD_COLOR8
 355 void
 356 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 357 {
 358         struct pxafb_info *fbi = &panel_info.pxa;
 359         unsigned short *palette = (unsigned short *)fbi->palette;
 360         u_int val;
 361
 362         if (regno < fbi->palette_size) {
 363                 val = ((red << 8) & 0xf800);
 364                 val |= ((green << 4) & 0x07e0);
 365                 val |= (blue & 0x001f);
 366
 367 #ifdef LCD_INVERT_COLORS
 368                 palette[regno] = ~val;
 369 #else
 370                 palette[regno] = val;
 371 #endif
 372         }
 373
 374         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
 375                 regno, &palette[regno],
 376                 red, green, blue,
 377                 palette[regno]);
 378 }
 379 #endif /* LCD_COLOR8 */
 380
 381 /*----------------------------------------------------------------------*/
 382 #if LCD_BPP == LCD_MONOCHROME
 383 void lcd_initcolregs (void)
 384 {
 385         struct pxafb_info *fbi = &panel_info.pxa;
 386         cmap = (ushort *)fbi->palette;
 387         ushort regno;
 388
 389         for (regno = 0; regno < 16; regno++) {
 390                 cmap[regno * 2] = 0;
 391                 cmap[(regno * 2) + 1] = regno & 0x0f;
 392         }
 393 }
 394 #endif /* LCD_MONOCHROME */
 395
 396 /*----------------------------------------------------------------------*/
 397 __weak void lcd_enable(void)
 398 {
 399 }
 400
 401 /************************************************************************/
 402 /* ** PXA255 specific routines                                          */
 403 /************************************************************************/
 404
 405 /*
 406  * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 407  * descriptors and palette areas.
 408  */
 409 ulong calc_fbsize (void)
 410 {
 411         ulong size;
 412         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 413
 414         size = line_length * panel_info.vl_row;
 415         size += PAGE_SIZE;
 416
 417         return size;
 418 }
 419
 420 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 421 {
 422         u_long palette_mem_size;
 423         struct pxafb_info *fbi = &vid->pxa;
 424         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 425
 426         fbi->screen = (u_long)lcdbase;
 427
 428         fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
 429         palette_mem_size = fbi->palette_size * sizeof(u16);
 430
 431         debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 432         /* locate palette and descs at end of page following fb */
 433         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 434
 435         return 0;
 436 }
 437 #ifdef  CONFIG_CPU_MONAHANS
 438 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
 439 #else
 440 static void pxafb_setup_gpio (vidinfo_t *vid)
 441 {
 442         u_long lccr0;
 443
 444         /*
 445          * setup is based on type of panel supported
 446          */
 447
 448         lccr0 = vid->pxa.reg_lccr0;
 449
 450         /* 4 bit interface */
 451         if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
 452         {
 453                 debug("Setting GPIO for 4 bit data\n");
 454                 /* bits 58-61 */
 455                 writel(readl(GPDR1) | (0xf << 26), GPDR1);
 456                 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
 457                         GAFR1_U);
 458
 459                 /* bits 74-77 */
 460                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 461                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 462                         GAFR2_L);
 463         }
 464
 465         /* 8 bit interface */
 466         else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
 467                 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
 468         {
 469                 debug("Setting GPIO for 8 bit data\n");
 470                 /* bits 58-65 */
 471                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 472                 writel(readl(GPDR2) | (0x3), GPDR2);
 473
 474                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 475                         GAFR1_U);
 476                 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
 477
 478                 /* bits 74-77 */
 479                 writel(readl(GPDR2) | (0xf << 10), GPDR2);
 480                 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
 481                         GAFR2_L);
 482         }
 483
 484         /* 16 bit interface */
 485         else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
 486         {
 487                 debug("Setting GPIO for 16 bit data\n");
 488                 /* bits 58-77 */
 489                 writel(readl(GPDR1) | (0x3f << 26), GPDR1);
 490                 writel(readl(GPDR2) | 0x00003fff, GPDR2);
 491
 492                 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
 493                         GAFR1_U);
 494                 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
 495         }
 496         else
 497         {
 498                 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 499         }
 500 }
 501 #endif
 502
 503 static void pxafb_enable_controller (vidinfo_t *vid)
 504 {
 505         debug("Enabling LCD controller\n");
 506
 507         /* Sequence from 11.7.10 */
 508         writel(vid->pxa.reg_lccr3, LCCR3);
 509         writel(vid->pxa.reg_lccr2, LCCR2);
 510         writel(vid->pxa.reg_lccr1, LCCR1);
 511         writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
 512         writel(vid->pxa.fdadr0, FDADR0);
 513         writel(vid->pxa.fdadr1, FDADR1);
 514         writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
 515
 516 #ifdef  CONFIG_CPU_MONAHANS
 517         writel(readl(CKENA) | CKENA_1_LCD, CKENA);
 518 #else
 519         writel(readl(CKEN) | CKEN16_LCD, CKEN);
 520 #endif
 521
 522         debug("FDADR0 = 0x%08x\n", readl(FDADR0));
 523         debug("FDADR1 = 0x%08x\n", readl(FDADR1));
 524         debug("LCCR0 = 0x%08x\n", readl(LCCR0));
 525         debug("LCCR1 = 0x%08x\n", readl(LCCR1));
 526         debug("LCCR2 = 0x%08x\n", readl(LCCR2));
 527         debug("LCCR3 = 0x%08x\n", readl(LCCR3));
 528 }
 529
 530 static int pxafb_init (vidinfo_t *vid)
 531 {
 532         struct pxafb_info *fbi = &vid->pxa;
 533
 534         debug("Configuring PXA LCD\n");
 535
 536         fbi->reg_lccr0 = REG_LCCR0;
 537         fbi->reg_lccr3 = REG_LCCR3;
 538
 539         debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
 540                 vid->vl_col, vid->vl_hpw,
 541                 vid->vl_blw, vid->vl_elw);
 542         debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
 543                 vid->vl_row, vid->vl_vpw,
 544                 vid->vl_bfw, vid->vl_efw);
 545
 546         fbi->reg_lccr1 =
 547                 LCCR1_DisWdth(vid->vl_col) +
 548                 LCCR1_HorSnchWdth(vid->vl_hpw) +
 549                 LCCR1_BegLnDel(vid->vl_blw) +
 550                 LCCR1_EndLnDel(vid->vl_elw);
 551
 552         fbi->reg_lccr2 =
 553                 LCCR2_DisHght(vid->vl_row) +
 554                 LCCR2_VrtSnchWdth(vid->vl_vpw) +
 555                 LCCR2_BegFrmDel(vid->vl_bfw) +
 556                 LCCR2_EndFrmDel(vid->vl_efw);
 557
 558         fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
 559         fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
 560                         | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
 561
 562
 563         /* setup dma descriptors */
 564         fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 565         fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 566         fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 567
 568         #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
 569                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
 570                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
 571
 572         /* populate descriptors */
 573         fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
 574         fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
 575         fbi->dmadesc_fblow->fidr  = 0;
 576         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 577
 578         fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
 579
 580         fbi->dmadesc_fbhigh->fsadr = fbi->screen;
 581         fbi->dmadesc_fbhigh->fidr = 0;
 582         fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
 583
 584         fbi->dmadesc_palette->fsadr = fbi->palette;
 585         fbi->dmadesc_palette->fidr  = 0;
 586         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 587
 588         if( NBITS(vid->vl_bpix) < 12)
 589         {
 590                 /* assume any mode with <12 bpp is palette driven */
 591                 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
 592                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
 593                 /* flips back and forth between pal and fbhigh */
 594                 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
 595         }
 596         else
 597         {
 598                 /* palette shouldn't be loaded in true-color mode */
 599                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
 600                 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
 601         }
 602
 603         debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
 604         debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
 605         debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
 606
 607         debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
 608         debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
 609         debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
 610
 611         debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
 612         debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
 613         debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
 614
 615         debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
 616         debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
 617         debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
 618
 619         return 0;
 620 }
 621
 622 /************************************************************************/
 623 /************************************************************************/
 624
 625 #endif /* CONFIG_LCD */