64acc88b7a7859131a7e3224b10fd2092384b872
[karo-tx-uboot.git] / include / configs / B4860QDS.h
1 /*
2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 /*
11  * B4860 QDS board configuration file
12  */
13 #define CONFIG_B4860QDS
14 #define CONFIG_PHYS_64BIT
15
16 #ifdef CONFIG_RAMBOOT_PBL
17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
19 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
20 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
21 #endif
22
23 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
24 /* Set 1M boot space */
25 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
26 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
27                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
28 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
29 #define CONFIG_SYS_NO_FLASH
30 #endif
31
32 /* High Level Configuration Options */
33 #define CONFIG_BOOKE
34 #define CONFIG_E500                     /* BOOKE e500 family */
35 #define CONFIG_E500MC                   /* BOOKE e500mc family */
36 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
37 #define CONFIG_MP                       /* support multiple processors */
38
39 #ifndef CONFIG_SYS_TEXT_BASE
40 #define CONFIG_SYS_TEXT_BASE    0xeff40000
41 #endif
42
43 #ifndef CONFIG_RESET_VECTOR_ADDRESS
44 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
45 #endif
46
47 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
48 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
49 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
50 #define CONFIG_PCI                      /* Enable PCI/PCIE */
51 #define CONFIG_PCIE1                    /* PCIE controler 1 */
52 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
53 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
54
55 #ifndef CONFIG_PPC_B4420
56 #define CONFIG_SYS_SRIO
57 #define CONFIG_SRIO1                    /* SRIO port 1 */
58 #define CONFIG_SRIO2                    /* SRIO port 2 */
59 #define CONFIG_SRIO_PCIE_BOOT_MASTER
60 #endif
61
62 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
63
64 /* I2C bus multiplexer */
65 #define I2C_MUX_PCA_ADDR                0x77
66
67 /* VSC Crossbar switches */
68 #define CONFIG_VSC_CROSSBAR
69 #define I2C_CH_DEFAULT                  0x8
70 #define I2C_CH_VSC3316                  0xc
71 #define I2C_CH_VSC3308                  0xd
72
73 #define VSC3316_TX_ADDRESS              0x70
74 #define VSC3316_RX_ADDRESS              0x71
75 #define VSC3308_TX_ADDRESS              0x02
76 #define VSC3308_RX_ADDRESS              0x03
77
78 /* IDT clock synthesizers */
79 #define CONFIG_IDT8T49N222A
80 #define I2C_CH_IDT                     0x9
81
82 #define IDT_SERDES1_ADDRESS            0x6E
83 #define IDT_SERDES2_ADDRESS            0x6C
84
85 #define CONFIG_ENV_OVERWRITE
86
87 #ifdef CONFIG_SYS_NO_FLASH
88 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
89 #define CONFIG_ENV_IS_NOWHERE
90 #endif
91 #else
92 #define CONFIG_FLASH_CFI_DRIVER
93 #define CONFIG_SYS_FLASH_CFI
94 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
95 #endif
96
97 #if defined(CONFIG_SPIFLASH)
98 #define CONFIG_SYS_EXTRA_ENV_RELOC
99 #define CONFIG_ENV_IS_IN_SPI_FLASH
100 #define CONFIG_ENV_SPI_BUS              0
101 #define CONFIG_ENV_SPI_CS               0
102 #define CONFIG_ENV_SPI_MAX_HZ           10000000
103 #define CONFIG_ENV_SPI_MODE             0
104 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
105 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
106 #define CONFIG_ENV_SECT_SIZE            0x10000
107 #elif defined(CONFIG_SDCARD)
108 #define CONFIG_SYS_EXTRA_ENV_RELOC
109 #define CONFIG_ENV_IS_IN_MMC
110 #define CONFIG_SYS_MMC_ENV_DEV          0
111 #define CONFIG_ENV_SIZE                 0x2000
112 #define CONFIG_ENV_OFFSET               (512 * 1097)
113 #elif defined(CONFIG_NAND)
114 #define CONFIG_SYS_EXTRA_ENV_RELOC
115 #define CONFIG_ENV_IS_IN_NAND
116 #define CONFIG_ENV_SIZE                 CONFIG_SYS_NAND_BLOCK_SIZE
117 #define CONFIG_ENV_OFFSET               (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
118 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
119 #define CONFIG_ENV_IS_IN_REMOTE
120 #define CONFIG_ENV_ADDR         0xffe20000
121 #define CONFIG_ENV_SIZE         0x2000
122 #elif defined(CONFIG_ENV_IS_NOWHERE)
123 #define CONFIG_ENV_SIZE         0x2000
124 #else
125 #define CONFIG_ENV_IS_IN_FLASH
126 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
127 #define CONFIG_ENV_SIZE         0x2000
128 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
129 #endif
130
131 #ifndef __ASSEMBLY__
132 unsigned long get_board_sys_clk(void);
133 unsigned long get_board_ddr_clk(void);
134 #endif
135 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
136 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
137
138 /*
139  * These can be toggled for performance analysis, otherwise use default.
140  */
141 #define CONFIG_SYS_CACHE_STASHING
142 #define CONFIG_BTB                      /* toggle branch predition */
143 #define CONFIG_DDR_ECC
144 #ifdef CONFIG_DDR_ECC
145 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
146 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
147 #endif
148
149 #define CONFIG_ENABLE_36BIT_PHYS
150
151 #ifdef CONFIG_PHYS_64BIT
152 #define CONFIG_ADDR_MAP
153 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
154 #endif
155
156 #if 0
157 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
158 #endif
159 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
160 #define CONFIG_SYS_MEMTEST_END          0x00400000
161 #define CONFIG_SYS_ALT_MEMTEST
162 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
163
164 /*
165  *  Config the L3 Cache as L3 SRAM
166  */
167 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
168
169 #ifdef CONFIG_PHYS_64BIT
170 #define CONFIG_SYS_DCSRBAR              0xf0000000
171 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
172 #endif
173
174 /* EEPROM */
175 #define CONFIG_SYS_I2C_EEPROM_NXID
176 #define CONFIG_SYS_EEPROM_BUS_NUM       0
177 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
178 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
179 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
181
182 /*
183  * DDR Setup
184  */
185 #define CONFIG_VERY_BIG_RAM
186 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
187 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
188
189 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
190 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
191 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
192
193 #define CONFIG_DDR_SPD
194 #define CONFIG_SYS_DDR_RAW_TIMING
195 #define CONFIG_SYS_FSL_DDR3
196 #define CONFIG_FSL_DDR_INTERACTIVE
197
198 #define CONFIG_SYS_SPD_BUS_NUM  0
199 #define SPD_EEPROM_ADDRESS1     0x51
200 #define SPD_EEPROM_ADDRESS2     0x53
201
202 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
203 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
204
205 /*
206  * IFC Definitions
207  */
208 #define CONFIG_SYS_FLASH_BASE   0xe0000000
209 #ifdef CONFIG_PHYS_64BIT
210 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
211 #else
212 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
213 #endif
214
215 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
216 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
217                                 + 0x8000000) | \
218                                 CSPR_PORT_SIZE_16 | \
219                                 CSPR_MSEL_NOR | \
220                                 CSPR_V)
221 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
222 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
223                                 CSPR_PORT_SIZE_16 | \
224                                 CSPR_MSEL_NOR | \
225                                 CSPR_V)
226 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
227 /* NOR Flash Timing Params */
228 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
229 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
230                                 FTIM0_NOR_TEADC(0x04) | \
231                                 FTIM0_NOR_TEAHC(0x20))
232 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
233                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
234                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
235 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
236                                 FTIM2_NOR_TCH(0x0E) | \
237                                 FTIM2_NOR_TWPH(0x0E) | \
238                                 FTIM2_NOR_TWP(0x1c))
239 #define CONFIG_SYS_NOR_FTIM3    0x0
240
241 #define CONFIG_SYS_FLASH_QUIET_TEST
242 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
243
244 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
245 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
246 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
247 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
248
249 #define CONFIG_SYS_FLASH_EMPTY_INFO
250 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
251                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
252
253 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
254 #define CONFIG_FSL_QIXIS_V2
255 #define QIXIS_BASE              0xffdf0000
256 #ifdef CONFIG_PHYS_64BIT
257 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
258 #else
259 #define QIXIS_BASE_PHYS         QIXIS_BASE
260 #endif
261 #define QIXIS_LBMAP_SWITCH              0x01
262 #define QIXIS_LBMAP_MASK                0x0f
263 #define QIXIS_LBMAP_SHIFT               0
264 #define QIXIS_LBMAP_DFLTBANK            0x00
265 #define QIXIS_LBMAP_ALTBANK             0x02
266 #define QIXIS_RST_CTL_RESET             0x31
267 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
268 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
269 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
270
271 #define CONFIG_SYS_CSPR3_EXT    (0xf)
272 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
273                                 | CSPR_PORT_SIZE_8 \
274                                 | CSPR_MSEL_GPCM \
275                                 | CSPR_V)
276 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
277 #define CONFIG_SYS_CSOR3        0x0
278 /* QIXIS Timing parameters for IFC CS3 */
279 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
280                                         FTIM0_GPCM_TEADC(0x0e) | \
281                                         FTIM0_GPCM_TEAHC(0x0e))
282 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
283                                         FTIM1_GPCM_TRAD(0x1f))
284 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
285                                         FTIM2_GPCM_TCH(0x0) | \
286                                         FTIM2_GPCM_TWP(0x1f))
287 #define CONFIG_SYS_CS3_FTIM3            0x0
288
289 /* NAND Flash on IFC */
290 #define CONFIG_NAND_FSL_IFC
291 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
292 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
293 #define CONFIG_SYS_NAND_BASE            0xff800000
294 #ifdef CONFIG_PHYS_64BIT
295 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
296 #else
297 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
298 #endif
299
300 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
301 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
302                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
303                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
304                                 | CSPR_V)
305 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
306
307 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
308                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
309                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
310                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
311                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
312                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
313                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
314
315 #define CONFIG_SYS_NAND_ONFI_DETECTION
316
317 /* ONFI NAND Flash mode0 Timing Params */
318 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
319                                         FTIM0_NAND_TWP(0x18)   | \
320                                         FTIM0_NAND_TWCHT(0x07) | \
321                                         FTIM0_NAND_TWH(0x0a))
322 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
323                                         FTIM1_NAND_TWBE(0x39)  | \
324                                         FTIM1_NAND_TRR(0x0e)   | \
325                                         FTIM1_NAND_TRP(0x18))
326 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
327                                         FTIM2_NAND_TREH(0x0a) | \
328                                         FTIM2_NAND_TWHRE(0x1e))
329 #define CONFIG_SYS_NAND_FTIM3           0x0
330
331 #define CONFIG_SYS_NAND_DDR_LAW         11
332
333 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
334 #define CONFIG_SYS_MAX_NAND_DEVICE      1
335 #define CONFIG_MTD_NAND_VERIFY_WRITE
336 #define CONFIG_CMD_NAND
337
338 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
339
340 #if defined(CONFIG_NAND)
341 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
342 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
343 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
344 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
345 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
346 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
347 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
348 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
349 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
350 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
351 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
352 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
353 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
354 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
355 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
356 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
357 #else
358 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
359 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
360 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
361 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
362 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
363 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
364 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
365 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
366 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
367 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
368 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
369 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
370 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
371 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
372 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
373 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
374 #endif
375 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
376 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
377 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
378 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
379 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
380 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
381 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
382 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
383
384 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
385
386 #if defined(CONFIG_RAMBOOT_PBL)
387 #define CONFIG_SYS_RAMBOOT
388 #endif
389
390 #define CONFIG_BOARD_EARLY_INIT_R
391 #define CONFIG_MISC_INIT_R
392
393 #define CONFIG_HWCONFIG
394
395 /* define to use L1 as initial stack */
396 #define CONFIG_L1_INIT_RAM
397 #define CONFIG_SYS_INIT_RAM_LOCK
398 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
399 #ifdef CONFIG_PHYS_64BIT
400 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
401 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
402 /* The assembler doesn't like typecast */
403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
404         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
405           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
406 #else
407 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe0ec000 /* Initial L1 address */
408 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
409 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
410 #endif
411 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
412
413 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
414                                         GENERATED_GBL_DATA_SIZE)
415 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
416
417 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
418 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
419
420 /* Serial Port - controlled on board with jumper J8
421  * open - index 2
422  * shorted - index 1
423  */
424 #define CONFIG_CONS_INDEX       1
425 #define CONFIG_SYS_NS16550
426 #define CONFIG_SYS_NS16550_SERIAL
427 #define CONFIG_SYS_NS16550_REG_SIZE     1
428 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
429
430 #define CONFIG_SYS_BAUDRATE_TABLE       \
431         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
432
433 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
434 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
435 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
436 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
437 #define CONFIG_SERIAL_MULTI             /* Enable both serial ports */
438 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
439
440
441 /* Use the HUSH parser */
442 #define CONFIG_SYS_HUSH_PARSER
443 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
444
445 /* pass open firmware flat tree */
446 #define CONFIG_OF_LIBFDT
447 #define CONFIG_OF_BOARD_SETUP
448 #define CONFIG_OF_STDOUT_VIA_ALIAS
449
450 /* new uImage format support */
451 #define CONFIG_FIT
452 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
453
454 /* I2C */
455 #define CONFIG_SYS_I2C
456 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
457 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
458 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
459 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
460 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
461 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
462 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
463
464 /*
465  * RTC configuration
466  */
467 #define RTC
468 #define CONFIG_RTC_DS3231               1
469 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
470
471 /*
472  * RapidIO
473  */
474 #ifdef CONFIG_SYS_SRIO
475 #ifdef CONFIG_SRIO1
476 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
477 #ifdef CONFIG_PHYS_64BIT
478 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
479 #else
480 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
481 #endif
482 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
483 #endif
484
485 #ifdef CONFIG_SRIO2
486 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
487 #ifdef CONFIG_PHYS_64BIT
488 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
489 #else
490 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
491 #endif
492 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
493 #endif
494 #endif
495
496 /*
497  * for slave u-boot IMAGE instored in master memory space,
498  * PHYS must be aligned based on the SIZE
499  */
500 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
501 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
502 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000        /* 512K */
503 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
504 /*
505  * for slave UCODE and ENV instored in master memory space,
506  * PHYS must be aligned based on the SIZE
507  */
508 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
509 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
510 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
511
512 /* slave core release by master*/
513 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
514 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
515
516 /*
517  * SRIO_PCIE_BOOT - SLAVE
518  */
519 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
520 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
521 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
522                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
523 #endif
524
525 /*
526  * eSPI - Enhanced SPI
527  */
528 #define CONFIG_FSL_ESPI
529 #define CONFIG_SPI_FLASH
530 #define CONFIG_SPI_FLASH_SST
531 #define CONFIG_CMD_SF
532 #define CONFIG_SF_DEFAULT_SPEED         10000000
533 #define CONFIG_SF_DEFAULT_MODE          0
534
535 /*
536  * MAPLE
537  */
538 #ifdef CONFIG_PHYS_64BIT
539 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
540 #else
541 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
542 #endif
543
544 /*
545  * General PCI
546  * Memory space is mapped 1-1, but I/O space must start from 0.
547  */
548
549 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
550 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
551 #ifdef CONFIG_PHYS_64BIT
552 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
553 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
554 #else
555 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
556 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
557 #endif
558 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
559 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
560 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
561 #ifdef CONFIG_PHYS_64BIT
562 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
563 #else
564 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
565 #endif
566 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
567
568 /* Qman/Bman */
569 #ifndef CONFIG_NOBQFMAN
570 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
571 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
572 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
573 #ifdef CONFIG_PHYS_64BIT
574 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
575 #else
576 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
577 #endif
578 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
579 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
580 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
581 #ifdef CONFIG_PHYS_64BIT
582 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
583 #else
584 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
585 #endif
586 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
587
588 #define CONFIG_SYS_DPAA_FMAN
589
590 #define CONFIG_SYS_DPAA_RMAN
591
592 /* Default address of microcode for the Linux Fman driver */
593 #if defined(CONFIG_SPIFLASH)
594 /*
595  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
596  * env, so we got 0x110000.
597  */
598 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
599 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0x110000
600 #elif defined(CONFIG_SDCARD)
601 /*
602  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
603  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
604  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
605  */
606 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
607 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (512 * 1130)
608 #elif defined(CONFIG_NAND)
609 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
610 #define CONFIG_SYS_QE_FMAN_FW_ADDR      (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
611 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
612 /*
613  * Slave has no ucode locally, it can fetch this from remote. When implementing
614  * in two corenet boards, slave's ucode could be stored in master's memory
615  * space, the address can be mapped from slave TLB->slave LAW->
616  * slave SRIO or PCIE outbound window->master inbound window->
617  * master LAW->the ucode address in master's memory space.
618  */
619 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
620 #define CONFIG_SYS_QE_FMAN_FW_ADDR      0xFFE00000
621 #else
622 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
623 #define CONFIG_SYS_QE_FMAN_FW_ADDR              0xEFF00000
624 #endif
625 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
626 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
627 #endif /* CONFIG_NOBQFMAN */
628
629 #ifdef CONFIG_SYS_DPAA_FMAN
630 #define CONFIG_FMAN_ENET
631 #define CONFIG_PHYLIB_10G
632 #define CONFIG_PHY_VITESSE
633 #define CONFIG_PHY_TERANETICS
634 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
635 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
636 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
637 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
638 #endif
639
640 #ifdef CONFIG_PCI
641 #define CONFIG_PCI_INDIRECT_BRIDGE
642 #define CONFIG_NET_MULTI
643 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
644 #define CONFIG_E1000
645
646 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
647 #define CONFIG_DOS_PARTITION
648 #endif  /* CONFIG_PCI */
649
650 #ifdef CONFIG_FMAN_ENET
651 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x10
652 #define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR  0x11
653
654 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
655 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
656 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
657
658
659 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
660 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
661 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
662 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
663
664 #define CONFIG_MII              /* MII PHY management */
665 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
666 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
667 #endif
668
669 /*
670  * Environment
671  */
672 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
673 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
674
675 /*
676  * Command line configuration.
677  */
678 #include <config_cmd_default.h>
679
680 #define CONFIG_CMD_DATE
681 #define CONFIG_CMD_DHCP
682 #define CONFIG_CMD_EEPROM
683 #define CONFIG_CMD_ELF
684 #define CONFIG_CMD_ERRATA
685 #define CONFIG_CMD_GREPENV
686 #define CONFIG_CMD_IRQ
687 #define CONFIG_CMD_I2C
688 #define CONFIG_CMD_MII
689 #define CONFIG_CMD_PING
690 #define CONFIG_CMD_REGINFO
691 #define CONFIG_CMD_SETEXPR
692
693 #ifdef CONFIG_PCI
694 #define CONFIG_CMD_PCI
695 #define CONFIG_CMD_NET
696 #endif
697
698 /*
699 * USB
700 */
701 #define CONFIG_HAS_FSL_DR_USB
702
703 #ifdef CONFIG_HAS_FSL_DR_USB
704 #define CONFIG_USB_EHCI
705
706 #ifdef CONFIG_USB_EHCI
707 #define CONFIG_CMD_USB
708 #define CONFIG_USB_STORAGE
709 #define CONFIG_USB_EHCI_FSL
710 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
711 #define CONFIG_CMD_EXT2
712 #endif
713 #endif
714
715 /*
716  * Miscellaneous configurable options
717  */
718 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
719 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
720 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
721 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
722 #ifdef CONFIG_CMD_KGDB
723 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
724 #else
725 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
726 #endif
727 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
728 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
729 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
730
731 /*
732  * For booting Linux, the board info and command line data
733  * have to be in the first 64 MB of memory, since this is
734  * the maximum mapped by the Linux kernel during initialization.
735  */
736 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
737 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
738
739 #ifdef CONFIG_CMD_KGDB
740 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
741 #endif
742
743 /*
744  * Environment Configuration
745  */
746 #define CONFIG_ROOTPATH         "/opt/nfsroot"
747 #define CONFIG_BOOTFILE         "uImage"
748 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
749
750 /* default location for tftp and bootm */
751 #define CONFIG_LOADADDR         1000000
752
753 #define CONFIG_BOOTDELAY        10      /* -1 disables auto-boot */
754
755 #define CONFIG_BAUDRATE 115200
756
757 #define __USB_PHY_TYPE  ulpi
758
759 #define CONFIG_EXTRA_ENV_SETTINGS                               \
760         "hwconfig=fsl_ddr:ctlr_intlv=null,"             \
761         "bank_intlv=cs0_cs1;"                                   \
762         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
763         "netdev=eth0\0"                                         \
764         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
765         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
766         "tftpflash=tftpboot $loadaddr $uboot && "               \
767         "protect off $ubootaddr +$filesize && "                 \
768         "erase $ubootaddr +$filesize && "                       \
769         "cp.b $loadaddr $ubootaddr $filesize && "               \
770         "protect on $ubootaddr +$filesize && "                  \
771         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
772         "consoledev=ttyS0\0"                                    \
773         "ramdiskaddr=2000000\0"                                 \
774         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
775         "fdtaddr=c00000\0"                                      \
776         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
777         "bdev=sda3\0"                                           \
778         "c=ffe\0"
779
780 /* For emulation this causes u-boot to jump to the start of the proof point
781    app code automatically */
782 #define CONFIG_PROOF_POINTS                     \
783  "setenv bootargs root=/dev/$bdev rw "          \
784  "console=$consoledev,$baudrate $othbootargs;"  \
785  "cpu 1 release 0x29000000 - - -;"              \
786  "cpu 2 release 0x29000000 - - -;"              \
787  "cpu 3 release 0x29000000 - - -;"              \
788  "cpu 4 release 0x29000000 - - -;"              \
789  "cpu 5 release 0x29000000 - - -;"              \
790  "cpu 6 release 0x29000000 - - -;"              \
791  "cpu 7 release 0x29000000 - - -;"              \
792  "go 0x29000000"
793
794 #define CONFIG_HVBOOT   \
795  "setenv bootargs config-addr=0x60000000; "     \
796  "bootm 0x01000000 - 0x00f00000"
797
798 #define CONFIG_ALU                              \
799  "setenv bootargs root=/dev/$bdev rw "          \
800  "console=$consoledev,$baudrate $othbootargs;"  \
801  "cpu 1 release 0x01000000 - - -;"              \
802  "cpu 2 release 0x01000000 - - -;"              \
803  "cpu 3 release 0x01000000 - - -;"              \
804  "cpu 4 release 0x01000000 - - -;"              \
805  "cpu 5 release 0x01000000 - - -;"              \
806  "cpu 6 release 0x01000000 - - -;"              \
807  "cpu 7 release 0x01000000 - - -;"              \
808  "go 0x01000000"
809
810 #define CONFIG_LINUX                            \
811  "setenv bootargs root=/dev/ram rw "            \
812  "console=$consoledev,$baudrate $othbootargs;"  \
813  "setenv ramdiskaddr 0x02000000;"               \
814  "setenv fdtaddr 0x00c00000;"                   \
815  "setenv loadaddr 0x1000000;"                   \
816  "bootm $loadaddr $ramdiskaddr $fdtaddr"
817
818 #define CONFIG_HDBOOT                                   \
819         "setenv bootargs root=/dev/$bdev rw "           \
820         "console=$consoledev,$baudrate $othbootargs;"   \
821         "tftp $loadaddr $bootfile;"                     \
822         "tftp $fdtaddr $fdtfile;"                       \
823         "bootm $loadaddr - $fdtaddr"
824
825 #define CONFIG_NFSBOOTCOMMAND                   \
826         "setenv bootargs root=/dev/nfs rw "     \
827         "nfsroot=$serverip:$rootpath "          \
828         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
829         "console=$consoledev,$baudrate $othbootargs;"   \
830         "tftp $loadaddr $bootfile;"             \
831         "tftp $fdtaddr $fdtfile;"               \
832         "bootm $loadaddr - $fdtaddr"
833
834 #define CONFIG_RAMBOOTCOMMAND                           \
835         "setenv bootargs root=/dev/ram rw "             \
836         "console=$consoledev,$baudrate $othbootargs;"   \
837         "tftp $ramdiskaddr $ramdiskfile;"               \
838         "tftp $loadaddr $bootfile;"                     \
839         "tftp $fdtaddr $fdtfile;"                       \
840         "bootm $loadaddr $ramdiskaddr $fdtaddr"
841
842 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
843
844 #include <asm/fsl_secure_boot.h>
845
846 #endif  /* __CONFIG_H */