include/configs/BSC9132QDS.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * BSC9132 QDS board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #ifdef CONFIG_BSC9132QDS
  31 #define CONFIG_BSC9132
  32 #endif
  33
  34 #define CONFIG_MISC_INIT_R
  35
  36 #ifdef CONFIG_SDCARD
  37 #define CONFIG_RAMBOOT_SDCARD
  38 #define CONFIG_SYS_RAMBOOT
  39 #define CONFIG_SYS_EXTRA_ENV_RELOC
  40 #define CONFIG_SYS_TEXT_BASE            0x11000000
  41 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  42 #endif
  43 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769      1
  44 #ifdef CONFIG_SPIFLASH
  45 #define CONFIG_RAMBOOT_SPIFLASH
  46 #define CONFIG_SYS_RAMBOOT
  47 #define CONFIG_SYS_EXTRA_ENV_RELOC
  48 #define CONFIG_SYS_TEXT_BASE            0x11000000
  49 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  50 #endif
  51
  52 #ifndef CONFIG_SYS_TEXT_BASE
  53 #define CONFIG_SYS_TEXT_BASE            0x8ff80000
  54 #endif
  55
  56 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  57 #define CONFIG_RESET_VECTOR_ADDRESS     0x8ffffffc
  58 #endif
  59
  60 #ifndef CONFIG_SYS_MONITOR_BASE
  61 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  62 #endif
  63
  64
  65 /* High Level Configuration Options */
  66 #define CONFIG_BOOKE                    /* BOOKE */
  67 #define CONFIG_E500                     /* BOOKE e500 family */
  68 #define CONFIG_MPC85xx
  69 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  70 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
  71
  72 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  73 #if defined(CONFIG_PCI)
  74 #define CONFIG_PCIE1                    /* PCIE controler 1 (slot 1) */
  75 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  76 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  77 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  78
  79 #define CONFIG_CMD_NET
  80 #define CONFIG_CMD_PCI
  81
  82 #define CONFIG_E1000                    /*  E1000 pci Ethernet card*/
  83
  84 /*
  85  * PCI Windows
  86  * Memory space is mapped 1-1, but I/O space must start from 0.
  87  */
  88 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  89 #define CONFIG_SYS_PCIE1_NAME           "PCIe Slot"
  90 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
  91 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
  92 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
  93 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
  94 #define CONFIG_SYS_PCIE1_IO_VIRT        0xC0010000
  95 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
  96 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
  97 #define CONFIG_SYS_PCIE1_IO_PHYS        0xC0010000
  98
  99 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 100
 101 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 102 #define CONFIG_DOS_PARTITION
 103 #endif
 104
 105 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 106 #define CONFIG_ENV_OVERWRITE
 107 #define CONFIG_TSEC_ENET /* ethernet */
 108
 109 #if defined(CONFIG_SYS_CLK_100_DDR_100)
 110 #define CONFIG_SYS_CLK_FREQ     100000000
 111 #define CONFIG_DDR_CLK_FREQ     100000000
 112 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
 113 #define CONFIG_SYS_CLK_FREQ     100000000
 114 #define CONFIG_DDR_CLK_FREQ     133000000
 115 #endif
 116
 117 #define CONFIG_MP
 118
 119 #define CONFIG_HWCONFIG
 120 /*
 121  * These can be toggled for performance analysis, otherwise use default.
 122  */
 123 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 124 #define CONFIG_BTB                      /* enable branch predition */
 125
 126 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
 127 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
 128
 129 /* DDR Setup */
 130 #define CONFIG_FSL_DDR3
 131 #define CONFIG_SYS_SPD_BUS_NUM          0
 132 #define SPD_EEPROM_ADDRESS1             0x54 /* I2C access */
 133 #define SPD_EEPROM_ADDRESS2             0x56 /* I2C access */
 134 #define CONFIG_FSL_DDR_INTERACTIVE
 135
 136 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 137
 138 #define CONFIG_SYS_SDRAM_SIZE           (1024)
 139 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 140 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 141
 142 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 143
 144 /* DDR3 Controller Settings */
 145 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 146 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 147 #define CONFIG_SYS_DDR_CS0_CONFIG_1333  0x80004302
 148 #define CONFIG_SYS_DDR_CS0_CONFIG_800   0x80014302
 149 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 150 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 151 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 152 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 153 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 154 #define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
 155
 156 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 157 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 158 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 159 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 160 #define CONFIG_SYS_DDR_CONTROL_800              0x470C0000
 161 #define CONFIG_SYS_DDR_CONTROL_2_800    0x04401050
 162 #define CONFIG_SYS_DDR_TIMING_4_800             0x00220001
 163 #define CONFIG_SYS_DDR_TIMING_5_800             0x03402400
 164
 165 #define CONFIG_SYS_DDR_CONTROL_1333             0x470C0008
 166 #define CONFIG_SYS_DDR_CONTROL_2_1333   0x24401010
 167 #define CONFIG_SYS_DDR_TIMING_4_1333            0x00000001
 168 #define CONFIG_SYS_DDR_TIMING_5_1333            0x03401400
 169
 170 #define CONFIG_SYS_DDR_TIMING_3_800             0x00020000
 171 #define CONFIG_SYS_DDR_TIMING_0_800             0x00330004
 172 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6B4846
 173 #define CONFIG_SYS_DDR_TIMING_2_800             0x0FA8C8CF
 174 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
 175 #define CONFIG_SYS_DDR_MODE_1_800               0x40461520
 176 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
 177 #define CONFIG_SYS_DDR_INTERVAL_800             0x0C300000
 178 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8655A608
 179
 180 #define CONFIG_SYS_DDR_TIMING_3_1333            0x01061000
 181 #define CONFIG_SYS_DDR_TIMING_0_1333            0x00440104
 182 #define CONFIG_SYS_DDR_TIMING_1_1333            0x98913A45
 183 #define CONFIG_SYS_DDR_TIMING_2_1333            0x0FB8B114
 184 #define CONFIG_SYS_DDR_CLK_CTRL_1333            0x02800000
 185 #define CONFIG_SYS_DDR_MODE_1_1333              0x00061A50
 186 #define CONFIG_SYS_DDR_MODE_2_1333              0x00100000
 187 #define CONFIG_SYS_DDR_INTERVAL_1333            0x144E0513
 188 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333       0x8655F607
 189
 190 /*FIXME: the following params are constant w.r.t diff freq
 191 combinations. this should be removed later
 192 */
 193 #if CONFIG_DDR_CLK_FREQ == 100000000
 194 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
 195 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
 196 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
 197 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
 198 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
 199 #elif CONFIG_DDR_CLK_FREQ == 133000000
 200 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
 201 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_1333
 202 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_1333
 203 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
 204 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
 205 #else
 206 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
 207 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
 208 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_800
 209 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
 210 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
 211 #endif
 212
 213
 214 /* relocated CCSRBAR */
 215 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
 216 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
 217
 218 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
 219
 220 /*
 221  * IFC Definitions
 222  */
 223 /* NOR Flash on IFC */
 224 #define CONFIG_SYS_FLASH_BASE           0x88000000
 225 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* Max number of sector: 32M */
 226
 227 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 228
 229 #define CONFIG_SYS_NOR_CSPR     0x88000101
 230 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 231 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(5)
 232 /* NOR Flash Timing Params */
 233
 234 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) \
 235                                 | FTIM0_NOR_TEADC(0x03) \
 236                                 | FTIM0_NOR_TAVDS(0x00) \
 237                                 | FTIM0_NOR_TEAHC(0x0f))
 238 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1d) \
 239                                 | FTIM1_NOR_TRAD_NOR(0x09) \
 240                                 | FTIM1_NOR_TSEQRAD_NOR(0x09))
 241 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x1) \
 242                                 | FTIM2_NOR_TCH(0x4) \
 243                                 | FTIM2_NOR_TWPH(0x7) \
 244                                 | FTIM2_NOR_TWP(0x1e))
 245 #define CONFIG_SYS_NOR_FTIM3    0x0
 246
 247 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 248 #define CONFIG_SYS_FLASH_QUIET_TEST
 249 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 250 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 251
 252 #undef CONFIG_SYS_FLASH_CHECKSUM
 253 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 254 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 255
 256 /* CFI for NOR Flash */
 257 #define CONFIG_FLASH_CFI_DRIVER
 258 #define CONFIG_SYS_FLASH_CFI
 259 #define CONFIG_SYS_FLASH_EMPTY_INFO
 260 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 261
 262 /* NAND Flash on IFC */
 263 #define CONFIG_SYS_NAND_BASE            0xff800000
 264 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 265
 266 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 267                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 268                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 269                                 | CSPR_V)
 270 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 271
 272 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 273                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 274                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 275                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
 276                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 277                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 278                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 279
 280 /* NAND Flash Timing Params */
 281 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03) \
 282                                         | FTIM0_NAND_TWP(0x05) \
 283                                         | FTIM0_NAND_TWCHT(0x02) \
 284                                         | FTIM0_NAND_TWH(0x04))
 285 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1c) \
 286                                         | FTIM1_NAND_TWBE(0x1e) \
 287                                         | FTIM1_NAND_TRR(0x07) \
 288                                         | FTIM1_NAND_TRP(0x05))
 289 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08) \
 290                                         | FTIM2_NAND_TREH(0x04) \
 291                                         | FTIM2_NAND_TWHRE(0x11))
 292 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 293
 294 #define CONFIG_SYS_NAND_DDR_LAW         11
 295
 296 /* NAND */
 297 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 298 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 299 #define CONFIG_MTD_NAND_VERIFY_WRITE
 300 #define CONFIG_CMD_NAND
 301
 302 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 303
 304 #define CONFIG_FSL_QIXIS
 305 #ifdef CONFIG_FSL_QIXIS
 306 #define CONFIG_SYS_FPGA_BASE    0xffb00000
 307 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 308 #define QIXIS_BASE      CONFIG_SYS_FPGA_BASE
 309 #define QIXIS_LBMAP_SWITCH      9
 310 #define QIXIS_LBMAP_MASK        0x07
 311 #define QIXIS_LBMAP_SHIFT       0
 312 #define QIXIS_LBMAP_DFLTBANK            0x00
 313 #define QIXIS_LBMAP_ALTBANK             0x04
 314 #define QIXIS_RST_CTL_RESET             0x83
 315 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 316 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 317 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 318
 319 #define CONFIG_SYS_FPGA_BASE_PHYS       CONFIG_SYS_FPGA_BASE
 320
 321 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
 322                                         | CSPR_PORT_SIZE_8 \
 323                                         | CSPR_MSEL_GPCM \
 324                                         | CSPR_V)
 325 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 326 #define CONFIG_SYS_CSOR2                0x0
 327 /* CPLD Timing parameters for IFC CS3 */
 328 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 329                                         FTIM0_GPCM_TEADC(0x0e) | \
 330                                         FTIM0_GPCM_TEAHC(0x0e))
 331 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 332                                         FTIM1_GPCM_TRAD(0x1f))
 333 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 334                                         FTIM2_GPCM_TCH(0x0) | \
 335                                         FTIM2_GPCM_TWP(0x1f))
 336 #define CONFIG_SYS_CS2_FTIM3            0x0
 337 #endif
 338
 339 /* Set up IFC registers for boot location NOR/NAND */
 340 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 341 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 342 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 343 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 344 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 345 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 346 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 347 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 348 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 349 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 350 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 351 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 352 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 353 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 354
 355 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 356 #define CONFIG_BOARD_EARLY_INIT_R
 357
 358 #define CONFIG_SYS_INIT_RAM_LOCK
 359 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
 360 #define CONFIG_SYS_INIT_RAM_END         0x00004000 /* End of used area in RAM */
 361
 362 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END \
 363                                                 - GENERATED_GBL_DATA_SIZE)
 364 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 365
 366 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 367 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 368
 369 /* Serial Port */
 370 #define CONFIG_CONS_INDEX       1
 371 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 372 #define CONFIG_SYS_NS16550
 373 #define CONFIG_SYS_NS16550_SERIAL
 374 #define CONFIG_SYS_NS16550_REG_SIZE     1
 375 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 376
 377 #define CONFIG_SERIAL_MULTI     1 /* Enable both serial ports */
 378 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 379
 380 #define CONFIG_SYS_BAUDRATE_TABLE       \
 381         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 382
 383 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 384 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 385 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
 386 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
 387
 388 /* Use the HUSH parser */
 389 #define CONFIG_SYS_HUSH_PARSER    /* hush parser */
 390 #ifdef  CONFIG_SYS_HUSH_PARSER
 391 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 392 #endif
 393
 394 /*
 395  * Pass open firmware flat tree
 396  */
 397 #define CONFIG_OF_LIBFDT
 398 #define CONFIG_OF_BOARD_SETUP
 399 #define CONFIG_OF_STDOUT_VIA_ALIAS
 400
 401 /* new uImage format support */
 402 #define CONFIG_FIT
 403 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 404
 405 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver */
 406 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 407 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 408 #define CONFIG_I2C_MULTI_BUS
 409 #define CONFIG_I2C_CMD_TREE
 410 #define CONFIG_SYS_I2C_SPEED            400800 /* I2C speed and slave address*/
 411 #define CONFIG_SYS_I2C_SLAVE            0x7F
 412 #define CONFIG_SYS_I2C_OFFSET           0x3000
 413 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 414
 415 /* I2C EEPROM */
 416 #define CONFIG_ID_EEPROM
 417 #ifdef CONFIG_ID_EEPROM
 418 #define CONFIG_SYS_I2C_EEPROM_NXID
 419 #endif
 420 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 421 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 422 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 423
 424 /* enable read and write access to EEPROM */
 425 #define CONFIG_CMD_EEPROM
 426 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 427 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 428 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 429 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 430
 431 /* I2C FPGA */
 432 #define CONFIG_I2C_FPGA
 433 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 434
 435 #define CONFIG_RTC_DS3231
 436 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 437
 438 /*
 439  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 440  * used for SLIC
 441  */
 442 /* eSPI - Enhanced SPI */
 443 #define CONFIG_FSL_ESPI  /* SPI */
 444 #ifdef CONFIG_FSL_ESPI
 445 #define CONFIG_SPI_FLASH
 446 #define CONFIG_SPI_FLASH_SPANSION
 447 #define CONFIG_CMD_SF
 448 #define CONFIG_SF_DEFAULT_SPEED         10000000
 449 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 450 #endif
 451
 452 #if defined(CONFIG_TSEC_ENET)
 453
 454 #define CONFIG_MII                      /* MII PHY management */
 455 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 456 #define CONFIG_TSEC1    1
 457 #define CONFIG_TSEC1_NAME       "eTSEC1"
 458 #define CONFIG_TSEC2    1
 459 #define CONFIG_TSEC2_NAME       "eTSEC2"
 460
 461 #define TSEC1_PHY_ADDR          0
 462 #define TSEC2_PHY_ADDR          1
 463
 464 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 465 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 466
 467 #define TSEC1_PHYIDX            0
 468 #define TSEC2_PHYIDX            0
 469
 470 #define CONFIG_ETHPRIME         "eTSEC1"
 471
 472 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 473
 474 /* TBI PHY configuration for SGMII mode */
 475 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 476                 TBICR_PHY_RESET \
 477                 | TBICR_ANEG_ENABLE \
 478                 | TBICR_FULL_DUPLEX \
 479                 | TBICR_SPEED1_SET \
 480                 )
 481
 482 #endif  /* CONFIG_TSEC_ENET */
 483
 484 #define CONFIG_MMC
 485 #ifdef CONFIG_MMC
 486 #define CONFIG_CMD_MMC
 487 #define CONFIG_DOS_PARTITION
 488 #define CONFIG_FSL_ESDHC
 489 #define CONFIG_GENERIC_MMC
 490 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 491 #endif
 492
 493 #define CONFIG_USB_EHCI  /* USB */
 494 #ifdef CONFIG_USB_EHCI
 495 #define CONFIG_CMD_USB
 496 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 497 #define CONFIG_USB_EHCI_FSL
 498 #define CONFIG_USB_STORAGE
 499 #define CONFIG_HAS_FSL_DR_USB
 500 #endif
 501
 502 /*
 503  * Environment
 504  */
 505 #if defined(CONFIG_SYS_RAMBOOT)
 506 #if defined(CONFIG_RAMBOOT_SDCARD)
 507 #define CONFIG_ENV_IS_IN_MMC
 508 #define CONFIG_SYS_MMC_ENV_DEV          0
 509 #define CONFIG_ENV_SIZE                 0x2000
 510 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 511 #define CONFIG_ENV_IS_IN_SPI_FLASH
 512 #define CONFIG_ENV_SPI_BUS      0
 513 #define CONFIG_ENV_SPI_CS       0
 514 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 515 #define CONFIG_ENV_SPI_MODE     0
 516 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 517 #define CONFIG_ENV_SECT_SIZE    0x10000
 518 #define CONFIG_ENV_SIZE         0x2000
 519 #else
 520 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 521 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 522 #define CONFIG_ENV_SIZE                 0x2000
 523 #endif
 524 #else
 525 #define CONFIG_ENV_IS_IN_FLASH
 526 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
 527 #define CONFIG_ENV_ADDR 0xfff80000
 528 #else
 529 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 530 #endif
 531 #define CONFIG_ENV_SIZE         0x2000
 532 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 533 #endif
 534
 535 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 536 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 537
 538 /*
 539  * Command line configuration.
 540  */
 541 #include <config_cmd_default.h>
 542
 543 #define CONFIG_CMD_DATE
 544 #define CONFIG_CMD_DHCP
 545 #define CONFIG_CMD_ELF
 546 #define CONFIG_CMD_ERRATA
 547 #define CONFIG_CMD_I2C
 548 #define CONFIG_CMD_IRQ
 549 #define CONFIG_CMD_MII
 550 #define CONFIG_CMD_PING
 551 #define CONFIG_CMD_SETEXPR
 552 #define CONFIG_CMD_REGINFO
 553
 554 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 555 #define CONFIG_CMD_EXT2
 556 #define CONFIG_CMD_FAT
 557 #define CONFIG_DOS_PARTITION
 558 #endif
 559
 560 /*
 561  * Miscellaneous configurable options
 562  */
 563 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 564 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 565 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 566 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 567 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 568
 569 #if defined(CONFIG_CMD_KGDB)
 570 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 571 #else
 572 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 573 #endif
 574 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 575                                                 /* Print Buffer Size */
 576 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 577 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 578 #define CONFIG_SYS_HZ           1000            /* decrementer freq:1ms ticks */
 579
 580
 581 /*
 582  * For booting Linux, the board info and command line data
 583  * have to be in the first 64 MB of memory, since this is
 584  * the maximum mapped by the Linux kernel during initialization.
 585  */
 586 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 587 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 588
 589 #if defined(CONFIG_CMD_KGDB)
 590 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 591 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 592 #endif
 593
 594 /*
 595  * Environment Configuration
 596  */
 597
 598 #if defined(CONFIG_TSEC_ENET)
 599 #define CONFIG_HAS_ETH0
 600 #define CONFIG_HAS_ETH1
 601 #endif
 602
 603 #define CONFIG_HOSTNAME         BSC9132qds
 604 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 605 #define CONFIG_BOOTFILE         "uImage"
 606 #define CONFIG_UBOOTPATH        "u-boot.bin"
 607
 608 #define CONFIG_BAUDRATE         115200
 609
 610 #ifdef CONFIG_SDCARD
 611 #define CONFIG_DEF_HWCONFIG     "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 612 #else
 613 #define CONFIG_DEF_HWCONFIG     "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
 614 #endif
 615
 616 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 617         "netdev=eth0\0"                                         \
 618         "uboot=" CONFIG_UBOOTPATH "\0"                          \
 619         "loadaddr=1000000\0"                    \
 620         "bootfile=uImage\0"     \
 621         "consoledev=ttyS0\0"                            \
 622         "ramdiskaddr=2000000\0"                 \
 623         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 624         "fdtaddr=c00000\0"                              \
 625         "fdtfile=bsc9132qds.dtb\0"              \
 626         "bdev=sda1\0"   \
 627         CONFIG_DEF_HWCONFIG\
 628         "othbootargs=mem=880M ramdisk_size=600000 " \
 629                 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
 630                 "isolcpus=0\0" \
 631         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 632                 "console=$consoledev,$baudrate $othbootargs; "  \
 633                 "usb start;"                    \
 634                 "ext2load usb 0:4 $loadaddr $bootfile;"         \
 635                 "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 636                 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 637                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 638         "debug_halt_off=mw ff7e0e30 0xf0000000;"
 639
 640 #define CONFIG_NFSBOOTCOMMAND   \
 641         "setenv bootargs root=/dev/nfs rw "     \
 642         "nfsroot=$serverip:$rootpath "  \
 643         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 644         "console=$consoledev,$baudrate $othbootargs;" \
 645         "tftp $loadaddr $bootfile;"     \
 646         "tftp $fdtaddr $fdtfile;"       \
 647         "bootm $loadaddr - $fdtaddr"
 648
 649 #define CONFIG_HDBOOT   \
 650         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 651         "console=$consoledev,$baudrate $othbootargs;" \
 652         "usb start;"    \
 653         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 654         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 655         "bootm $loadaddr - $fdtaddr"
 656
 657 #define CONFIG_RAMBOOTCOMMAND           \
 658         "setenv bootargs root=/dev/ram rw "     \
 659         "console=$consoledev,$baudrate $othbootargs; "  \
 660         "tftp $ramdiskaddr $ramdiskfile;"       \
 661         "tftp $loadaddr $bootfile;"             \
 662         "tftp $fdtaddr $fdtfile;"               \
 663         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 664
 665 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 666
 667 #endif  /* __CONFIG_H */