include/configs/CPU87.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU               */
  21 #define CONFIG_CPU87            1       /* ...on a CPU87 board  */
  22 #define CONFIG_PCI
  23 #define CONFIG_CPM2             1       /* Has a CPM2 */
  24
  25 #ifdef CONFIG_BOOT_ROM
  26 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  27 #else
  28 #define CONFIG_SYS_TEXT_BASE    0xFF000000
  29 #endif
  30
  31 /*
  32  * select serial console configuration
  33  *
  34  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  35  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  36  * for SCC).
  37  *
  38  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  39  * defined elsewhere (for example, on the cogent platform, there are serial
  40  * ports on the motherboard which are used for the serial console - see
  41  * cogent/cma101/serial.[ch]).
  42  */
  43 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  44 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  45 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  46 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  47
  48 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  49 #define CONFIG_BAUDRATE         230400
  50 #else
  51 #define CONFIG_BAUDRATE         9600
  52 #endif
  53
  54 /*
  55  * select ethernet configuration
  56  *
  57  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  58  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  59  * for FCC)
  60  *
  61  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  62  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  63  */
  64 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  65 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  66 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  67 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
  68
  69 #define CONFIG_HAS_ETH1         1
  70 #define CONFIG_HAS_ETH2         1
  71
  72 #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  73
  74 /*
  75  * - Rx-CLK is CLK11
  76  * - Tx-CLK is CLK12
  77  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  78  * - Enable Full Duplex in FSMR
  79  */
  80 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  81 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  82 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  83 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  84
  85 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  86
  87 /*
  88  * - Rx-CLK is CLK13
  89  * - Tx-CLK is CLK14
  90  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  91  * - Enable Full Duplex in FSMR
  92  */
  93 # define CONFIG_SYS_CMXFCR_MASK2        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  94 # define CONFIG_SYS_CMXFCR_VALUE2       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  95 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
  96 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
  97
  98 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  99
 100 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 101 #define CONFIG_8260_CLKIN       100000000       /* in Hz */
 102
 103 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 104
 105 #define CONFIG_PREBOOT                                                          \
 106         "echo; "                                                                \
 107         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "   \
 108         "echo"
 109
 110 #undef  CONFIG_BOOTARGS
 111 #define CONFIG_BOOTCOMMAND                                                      \
 112         "bootp; "                                                               \
 113         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
 114         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
 115         "bootm"
 116
 117 /*-----------------------------------------------------------------------
 118  * I2C/EEPROM/RTC configuration
 119  */
 120 #define CONFIG_SYS_I2C
 121 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 122 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 123 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 124
 125 /*
 126  * Software (bit-bang) I2C driver configuration
 127  */
 128 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 129 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 130 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 131 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 132 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 133                         else    iop->pdat &= ~0x00010000
 134 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 135                         else    iop->pdat &= ~0x00020000
 136 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 137
 138 #define CONFIG_RTC_PCF8563
 139 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
 140
 141 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 142
 143 /*-----------------------------------------------------------------------
 144  * Disk-On-Chip configuration
 145  */
 146
 147 #define CONFIG_SYS_MAX_DOC_DEVICE       1       /* Max number of DOC devices    */
 148
 149 #define CONFIG_SYS_DOC_SUPPORT_2000
 150 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
 151
 152 /*-----------------------------------------------------------------------
 153  * Miscellaneous configuration options
 154  */
 155
 156 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 157 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 158
 159 /*
 160  * BOOTP options
 161  */
 162 #define CONFIG_BOOTP_SUBNETMASK
 163 #define CONFIG_BOOTP_GATEWAY
 164 #define CONFIG_BOOTP_HOSTNAME
 165 #define CONFIG_BOOTP_BOOTPATH
 166 #define CONFIG_BOOTP_BOOTFILESIZE
 167
 168
 169 /*
 170  * Command line configuration.
 171  */
 172 #include <config_cmd_default.h>
 173
 174 #define CONFIG_CMD_BEDBUG
 175 #define CONFIG_CMD_DATE
 176 #define CONFIG_CMD_EEPROM
 177 #define CONFIG_CMD_I2C
 178
 179 #ifdef CONFIG_PCI
 180 #define CONFIG_PCI_INDIRECT_BRIDGE
 181     #define CONFIG_CMD_PCI
 182 #endif
 183
 184 /*
 185  * Miscellaneous configurable options
 186  */
 187 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 188 #if defined(CONFIG_CMD_KGDB)
 189 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 190 #else
 191 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 192 #endif
 193 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 194 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 195 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 196
 197 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 198 #define CONFIG_SYS_MEMTEST_END 0x0C00000        /* 4 ... 12 MB in DRAM  */
 199
 200 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 201
 202 #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100     /* "bad" address                */
 203
 204 #define CONFIG_LOOPW
 205
 206 /*
 207  * For booting Linux, the board info and command line data
 208  * have to be in the first 8 MB of memory, since this is
 209  * the maximum mapped by the Linux kernel during initialization.
 210  */
 211 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 212
 213 /*-----------------------------------------------------------------------
 214  * Flash configuration
 215  */
 216
 217 #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
 218 #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
 219 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 220 #define CONFIG_SYS_FLASH_SIZE           0x00800000
 221
 222 /*-----------------------------------------------------------------------
 223  * FLASH organization
 224  */
 225 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       135     /* max num of sects on one chip */
 227
 228 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 229 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 230
 231 /*-----------------------------------------------------------------------
 232  * Other areas to be mapped
 233  */
 234
 235 /* CS3: Dual ported SRAM */
 236 #define CONFIG_SYS_DPSRAM_BASE          0x40000000
 237 #define CONFIG_SYS_DPSRAM_SIZE          0x00100000
 238
 239 /* CS4: DiskOnChip */
 240 #define CONFIG_SYS_DOC_BASE             0xF4000000
 241 #define CONFIG_SYS_DOC_SIZE             0x00100000
 242
 243 /* CS5: FDC37C78 controller */
 244 #define CONFIG_SYS_FDC37C78_BASE        0xF1000000
 245 #define CONFIG_SYS_FDC37C78_SIZE        0x00100000
 246
 247 /* CS6: Board configuration registers */
 248 #define CONFIG_SYS_BCRS_BASE            0xF2000000
 249 #define CONFIG_SYS_BCRS_SIZE            0x00010000
 250
 251 /* CS7: VME Extended Access Range */
 252 #define CONFIG_SYS_VMEEAR_BASE          0x60000000
 253 #define CONFIG_SYS_VMEEAR_SIZE          0x01000000
 254
 255 /* CS8: VME Standard Access Range */
 256 #define CONFIG_SYS_VMESAR_BASE          0xFE000000
 257 #define CONFIG_SYS_VMESAR_SIZE          0x01000000
 258
 259 /* CS9: VME Short I/O Access Range */
 260 #define CONFIG_SYS_VMESIOAR_BASE        0xFD000000
 261 #define CONFIG_SYS_VMESIOAR_SIZE        0x01000000
 262
 263 /*-----------------------------------------------------------------------
 264  * Hard Reset Configuration Words
 265  *
 266  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 267  * defines for the various registers affected by the HRCW e.g. changing
 268  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 269  */
 270 #if defined(CONFIG_BOOT_ROM)
 271 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
 272                                  HRCW_BPS01 | HRCW_CS10PC01)
 273 #else
 274 #define CONFIG_SYS_HRCW_MASTER          (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
 275 #endif
 276
 277 /* no slaves so just fill with zeros */
 278 #define CONFIG_SYS_HRCW_SLAVE1          0
 279 #define CONFIG_SYS_HRCW_SLAVE2          0
 280 #define CONFIG_SYS_HRCW_SLAVE3          0
 281 #define CONFIG_SYS_HRCW_SLAVE4          0
 282 #define CONFIG_SYS_HRCW_SLAVE5          0
 283 #define CONFIG_SYS_HRCW_SLAVE6          0
 284 #define CONFIG_SYS_HRCW_SLAVE7          0
 285
 286 /*-----------------------------------------------------------------------
 287  * Internal Memory Mapped Register
 288  */
 289 #define CONFIG_SYS_IMMR         0xF0000000
 290
 291 /*-----------------------------------------------------------------------
 292  * Definitions for initial stack pointer and data area (in DPRAM)
 293  */
 294 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 295 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM   */
 296 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 297 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 298
 299 /*-----------------------------------------------------------------------
 300  * Start addresses for the final memory configuration
 301  * (Set up by the startup code)
 302  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 303  *
 304  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
 305  */
 306 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 307 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* max. 128 MB          */
 308 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 309 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 310 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 311
 312 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 313 # define CONFIG_SYS_RAMBOOT
 314 #endif
 315
 316 #ifdef  CONFIG_PCI
 317 #define CONFIG_PCI_PNP
 318 #define CONFIG_EEPRO100
 319 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 320 #endif
 321
 322 #if 0
 323 /* environment is in Flash */
 324 #define CONFIG_ENV_IS_IN_FLASH  1
 325 #ifdef CONFIG_BOOT_ROM
 326 # define CONFIG_ENV_ADDR                (CONFIG_SYS_FLASH_BASE+0x70000)
 327 # define CONFIG_ENV_SIZE                0x10000
 328 # define CONFIG_ENV_SECT_SIZE   0x10000
 329 #endif
 330 #else
 331 /* environment is in EEPROM */
 332 #define CONFIG_ENV_IS_IN_EEPROM 1
 333 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM X24C16                */
 334 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 335 /* mask of address bits that overflow into the "EEPROM chip address"    */
 336 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 337 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 338 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 339 #define CONFIG_ENV_OFFSET               512
 340 #define CONFIG_ENV_SIZE         (2048 - 512)
 341 #endif
 342
 343 /*-----------------------------------------------------------------------
 344  * Cache Configuration
 345  */
 346 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPU              */
 347 #if defined(CONFIG_CMD_KGDB)
 348 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 349 #endif
 350
 351 /*-----------------------------------------------------------------------
 352  * HIDx - Hardware Implementation-dependent Registers                    2-11
 353  *-----------------------------------------------------------------------
 354  * HID0 also contains cache control - initially enable both caches and
 355  * invalidate contents, then the final state leaves only the instruction
 356  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 357  * but Soft reset does not.
 358  *
 359  * HID1 has only read-only information - nothing to set.
 360  */
 361 #define CONFIG_SYS_HID0_INIT    (HID0_ICE|HID0_DCE|HID0_ICFI|\
 362                          HID0_DCI|HID0_IFEM|HID0_ABE)
 363 #define CONFIG_SYS_HID0_FINAL   (HID0_IFEM|HID0_ABE)
 364 #define CONFIG_SYS_HID2 0
 365
 366 /*-----------------------------------------------------------------------
 367  * RMR - Reset Mode Register                                     5-5
 368  *-----------------------------------------------------------------------
 369  * turn on Checkstop Reset Enable
 370  */
 371 #define CONFIG_SYS_RMR          RMR_CSRE
 372
 373 /*-----------------------------------------------------------------------
 374  * BCR - Bus Configuration                                       4-25
 375  *-----------------------------------------------------------------------
 376  */
 377 #define BCR_APD01       0x10000000
 378 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 379
 380 /*-----------------------------------------------------------------------
 381  * SIUMCR - SIU Module Configuration                             4-31
 382  *-----------------------------------------------------------------------
 383  */
 384 #define CONFIG_SYS_SIUMCR       (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
 385                          SIUMCR_CS10PC01|SIUMCR_BCTLC10)
 386
 387 /*-----------------------------------------------------------------------
 388  * SYPCR - System Protection Control                             4-35
 389  * SYPCR can only be written once after reset!
 390  *-----------------------------------------------------------------------
 391  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 392  */
 393 #if defined(CONFIG_WATCHDOG)
 394 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 395                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 396 #else
 397 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 398                          SYPCR_SWRI|SYPCR_SWP)
 399 #endif /* CONFIG_WATCHDOG */
 400
 401 /*-----------------------------------------------------------------------
 402  * TMCNTSC - Time Counter Status and Control                     4-40
 403  *-----------------------------------------------------------------------
 404  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 405  * and enable Time Counter
 406  */
 407 #define CONFIG_SYS_TMCNTSC      (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 408
 409 /*-----------------------------------------------------------------------
 410  * PISCR - Periodic Interrupt Status and Control                 4-42
 411  *-----------------------------------------------------------------------
 412  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 413  * Periodic timer
 414  */
 415 #define CONFIG_SYS_PISCR        (PISCR_PS|PISCR_PTF|PISCR_PTE)
 416
 417 /*-----------------------------------------------------------------------
 418  * SCCR - System Clock Control                                   9-8
 419  *-----------------------------------------------------------------------
 420  * Ensure DFBRG is Divide by 16
 421  */
 422 #define CONFIG_SYS_SCCR SCCR_DFBRG01
 423
 424 /*-----------------------------------------------------------------------
 425  * RCCR - RISC Controller Configuration                         13-7
 426  *-----------------------------------------------------------------------
 427  */
 428 #define CONFIG_SYS_RCCR 0
 429
 430 #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
 431
 432 /*
 433  * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
 434  * refresh rate = 7.68 uS (100 MHz Bus Clock)
 435  */
 436
 437 /*-----------------------------------------------------------------------
 438  * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 439  *-----------------------------------------------------------------------
 440  */
 441 #define CONFIG_SYS_MPTPR        0x2000
 442
 443 /*-----------------------------------------------------------------------
 444  * PSRT - Refresh Timer Register                                10-16
 445  *-----------------------------------------------------------------------
 446  */
 447 #define CONFIG_SYS_PSRT 0x16
 448
 449 /*-----------------------------------------------------------------------
 450  * PSRT - SDRAM Mode Register                                   10-10
 451  *-----------------------------------------------------------------------
 452  */
 453
 454         /* SDRAM initialization values for 8-column chips
 455          */
 456 #define CONFIG_SYS_OR2_8COL     (CONFIG_SYS_MIN_AM_MASK         |\
 457                          ORxS_BPD_4                     |\
 458                          ORxS_ROWST_PBI0_A9             |\
 459                          ORxS_NUMR_12)
 460
 461 #define CONFIG_SYS_PSDMR_8COL   (PSDMR_SDAM_A13_IS_A5           |\
 462                          PSDMR_BSMA_A14_A16             |\
 463                          PSDMR_SDA10_PBI0_A10           |\
 464                          PSDMR_RFRC_7_CLK               |\
 465                          PSDMR_PRETOACT_2W              |\
 466                          PSDMR_ACTTORW_2W               |\
 467                          PSDMR_LDOTOPRE_1C              |\
 468                          PSDMR_WRC_1C                   |\
 469                          PSDMR_CL_2)
 470
 471         /* SDRAM initialization values for 9-column chips
 472          */
 473 #define CONFIG_SYS_OR2_9COL     (CONFIG_SYS_MIN_AM_MASK         |\
 474                          ORxS_BPD_4                     |\
 475                          ORxS_ROWST_PBI0_A7             |\
 476                          ORxS_NUMR_13)
 477
 478 #define CONFIG_SYS_PSDMR_9COL   (PSDMR_SDAM_A14_IS_A5           |\
 479                          PSDMR_BSMA_A13_A15             |\
 480                          PSDMR_SDA10_PBI0_A9            |\
 481                          PSDMR_RFRC_7_CLK               |\
 482                          PSDMR_PRETOACT_2W              |\
 483                          PSDMR_ACTTORW_2W               |\
 484                          PSDMR_LDOTOPRE_1C              |\
 485                          PSDMR_WRC_1C                   |\
 486                          PSDMR_CL_2)
 487
 488         /* SDRAM initialization values for 10-column chips
 489          */
 490 #define CONFIG_SYS_OR2_10COL    (CONFIG_SYS_MIN_AM_MASK         |\
 491                          ORxS_BPD_4                     |\
 492                          ORxS_ROWST_PBI1_A4             |\
 493                          ORxS_NUMR_13)
 494
 495 #define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 496                          PSDMR_SDAM_A17_IS_A5           |\
 497                          PSDMR_BSMA_A13_A15             |\
 498                          PSDMR_SDA10_PBI1_A6            |\
 499                          PSDMR_RFRC_7_CLK               |\
 500                          PSDMR_PRETOACT_2W              |\
 501                          PSDMR_ACTTORW_2W               |\
 502                          PSDMR_LDOTOPRE_1C              |\
 503                          PSDMR_WRC_1C                   |\
 504                          PSDMR_CL_2)
 505
 506 /*
 507  * Init Memory Controller:
 508  *
 509  * Bank Bus     Machine PortSz  Device
 510  * ---- ---     ------- ------  ------
 511  *  0   60x     GPCM    8  bit  Boot ROM
 512  *  1   60x     GPCM    64 bit  FLASH
 513  *  2   60x     SDRAM   64 bit  SDRAM
 514  *
 515  */
 516
 517 #define CONFIG_SYS_MRS_OFFS     0x00000000
 518
 519 #ifdef CONFIG_BOOT_ROM
 520 /* Bank 0 - Boot ROM
 521  */
 522 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 523                          BRx_PS_8                       |\
 524                          BRx_MS_GPCM_P                  |\
 525                          BRx_V)
 526
 527 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 528                          ORxG_CSNT                      |\
 529                          ORxG_ACS_DIV1                  |\
 530                          ORxG_SCY_5_CLK                 |\
 531                          ORxU_EHTR_8IDLE)
 532
 533 /* Bank 1 - FLASH
 534  */
 535 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 536                          BRx_PS_64                      |\
 537                          BRx_MS_GPCM_P                  |\
 538                          BRx_V)
 539
 540 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 541                          ORxG_CSNT                      |\
 542                          ORxG_ACS_DIV1                  |\
 543                          ORxG_SCY_5_CLK                 |\
 544                          ORxU_EHTR_8IDLE)
 545
 546 #else /* CONFIG_BOOT_ROM */
 547 /* Bank 0 - FLASH
 548  */
 549 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)   |\
 550                          BRx_PS_64                      |\
 551                          BRx_MS_GPCM_P                  |\
 552                          BRx_V)
 553
 554 #define CONFIG_SYS_OR0_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 555                          ORxG_CSNT                      |\
 556                          ORxG_ACS_DIV1                  |\
 557                          ORxG_SCY_5_CLK                 |\
 558                          ORxU_EHTR_8IDLE)
 559
 560 /* Bank 1 - Boot ROM
 561  */
 562 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
 563                          BRx_PS_8                       |\
 564                          BRx_MS_GPCM_P                  |\
 565                          BRx_V)
 566
 567 #define CONFIG_SYS_OR1_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)    |\
 568                          ORxG_CSNT                      |\
 569                          ORxG_ACS_DIV1                  |\
 570                          ORxG_SCY_5_CLK                 |\
 571                          ORxU_EHTR_8IDLE)
 572
 573 #endif /* CONFIG_BOOT_ROM */
 574
 575
 576 /* Bank 2 - 60x bus SDRAM
 577  */
 578 #ifndef CONFIG_SYS_RAMBOOT
 579 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)   |\
 580                          BRx_PS_64                      |\
 581                          BRx_MS_SDRAM_P                 |\
 582                          BRx_V)
 583
 584 #define CONFIG_SYS_OR2_PRELIM    CONFIG_SYS_OR2_8COL
 585
 586 #define CONFIG_SYS_PSDMR         CONFIG_SYS_PSDMR_8COL
 587 #endif /* CONFIG_SYS_RAMBOOT */
 588
 589 /* Bank 3 - Dual Ported SRAM
 590  */
 591 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
 592                          BRx_PS_16                      |\
 593                          BRx_MS_GPCM_P                  |\
 594                          BRx_V)
 595
 596 #define CONFIG_SYS_OR3_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)     |\
 597                          ORxG_CSNT                      |\
 598                          ORxG_ACS_DIV1                  |\
 599                          ORxG_SCY_7_CLK                 |\
 600                          ORxG_SETA)
 601
 602 /* Bank 4 - DiskOnChip
 603  */
 604 #define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)     |\
 605                          BRx_PS_8                       |\
 606                          BRx_MS_GPCM_P                  |\
 607                          BRx_V)
 608
 609 #define CONFIG_SYS_OR4_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)        |\
 610                          ORxG_CSNT                      |\
 611                          ORxG_ACS_DIV2                  |\
 612                          ORxG_SCY_9_CLK                 |\
 613                          ORxU_EHTR_8IDLE)
 614
 615 /* Bank 5 - FDC37C78 controller
 616  */
 617 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
 618                          BRx_PS_8                         |\
 619                          BRx_MS_GPCM_P                    |\
 620                          BRx_V)
 621
 622 #define CONFIG_SYS_OR5_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)     |\
 623                          ORxG_ACS_DIV2                    |\
 624                          ORxG_SCY_10_CLK                  |\
 625                          ORxU_EHTR_8IDLE)
 626
 627 /* Bank 6 - Board control registers
 628  */
 629 #define CONFIG_SYS_BR6_PRELIM   ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)    |\
 630                          BRx_PS_8                       |\
 631                          BRx_MS_GPCM_P                  |\
 632                          BRx_V)
 633
 634 #define CONFIG_SYS_OR6_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)       |\
 635                          ORxG_CSNT                      |\
 636                          ORxG_SCY_7_CLK)
 637
 638 /* Bank 7 - VME Extended Access Range
 639  */
 640 #define CONFIG_SYS_BR7_PRELIM   ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
 641                          BRx_PS_32                      |\
 642                          BRx_MS_GPCM_P                  |\
 643                          BRx_V)
 644
 645 #define CONFIG_SYS_OR7_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)     |\
 646                          ORxG_CSNT                      |\
 647                          ORxG_ACS_DIV1                  |\
 648                          ORxG_SCY_7_CLK                 |\
 649                          ORxG_SETA)
 650
 651 /* Bank 8 - VME Standard Access Range
 652  */
 653 #define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
 654                          BRx_PS_16                      |\
 655                          BRx_MS_GPCM_P                  |\
 656                          BRx_V)
 657
 658 #define CONFIG_SYS_OR8_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)     |\
 659                          ORxG_CSNT                      |\
 660                          ORxG_ACS_DIV1                  |\
 661                          ORxG_SCY_7_CLK                 |\
 662                          ORxG_SETA)
 663
 664 /* Bank 9 - VME Short I/O Access Range
 665  */
 666 #define CONFIG_SYS_BR9_PRELIM   ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
 667                          BRx_PS_16                        |\
 668                          BRx_MS_GPCM_P                    |\
 669                          BRx_V)
 670
 671 #define CONFIG_SYS_OR9_PRELIM   (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)     |\
 672                          ORxG_CSNT                        |\
 673                          ORxG_ACS_DIV1                    |\
 674                          ORxG_SCY_7_CLK                   |\
 675                          ORxG_SETA)
 676
 677 #endif  /* __CONFIG_H */