include/configs/M54455EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF54455 EVB board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M54455EVB_H
  15 #define _M54455EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21 #define CONFIG_M54455EVB        /* M54455EVB board */
  22
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_MCFUART
  26 #define CONFIG_SYS_UART_PORT            (0)
  27 #define CONFIG_BAUDRATE         115200
  28
  29 #undef CONFIG_WATCHDOG
  30
  31 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  32
  33 /*
  34  * BOOTP options
  35  */
  36 #define CONFIG_BOOTP_BOOTFILESIZE
  37 #define CONFIG_BOOTP_BOOTPATH
  38 #define CONFIG_BOOTP_GATEWAY
  39 #define CONFIG_BOOTP_HOSTNAME
  40
  41 /* Command line configuration */
  42 #define CONFIG_CMD_CACHE
  43 #define CONFIG_CMD_DATE
  44 #define CONFIG_CMD_DHCP
  45 #define CONFIG_CMD_ELF
  46 #define CONFIG_CMD_EXT2
  47 #define CONFIG_CMD_FAT
  48 #define CONFIG_CMD_I2C
  49 #define CONFIG_CMD_IDE
  50 #define CONFIG_CMD_JFFS2
  51 #define CONFIG_CMD_MII
  52 #undef CONFIG_CMD_PCI
  53 #define CONFIG_CMD_PING
  54 #define CONFIG_CMD_REGINFO
  55 #define CONFIG_CMD_SPI
  56 #define CONFIG_CMD_SF
  57
  58
  59 /* Network configuration */
  60 #define CONFIG_MCFFEC
  61 #ifdef CONFIG_MCFFEC
  62 #       define CONFIG_MII               1
  63 #       define CONFIG_MII_INIT          1
  64 #       define CONFIG_SYS_DISCOVER_PHY
  65 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  66 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  67
  68 #       define CONFIG_SYS_FEC0_PINMUX   0
  69 #       define CONFIG_SYS_FEC1_PINMUX   0
  70 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  71 #       define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  72 #       define MCFFEC_TOUT_LOOP 50000
  73 #       define CONFIG_HAS_ETH1
  74
  75 #       define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
  76 #       define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  77 #       define CONFIG_ETHPRIME          "FEC0"
  78 #       define CONFIG_IPADDR            192.162.1.2
  79 #       define CONFIG_NETMASK           255.255.255.0
  80 #       define CONFIG_SERVERIP          192.162.1.1
  81 #       define CONFIG_GATEWAYIP         192.162.1.1
  82
  83 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  84 #       ifndef CONFIG_SYS_DISCOVER_PHY
  85 #               define FECDUPLEX        FULL
  86 #               define FECSPEED         _100BASET
  87 #       else
  88 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  89 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  90 #               endif
  91 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  92 #endif
  93
  94 #define CONFIG_HOSTNAME         M54455EVB
  95 #ifdef CONFIG_SYS_STMICRO_BOOT
  96 /* ST Micro serial flash */
  97 #define CONFIG_SYS_LOAD_ADDR2           0x40010013
  98 #define CONFIG_EXTRA_ENV_SETTINGS               \
  99         "netdev=eth0\0"                         \
 100         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 101         "loadaddr=0x40010000\0"                 \
 102         "sbfhdr=sbfhdr.bin\0"                   \
 103         "uboot=u-boot.bin\0"                    \
 104         "load=tftp ${loadaddr} ${sbfhdr};"      \
 105         "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"       \
 106         "upd=run load; run prog\0"              \
 107         "prog=sf probe 0:1 1000000 3;"          \
 108         "sf erase 0 30000;"                     \
 109         "sf write ${loadaddr} 0 0x30000;"       \
 110         "save\0"                                \
 111         ""
 112 #else
 113 /* Atmel and Intel */
 114 #ifdef CONFIG_SYS_ATMEL_BOOT
 115 #       define CONFIG_SYS_UBOOT_END     0x0403FFFF
 116 #elif defined(CONFIG_SYS_INTEL_BOOT)
 117 #       define CONFIG_SYS_UBOOT_END     0x3FFFF
 118 #endif
 119 #define CONFIG_EXTRA_ENV_SETTINGS               \
 120         "netdev=eth0\0"                         \
 121         "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"     \
 122         "loadaddr=0x40010000\0"                 \
 123         "uboot=u-boot.bin\0"                    \
 124         "load=tftp ${loadaddr} ${uboot}\0"      \
 125         "upd=run load; run prog\0"              \
 126         "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)     \
 127         " " __stringify(CONFIG_SYS_UBOOT_END) ";"               \
 128         "era " __stringify(CONFIG_SYS_FLASH_BASE) " "           \
 129         __stringify(CONFIG_SYS_UBOOT_END) ";"                   \
 130         "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)  \
 131         " ${filesize}; save\0"                  \
 132         ""
 133 #endif
 134
 135 /* ATA configuration */
 136 #define CONFIG_ISO_PARTITION
 137 #define CONFIG_DOS_PARTITION
 138 #define CONFIG_IDE_RESET        1
 139 #define CONFIG_IDE_PREINIT      1
 140 #define CONFIG_ATAPI
 141 #undef CONFIG_LBA48
 142
 143 #define CONFIG_SYS_IDE_MAXBUS           1
 144 #define CONFIG_SYS_IDE_MAXDEVICE        2
 145
 146 #define CONFIG_SYS_ATA_BASE_ADDR        0x90000000
 147 #define CONFIG_SYS_ATA_IDE0_OFFSET      0
 148
 149 #define CONFIG_SYS_ATA_DATA_OFFSET      0xA0    /* Offset for data I/O                            */
 150 #define CONFIG_SYS_ATA_REG_OFFSET       0xA0    /* Offset for normal register accesses */
 151 #define CONFIG_SYS_ATA_ALT_OFFSET       0xC0    /* Offset for alternate registers           */
 152 #define CONFIG_SYS_ATA_STRIDE           4       /* Interval between registers                 */
 153
 154 /* Realtime clock */
 155 #define CONFIG_MCFRTC
 156 #undef RTC_DEBUG
 157 #define CONFIG_SYS_RTC_OSCILLATOR       (32 * CONFIG_SYS_HZ)
 158
 159 /* Timer */
 160 #define CONFIG_MCFTMR
 161 #undef CONFIG_MCFPIT
 162
 163 /* I2c */
 164 #define CONFIG_SYS_I2C
 165 #define CONFIG_SYS_I2C_FSL
 166 #define CONFIG_SYS_FSL_I2C_SPEED        80000
 167 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 168 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
 169 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
 170
 171 /* DSPI and Serial Flash */
 172 #define CONFIG_CF_SPI
 173 #define CONFIG_CF_DSPI
 174 #define CONFIG_HARD_SPI
 175 #define CONFIG_SYS_SBFHDR_SIZE          0x13
 176 #ifdef CONFIG_CMD_SPI
 177 #       define CONFIG_SPI_FLASH_STMICRO
 178
 179 #       define CONFIG_SYS_DSPI_CTAR0            (DSPI_CTAR_TRSZ(7) | \
 180                                          DSPI_CTAR_PCSSCK_1CLK | \
 181                                          DSPI_CTAR_PASC(0) | \
 182                                          DSPI_CTAR_PDT(0) | \
 183                                          DSPI_CTAR_CSSCK(0) | \
 184                                          DSPI_CTAR_ASC(0) | \
 185                                          DSPI_CTAR_DT(1))
 186 #endif
 187
 188 /* PCI */
 189 #ifdef CONFIG_CMD_PCI
 190 #define CONFIG_PCI              1
 191 #define CONFIG_PCI_PNP          1
 192 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 193
 194 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  4
 195
 196 #define CONFIG_SYS_PCI_MEM_BUS          0xA0000000
 197 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
 198 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 199
 200 #define CONFIG_SYS_PCI_IO_BUS           0xB1000000
 201 #define CONFIG_SYS_PCI_IO_PHYS          CONFIG_SYS_PCI_IO_BUS
 202 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000
 203
 204 #define CONFIG_SYS_PCI_CFG_BUS          0xB0000000
 205 #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
 206 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
 207 #endif
 208
 209 /* FPGA - Spartan 2 */
 210 /* experiment
 211 #define CONFIG_FPGA
 212 #define CONFIG_FPGA_COUNT       1
 213 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 214 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 215 */
 216
 217 /* Input, PCI, Flexbus, and VCO */
 218 #define CONFIG_EXTRA_CLOCK
 219
 220 #define CONFIG_PRAM             2048    /* 2048 KB */
 221
 222 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 223
 224 #if defined(CONFIG_CMD_KGDB)
 225 #define CONFIG_SYS_CBSIZE                       1024    /* Console I/O Buffer Size */
 226 #else
 227 #define CONFIG_SYS_CBSIZE                       256     /* Console I/O Buffer Size */
 228 #endif
 229 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 230 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 231 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 232
 233 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x10000)
 234
 235 #define CONFIG_SYS_MBAR         0xFC000000
 236
 237 /*
 238  * Low Level Configuration Settings
 239  * (address mappings, register initial values, etc.)
 240  * You should know what you are doing if you make changes here.
 241  */
 242
 243 /*-----------------------------------------------------------------------
 244  * Definitions for initial stack pointer and data area (in DPRAM)
 245  */
 246 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
 247 #define CONFIG_SYS_INIT_RAM_SIZE                0x8000  /* Size of used area in internal SRAM */
 248 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
 249 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 250 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 251 #define CONFIG_SYS_SBFHDR_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - 32)
 252
 253 /*-----------------------------------------------------------------------
 254  * Start addresses for the final memory configuration
 255  * (Set up by the startup code)
 256  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 257  */
 258 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 259 #define CONFIG_SYS_SDRAM_BASE1          0x48000000
 260 #define CONFIG_SYS_SDRAM_SIZE           256     /* SDRAM size in MB */
 261 #define CONFIG_SYS_SDRAM_CFG1           0x65311610
 262 #define CONFIG_SYS_SDRAM_CFG2           0x59670000
 263 #define CONFIG_SYS_SDRAM_CTRL           0xEA0B2000
 264 #define CONFIG_SYS_SDRAM_EMOD           0x40010000
 265 #define CONFIG_SYS_SDRAM_MODE           0x00010033
 266 #define CONFIG_SYS_SDRAM_DRV_STRENGTH   0xAA
 267
 268 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 269 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 270
 271 #ifdef CONFIG_CF_SBF
 272 #       define CONFIG_SERIAL_BOOT
 273 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 274 #else
 275 #       define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 276 #endif
 277 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 278 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 279
 280 /* Reserve 256 kB for malloc() */
 281 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 282
 283 /*
 284  * For booting Linux, the board info and command line data
 285  * have to be in the first 8 MB of memory, since this is
 286  * the maximum mapped by the Linux kernel during initialization ??
 287  */
 288 /* Initial Memory map for Linux */
 289 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 290
 291 /*
 292  * Configuration for environment
 293  * Environment is not embedded in u-boot. First time runing may have env
 294  * crc error warning if there is no correct environment on the flash.
 295  */
 296 #ifdef CONFIG_CF_SBF
 297 #       define CONFIG_ENV_IS_IN_SPI_FLASH
 298 #       define CONFIG_ENV_SPI_CS                1
 299 #else
 300 #       define CONFIG_ENV_IS_IN_FLASH   1
 301 #endif
 302 #undef CONFIG_ENV_OVERWRITE
 303
 304 /*-----------------------------------------------------------------------
 305  * FLASH organization
 306  */
 307 #ifdef CONFIG_SYS_STMICRO_BOOT
 308 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 309 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS1_BASE
 310 #       define CONFIG_ENV_OFFSET                0x30000
 311 #       define CONFIG_ENV_SIZE          0x2000
 312 #       define CONFIG_ENV_SECT_SIZE     0x10000
 313 #endif
 314 #ifdef CONFIG_SYS_ATMEL_BOOT
 315 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 316 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 317 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 318 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 319 #       define CONFIG_ENV_SIZE          0x2000
 320 #       define CONFIG_ENV_SECT_SIZE     0x10000
 321 #endif
 322 #ifdef CONFIG_SYS_INTEL_BOOT
 323 #       define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
 324 #       define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
 325 #       define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS1_BASE
 326 #       define CONFIG_ENV_ADDR          (CONFIG_SYS_FLASH_BASE + 0x40000)
 327 #       define CONFIG_ENV_SIZE          0x2000
 328 #       define CONFIG_ENV_SECT_SIZE     0x20000
 329 #endif
 330
 331 #define CONFIG_SYS_FLASH_CFI
 332 #ifdef CONFIG_SYS_FLASH_CFI
 333
 334 #       define CONFIG_FLASH_CFI_DRIVER  1
 335 #       define CONFIG_SYS_FLASH_USE_BUFFER_WRITE        1
 336 #       define CONFIG_SYS_FLASH_SIZE            0x1000000       /* Max size that the board might have */
 337 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_8BIT
 338 #       define CONFIG_SYS_MAX_FLASH_BANKS       2       /* max number of memory banks */
 339 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 340 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 341 #       define CONFIG_SYS_FLASH_CHECKSUM
 342 #       define CONFIG_SYS_FLASH_BANKS_LIST      { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
 343 #       define CONFIG_FLASH_CFI_LEGACY
 344
 345 #ifdef CONFIG_FLASH_CFI_LEGACY
 346 #       define CONFIG_SYS_ATMEL_REGION          4
 347 #       define CONFIG_SYS_ATMEL_TOTALSECT       11
 348 #       define CONFIG_SYS_ATMEL_SECT            {1, 2, 1, 7}
 349 #       define CONFIG_SYS_ATMEL_SECTSZ          {0x4000, 0x2000, 0x8000, 0x10000}
 350 #endif
 351 #endif
 352
 353 /*
 354  * This is setting for JFFS2 support in u-boot.
 355  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 356  */
 357 #ifdef CONFIG_CMD_JFFS2
 358 #ifdef CF_STMICRO_BOOT
 359 #       define CONFIG_JFFS2_DEV         "nor1"
 360 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 361 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
 362 #endif
 363 #ifdef CONFIG_SYS_ATMEL_BOOT
 364 #       define CONFIG_JFFS2_DEV         "nor1"
 365 #       define CONFIG_JFFS2_PART_SIZE   0x01000000
 366 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
 367 #endif
 368 #ifdef CONFIG_SYS_INTEL_BOOT
 369 #       define CONFIG_JFFS2_DEV         "nor0"
 370 #       define CONFIG_JFFS2_PART_SIZE   (0x01000000 - 0x500000)
 371 #       define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
 372 #endif
 373 #endif
 374
 375 /*-----------------------------------------------------------------------
 376  * Cache Configuration
 377  */
 378 #define CONFIG_SYS_CACHELINE_SIZE               16
 379
 380 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 381                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 382 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 383                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 384 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_BCINVA + CF_CACR_ICINVA)
 385 #define CONFIG_SYS_DCACHE_INV           (CF_CACR_DCINVA)
 386 #define CONFIG_SYS_CACHE_ACR2           (CONFIG_SYS_SDRAM_BASE | \
 387                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 388                                          CF_ACR_EN | CF_ACR_SM_ALL)
 389 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_BEC | CF_CACR_IEC | \
 390                                          CF_CACR_ICINVA | CF_CACR_EUSP)
 391 #define CONFIG_SYS_CACHE_DCACR          ((CONFIG_SYS_CACHE_ICACR | \
 392                                          CF_CACR_DEC | CF_CACR_DDCM_P | \
 393                                          CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
 394
 395 /*-----------------------------------------------------------------------
 396  * Memory bank definitions
 397  */
 398 /*
 399  * CS0 - NOR Flash 1, 2, 4, or 8MB
 400  * CS1 - CompactFlash and registers
 401  * CS2 - CPLD
 402  * CS3 - FPGA
 403  * CS4 - Available
 404  * CS5 - Available
 405  */
 406
 407 #if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 408  /* Atmel Flash */
 409 #define CONFIG_SYS_CS0_BASE             0x04000000
 410 #define CONFIG_SYS_CS0_MASK             0x00070001
 411 #define CONFIG_SYS_CS0_CTRL             0x00001140
 412 /* Intel Flash */
 413 #define CONFIG_SYS_CS1_BASE             0x00000000
 414 #define CONFIG_SYS_CS1_MASK             0x01FF0001
 415 #define CONFIG_SYS_CS1_CTRL             0x00000D60
 416
 417 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS0_BASE
 418 #else
 419 /* Intel Flash */
 420 #define CONFIG_SYS_CS0_BASE             0x00000000
 421 #define CONFIG_SYS_CS0_MASK             0x01FF0001
 422 #define CONFIG_SYS_CS0_CTRL             0x00000D60
 423  /* Atmel Flash */
 424 #define CONFIG_SYS_CS1_BASE             0x04000000
 425 #define CONFIG_SYS_CS1_MASK             0x00070001
 426 #define CONFIG_SYS_CS1_CTRL             0x00001140
 427
 428 #define CONFIG_SYS_ATMEL_BASE           CONFIG_SYS_CS1_BASE
 429 #endif
 430
 431 /* CPLD */
 432 #define CONFIG_SYS_CS2_BASE             0x08000000
 433 #define CONFIG_SYS_CS2_MASK             0x00070001
 434 #define CONFIG_SYS_CS2_CTRL             0x003f1140
 435
 436 /* FPGA */
 437 #define CONFIG_SYS_CS3_BASE             0x09000000
 438 #define CONFIG_SYS_CS3_MASK             0x00070001
 439 #define CONFIG_SYS_CS3_CTRL             0x00000020
 440
 441 #endif                          /* _M54455EVB_H */