include/configs/at91sam9263ek.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Configuation settings for the AT91SAM9263EK board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * SoC must be defined first, before hardware.h is included.
  32  * In this case SoC is defined in boards.cfg.
  33  */
  34 #include <asm/hardware.h>
  35
  36 #define CONFIG_SYS_TEXT_BASE            0x21F00000
  37
  38 /* ARM asynchronous clock */
  39 #define CONFIG_SYS_AT91_MAIN_CLOCK      16367660 /* 16.367 MHz crystal */
  40 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  41 #define CONFIG_SYS_HZ                   1000
  42
  43 #define CONFIG_AT91SAM9263EK    1       /* It's an AT91SAM9263EK Board */
  44
  45 #define CONFIG_ARCH_CPU_INIT
  46 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff  */
  47
  48 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  49 #define CONFIG_SETUP_MEMORY_TAGS 1
  50 #define CONFIG_INITRD_TAG       1
  51
  52 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
  53 #define CONFIG_SKIP_LOWLEVEL_INIT
  54 #else
  55 #define CONFIG_SYS_USE_NORFLASH
  56 #endif
  57
  58 #define CONFIG_BOARD_EARLY_INIT_F
  59
  60 #define CONFIG_DISPLAY_CPUINFO
  61
  62 /*
  63  * Hardware drivers
  64  */
  65 #define CONFIG_ATMEL_LEGACY
  66 #define CONFIG_AT91_GPIO                1
  67 #define CONFIG_AT91_GPIO_PULLUP         1
  68
  69 /* serial console */
  70 #define CONFIG_ATMEL_USART
  71 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  72 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  73 #define CONFIG_BAUDRATE                 115200
  74
  75 /* LCD */
  76 #define CONFIG_LCD                      1
  77 #define LCD_BPP                         LCD_COLOR8
  78 #define CONFIG_LCD_LOGO                 1
  79 #undef LCD_TEST_PATTERN
  80 #define CONFIG_LCD_INFO                 1
  81 #define CONFIG_LCD_INFO_BELOW_LOGO      1
  82 #define CONFIG_SYS_WHITE_ON_BLACK       1
  83 #define CONFIG_ATMEL_LCD                1
  84 #define CONFIG_ATMEL_LCD_BGR555         1
  85 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
  86
  87 /* LED */
  88 #define CONFIG_AT91_LED
  89 #define CONFIG_RED_LED          AT91_PIN_PB7    /* the power led */
  90 #define CONFIG_GREEN_LED        AT91_PIN_PB8    /* the user1 led */
  91 #define CONFIG_YELLOW_LED       AT91_PIN_PC29   /* the user2 led */
  92
  93 #define CONFIG_BOOTDELAY        3
  94
  95 /*
  96  * BOOTP options
  97  */
  98 #define CONFIG_BOOTP_BOOTFILESIZE       1
  99 #define CONFIG_BOOTP_BOOTPATH           1
 100 #define CONFIG_BOOTP_GATEWAY            1
 101 #define CONFIG_BOOTP_HOSTNAME           1
 102
 103 /*
 104  * Command line configuration.
 105  */
 106 #include <config_cmd_default.h>
 107 #undef CONFIG_CMD_BDI
 108 #undef CONFIG_CMD_FPGA
 109 #undef CONFIG_CMD_IMI
 110 #undef CONFIG_CMD_IMLS
 111 #undef CONFIG_CMD_LOADS
 112 #undef CONFIG_CMD_SOURCE
 113
 114 #define CONFIG_CMD_PING         1
 115 #define CONFIG_CMD_DHCP         1
 116 #define CONFIG_CMD_NAND         1
 117 #define CONFIG_CMD_USB          1
 118
 119 /* SDRAM */
 120 #define CONFIG_NR_DRAM_BANKS            1
 121 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS1
 122 #define CONFIG_SYS_SDRAM_SIZE           0x04000000
 123
 124 #define CONFIG_SYS_INIT_SP_ADDR \
 125         (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
 126
 127 /* DataFlash */
 128 #define CONFIG_ATMEL_DATAFLASH_SPI
 129 #define CONFIG_HAS_DATAFLASH            1
 130 #define CONFIG_SYS_SPI_WRITE_TOUT               (5*CONFIG_SYS_HZ)
 131 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          1
 132 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* CS0 */
 133 #define AT91_SPI_CLK                    15000000
 134 #define DATAFLASH_TCSS                  (0x1a << 16)
 135 #define DATAFLASH_TCHS                  (0x1 << 24)
 136
 137 /* NOR flash, if populated */
 138 #ifdef CONFIG_SYS_USE_NORFLASH
 139 #define CONFIG_SYS_FLASH_CFI                    1
 140 #define CONFIG_FLASH_CFI_DRIVER                 1
 141 #define PHYS_FLASH_1                            0x10000000
 142 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 143 #define CONFIG_SYS_MAX_FLASH_SECT               256
 144 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 145
 146 #define CONFIG_SYS_MONITOR_SEC  1:0-3
 147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 148 #define CONFIG_SYS_MONITOR_LEN  (256 << 10)
 149 #define CONFIG_ENV_IS_IN_FLASH  1
 150 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x007FE000)
 151 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
 152
 153 /* Address and size of Primary Environment Sector */
 154 #define CONFIG_ENV_SIZE         0x2000
 155
 156 #define xstr(s)   str(s)
 157 #define str(s)  #s
 158
 159 #define CONFIG_EXTRA_ENV_SETTINGS       \
 160         "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
 161         "update=" \
 162                 "protect off ${monitor_base} +${filesize};" \
 163                 "erase ${monitor_base} +${filesize};" \
 164                 "cp.b ${load_addr} ${monitor_base} ${filesize};" \
 165                 "protect on ${monitor_base} +${filesize}\0"
 166
 167 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 168 #define MASTER_PLL_MUL          171
 169 #define MASTER_PLL_DIV          14
 170 #define MASTER_PLL_OUT          3
 171
 172 /* clocks */
 173 #define CONFIG_SYS_MOR_VAL                                              \
 174                 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
 175 #define CONFIG_SYS_PLLAR_VAL                                    \
 176         (AT91_PMC_PLLAR_29 |                                    \
 177         AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |                    \
 178         AT91_PMC_PLLXR_PLLCOUNT(63) |                           \
 179         AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |                \
 180         AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
 181
 182 /* PCK/2 = MCK Master Clock from PLLA */
 183 #define CONFIG_SYS_MCKR1_VAL            \
 184         (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |        \
 185          AT91_PMC_MCKR_MDIV_2)
 186
 187 /* PCK/2 = MCK Master Clock from PLLA */
 188 #define CONFIG_SYS_MCKR2_VAL            \
 189         (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |        \
 190         AT91_PMC_MCKR_MDIV_2)
 191
 192 /* define PDC[31:16] as DATA[31:16] */
 193 #define CONFIG_SYS_PIOD_PDR_VAL1        0xFFFF0000
 194 /* no pull-up for D[31:16] */
 195 #define CONFIG_SYS_PIOD_PPUDR_VAL       0xFFFF0000
 196 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
 197 #define CONFIG_SYS_MATRIX_EBICSA_VAL                                    \
 198         (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |       \
 199          AT91_MATRIX_CSA_EBI_CS1A)
 200
 201 /* SDRAM */
 202 /* SDRAMC_MR Mode register */
 203 #define CONFIG_SYS_SDRC_MR_VAL1         0
 204 /* SDRAMC_TR - Refresh Timer register */
 205 #define CONFIG_SYS_SDRC_TR_VAL1         0x13C
 206 /* SDRAMC_CR - Configuration register*/
 207 #define CONFIG_SYS_SDRC_CR_VAL                                                  \
 208                 (AT91_SDRAMC_NC_9 |                                             \
 209                  AT91_SDRAMC_NR_13 |                                            \
 210                  AT91_SDRAMC_NB_4 |                                             \
 211                  AT91_SDRAMC_CAS_3 |                                            \
 212                  AT91_SDRAMC_DBW_32 |                                           \
 213                  (1 <<  8) |            /* Write Recovery Delay */              \
 214                  (7 << 12) |            /* Row Cycle Delay */                   \
 215                  (2 << 16) |            /* Row Precharge Delay */               \
 216                  (2 << 20) |            /* Row to Column Delay */               \
 217                  (5 << 24) |            /* Active to Precharge Delay */         \
 218                  (1 << 28))             /* Exit Self Refresh to Active Delay */
 219
 220 /* Memory Device Register -> SDRAM */
 221 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
 222 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
 223 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
 224 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
 225 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
 226 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
 227 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
 228 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 229 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 230 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 231 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 232 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 233 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 234 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 235 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 236 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 237 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 238 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 239
 240 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
 241 #define CONFIG_SYS_SMC0_SETUP0_VAL                              \
 242         (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |   \
 243          AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
 244 #define CONFIG_SYS_SMC0_PULSE0_VAL                              \
 245         (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |   \
 246          AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
 247 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 248         (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
 249 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 250         (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |          \
 251          AT91_SMC_MODE_DBW_16 |                                 \
 252          AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
 253
 254 /* user reset enable */
 255 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 256                 (AT91_RSTC_KEY |                \
 257                 AT91_RSTC_MR_URSTEN |           \
 258                 AT91_RSTC_MR_ERSTL(15))
 259
 260 /* Disable Watchdog */
 261 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 262                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 263                  AT91_WDT_MR_WDV(0xfff) |                       \
 264                  AT91_WDT_MR_WDDIS |                            \
 265                  AT91_WDT_MR_WDD(0xfff))
 266
 267 #endif
 268
 269 #else
 270 #define CONFIG_SYS_NO_FLASH                     1
 271 #endif
 272
 273 /* NAND flash */
 274 #ifdef CONFIG_CMD_NAND
 275 #define CONFIG_NAND_ATMEL
 276 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 277 #define CONFIG_SYS_NAND_BASE                    ATMEL_BASE_CS3
 278 #define CONFIG_SYS_NAND_DBW_8                   1
 279 /* our ALE is AD21 */
 280 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
 281 /* our CLE is AD22 */
 282 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
 283 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIN_PD15
 284 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIN_PA22
 285 #endif
 286
 287 /* Ethernet */
 288 #define CONFIG_MACB                     1
 289 #define CONFIG_RMII                     1
 290 #define CONFIG_NET_RETRY_COUNT          20
 291 #define CONFIG_RESET_PHY_R              1
 292
 293 /* USB */
 294 #define CONFIG_USB_ATMEL
 295 #define CONFIG_USB_OHCI_NEW             1
 296 #define CONFIG_DOS_PARTITION            1
 297 #define CONFIG_SYS_USB_OHCI_CPU_INIT            1
 298 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00a00000      /* AT91SAM9263_UHP_BASE */
 299 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9263"
 300 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 301 #define CONFIG_USB_STORAGE              1
 302 #define CONFIG_CMD_FAT                  1
 303
 304 #define CONFIG_SYS_LOAD_ADDR                    0x22000000      /* load address */
 305
 306 #define CONFIG_SYS_MEMTEST_START                CONFIG_SYS_SDRAM_BASE
 307 #define CONFIG_SYS_MEMTEST_END                  0x23e00000
 308
 309 #ifdef CONFIG_SYS_USE_DATAFLASH
 310
 311 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 312 #define CONFIG_ENV_IS_IN_DATAFLASH      1
 313 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
 314 #define CONFIG_ENV_OFFSET               0x4200
 315 #define CONFIG_ENV_ADDR         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 316 #define CONFIG_ENV_SIZE         0x4200
 317 #define CONFIG_BOOTCOMMAND      "cp.b 0xC0042000 0x22000000 0x210000; bootm"
 318 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 319                                 "root=/dev/mtdblock0 " \
 320                                 "mtdparts=atmel_nand:-(root) "\
 321                                 "rw rootfstype=jffs2"
 322
 323 #elif CONFIG_SYS_USE_NANDFLASH
 324
 325 /* bootstrap + u-boot + env + linux in nandflash */
 326 #define CONFIG_ENV_IS_IN_NAND           1
 327 #define CONFIG_ENV_OFFSET               0x60000
 328 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 329 #define CONFIG_ENV_SIZE         0x20000         /* 1 sector = 128 kB */
 330 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0xA0000 0x200000; bootm"
 331 #define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 332                                 "root=/dev/mtdblock5 " \
 333                                 "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
 334                                 "rw rootfstype=jffs2"
 335
 336 #endif
 337
 338 #define CONFIG_SYS_PROMPT               "U-Boot> "
 339 #define CONFIG_SYS_CBSIZE               256
 340 #define CONFIG_SYS_MAXARGS              16
 341 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 342 #define CONFIG_SYS_LONGHELP             1
 343 #define CONFIG_CMDLINE_EDITING          1
 344 #define CONFIG_AUTO_COMPLETE
 345 #define CONFIG_SYS_HUSH_PARSER
 346
 347 /*
 348  * Size of malloc() pool
 349  */
 350 #define CONFIG_SYS_MALLOC_LEN   ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
 351
 352 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 353
 354 #undef CONFIG_USE_IRQ
 355
 356 #endif