include/configs/cm_t35.h

   1 /*
   2  * (C) Copyright 2011 CompuLab, Ltd.
   3  * Mike Rapoport <mike@compulab.co.il>
   4  * Igor Grinberg <grinberg@compulab.co.il>
   5  *
   6  * Based on omap3_beagle.h
   7  * (C) Copyright 2006-2008
   8  * Texas Instruments.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  * Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_OMAP     /* in a TI OMAP core */
  24 #define CONFIG_OMAP34XX /* which is a 34XX */
  25 #define CONFIG_OMAP_GPIO
  26 #define CONFIG_CMD_GPIO
  27 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  28 #define CONFIG_OMAP_COMMON
  29
  30 #define CONFIG_SDRC     /* The chip has SDRC controller */
  31
  32 #include <asm/arch/cpu.h>               /* get chip and board defs */
  33 #include <asm/arch/omap3.h>
  34
  35 /*
  36  * Display CPU and Board information
  37  */
  38 #define CONFIG_DISPLAY_CPUINFO
  39 #define CONFIG_DISPLAY_BOARDINFO
  40
  41 /* Clock Defines */
  42 #define V_OSCK                  26000000        /* Clock output from T2 */
  43 #define V_SCLK                  (V_OSCK >> 1)
  44
  45 #define CONFIG_MISC_INIT_R
  46
  47 #define CONFIG_OF_LIBFDT                1
  48 /*
  49  * The early kernel mapping on ARM currently only maps from the base of DRAM
  50  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
  51  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
  52  * so that leaves DRAM base to DRAM base + 0x4000 available.
  53  */
  54 #define CONFIG_SYS_BOOTMAPSZ            0x4000
  55
  56 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  57 #define CONFIG_SETUP_MEMORY_TAGS
  58 #define CONFIG_INITRD_TAG
  59 #define CONFIG_REVISION_TAG
  60 #define CONFIG_SERIAL_TAG
  61
  62 /*
  63  * Size of malloc() pool
  64  */
  65 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  66                                         /* Sector */
  67 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  68
  69 /*
  70  * Hardware drivers
  71  */
  72
  73 /*
  74  * NS16550 Configuration
  75  */
  76 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  77
  78 #define CONFIG_SYS_NS16550
  79 #define CONFIG_SYS_NS16550_SERIAL
  80 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  81 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  82
  83 /*
  84  * select serial console configuration
  85  */
  86 #define CONFIG_CONS_INDEX               3
  87 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  88 #define CONFIG_SERIAL3                  3       /* UART3 */
  89
  90 /* allow to overwrite serial and ethaddr */
  91 #define CONFIG_ENV_OVERWRITE
  92 #define CONFIG_BAUDRATE                 115200
  93 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  94                                         115200}
  95
  96 #define CONFIG_GENERIC_MMC
  97 #define CONFIG_MMC
  98 #define CONFIG_OMAP_HSMMC
  99 #define CONFIG_DOS_PARTITION
 100
 101 /* USB */
 102 #define CONFIG_USB_OMAP3
 103 #define CONFIG_USB_EHCI
 104 #define CONFIG_USB_EHCI_OMAP
 105 #define CONFIG_USB_STORAGE
 106 #define CONFIG_MUSB_UDC
 107 #define CONFIG_TWL4030_USB
 108 #define CONFIG_CMD_USB
 109
 110 /* USB device configuration */
 111 #define CONFIG_USB_DEVICE
 112 #define CONFIG_USB_TTY
 113 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 114 /* This delay is really for slow-to-power-on USB sticks, not the hub */
 115 #define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500
 116
 117 /* commands to include */
 118 #include <config_cmd_default.h>
 119
 120 #define CONFIG_CMD_CACHE
 121 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 122 #define CONFIG_CMD_FAT          /* FAT support                  */
 123 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
 124 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 125 #define CONFIG_MTD_PARTITIONS
 126 #define MTDIDS_DEFAULT          "nand0=nand"
 127 #define MTDPARTS_DEFAULT        "mtdparts=nand:512k(x-loader),"\
 128                                 "1920k(u-boot),256k(u-boot-env),"\
 129                                 "4m(kernel),-(fs)"
 130
 131 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 132 #define CONFIG_CMD_MMC          /* MMC support                  */
 133 #define CONFIG_CMD_NAND         /* NAND support                 */
 134 #define CONFIG_CMD_DHCP
 135 #define CONFIG_CMD_PING
 136
 137 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 138 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 139 #undef CONFIG_CMD_IMLS          /* List all found images        */
 140
 141 #define CONFIG_SYS_NO_FLASH
 142 #define CONFIG_SYS_I2C
 143 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 144 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 145 #define CONFIG_SYS_I2C_OMAP34XX
 146 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 148 #define CONFIG_I2C_MULTI_BUS
 149
 150 /*
 151  * TWL4030
 152  */
 153 #define CONFIG_TWL4030_POWER
 154 #define CONFIG_TWL4030_LED
 155
 156 /*
 157  * Board NAND Info.
 158  */
 159 #define CONFIG_SYS_NAND_QUIET_TEST
 160 #define CONFIG_NAND_OMAP_GPMC
 161 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 162                                                         /* to access nand */
 163 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 164                                                         /* to access nand at */
 165                                                         /* CS0 */
 166 #define GPMC_NAND_ECC_LP_x8_LAYOUT
 167
 168 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 169                                                         /* devices */
 170 /* Environment information */
 171 #define CONFIG_BOOTDELAY                3
 172 #define CONFIG_ZERO_BOOTDELAY_CHECK
 173
 174 #define CONFIG_EXTRA_ENV_SETTINGS \
 175         "loadaddr=0x82000000\0" \
 176         "usbtty=cdc_acm\0" \
 177         "console=ttyO2,115200n8\0" \
 178         "mpurate=500\0" \
 179         "vram=12M\0" \
 180         "dvimode=1024x768MR-16@60\0" \
 181         "defaultdisplay=dvi\0" \
 182         "mmcdev=0\0" \
 183         "mmcroot=/dev/mmcblk0p2 rw\0" \
 184         "mmcrootfstype=ext4 rootwait\0" \
 185         "nandroot=/dev/mtdblock4 rw\0" \
 186         "nandrootfstype=ubifs\0" \
 187         "mmcargs=setenv bootargs console=${console} " \
 188                 "mpurate=${mpurate} " \
 189                 "vram=${vram} " \
 190                 "omapfb.mode=dvi:${dvimode} " \
 191                 "omapdss.def_disp=${defaultdisplay} " \
 192                 "root=${mmcroot} " \
 193                 "rootfstype=${mmcrootfstype}\0" \
 194         "nandargs=setenv bootargs console=${console} " \
 195                 "mpurate=${mpurate} " \
 196                 "vram=${vram} " \
 197                 "omapfb.mode=dvi:${dvimode} " \
 198                 "omapdss.def_disp=${defaultdisplay} " \
 199                 "root=${nandroot} " \
 200                 "rootfstype=${nandrootfstype}\0" \
 201         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 202         "bootscript=echo Running bootscript from mmc ...; " \
 203                 "source ${loadaddr}\0" \
 204         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 205         "mmcboot=echo Booting from mmc ...; " \
 206                 "run mmcargs; " \
 207                 "bootm ${loadaddr}\0" \
 208         "nandboot=echo Booting from nand ...; " \
 209                 "run nandargs; " \
 210                 "nand read ${loadaddr} 2a0000 400000; " \
 211                 "bootm ${loadaddr}\0" \
 212
 213 #define CONFIG_CMD_BOOTZ
 214 #define CONFIG_BOOTCOMMAND \
 215         "mmc dev ${mmcdev}; if mmc rescan; then " \
 216                 "if run loadbootscript; then " \
 217                         "run bootscript; " \
 218                 "else " \
 219                         "if run loaduimage; then " \
 220                                 "run mmcboot; " \
 221                         "else run nandboot; " \
 222                         "fi; " \
 223                 "fi; " \
 224         "else run nandboot; fi"
 225
 226 /*
 227  * Miscellaneous configurable options
 228  */
 229 #define CONFIG_AUTO_COMPLETE
 230 #define CONFIG_CMDLINE_EDITING
 231 #define CONFIG_TIMESTAMP
 232 #define CONFIG_SYS_AUTOLOAD             "no"
 233 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 234 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 235 #define CONFIG_SYS_PROMPT               "CM-T3x # "
 236 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 237 /* Print Buffer Size */
 238 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 239                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 240 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 241 /* Boot Argument Buffer Size */
 242 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 243
 244 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 245                                                                 /* works on */
 246 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 247                                         0x01F00000) /* 31MB */
 248
 249 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 250                                                         /* load address */
 251
 252 /*
 253  * OMAP3 has 12 GP timers, they can be driven by the system clock
 254  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 255  * This rate is divided by a local divisor.
 256  */
 257 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 258 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 259
 260 /*-----------------------------------------------------------------------
 261  * Physical Memory Map
 262  */
 263 #define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 264 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 265
 266 /*-----------------------------------------------------------------------
 267  * FLASH and environment organization
 268  */
 269
 270 /* **** PISMO SUPPORT *** */
 271 /* Configure the PISMO */
 272 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 273
 274 /* Monitor at start of flash */
 275 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 276 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 277
 278 #define CONFIG_ENV_IS_IN_NAND
 279 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 280 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 281 #define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 282
 283 #if defined(CONFIG_CMD_NET)
 284 #define CONFIG_SMC911X
 285 #define CONFIG_SMC911X_32_BIT
 286 #define CM_T3X_SMC911X_BASE     0x2C000000
 287 #define SB_T35_SMC911X_BASE     (CM_T3X_SMC911X_BASE + (16 << 20))
 288 #define CONFIG_SMC911X_BASE     CM_T3X_SMC911X_BASE
 289 #endif /* (CONFIG_CMD_NET) */
 290
 291 /* additions for new relocation code, must be added to all boards */
 292 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 293 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 294 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 295 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 296                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 297                                          GENERATED_GBL_DATA_SIZE)
 298
 299 /* Status LED */
 300 #define CONFIG_STATUS_LED               /* Status LED enabled */
 301 #define CONFIG_BOARD_SPECIFIC_LED
 302 #define CONFIG_GPIO_LED
 303 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 304 #define GREEN_LED_DEV                   0
 305 #define STATUS_LED_BIT                  GREEN_LED_GPIO
 306 #define STATUS_LED_STATE                STATUS_LED_ON
 307 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 308 #define STATUS_LED_BOOT                 GREEN_LED_DEV
 309
 310 #define CONFIG_SPLASHIMAGE_GUARD
 311
 312 /* GPIO banks */
 313 #ifdef CONFIG_STATUS_LED
 314 #define CONFIG_OMAP3_GPIO_6     /* GPIO186 is in GPIO bank 6  */
 315 #endif
 316
 317 /* Display Configuration */
 318 #define CONFIG_OMAP3_GPIO_2
 319 #define CONFIG_OMAP3_GPIO_5
 320 #define CONFIG_VIDEO_OMAP3
 321 #define LCD_BPP         LCD_COLOR16
 322
 323 #define CONFIG_LCD
 324 #define CONFIG_SPLASH_SCREEN
 325 #define CONFIG_CMD_BMP
 326 #define CONFIG_BMP_16BPP
 327 #define CONFIG_SCF0403_LCD
 328
 329 #define CONFIG_OMAP3_SPI
 330
 331 /* Defines for SPL */
 332 #define CONFIG_SPL
 333 #define CONFIG_SPL_FRAMEWORK
 334 #define CONFIG_SPL_NAND_SIMPLE
 335
 336 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 337 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
 338 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 339 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
 340
 341 #define CONFIG_SPL_BOARD_INIT
 342 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 343 #define CONFIG_SPL_LIBDISK_SUPPORT
 344 #define CONFIG_SPL_I2C_SUPPORT
 345 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 346 #define CONFIG_SPL_MMC_SUPPORT
 347 #define CONFIG_SPL_FAT_SUPPORT
 348 #define CONFIG_SPL_SERIAL_SUPPORT
 349 #define CONFIG_SPL_NAND_SUPPORT
 350 #define CONFIG_SPL_NAND_BASE
 351 #define CONFIG_SPL_NAND_DRIVERS
 352 #define CONFIG_SPL_NAND_ECC
 353 #define CONFIG_SPL_GPIO_SUPPORT
 354 #define CONFIG_SPL_POWER_SUPPORT
 355 #define CONFIG_SPL_OMAP3_ID_NAND
 356 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 357
 358 /* NAND boot config */
 359 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 360 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 361 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 362 #define CONFIG_SYS_NAND_OOBSIZE         64
 363 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 364 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 365 /*
 366  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 367  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 368  */
 369 #define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 370                                          10, 11, 12 }
 371 #define CONFIG_SYS_NAND_ECCSIZE         512
 372 #define CONFIG_SYS_NAND_ECCBYTES        3
 373 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 374
 375 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 376 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 377
 378 #define CONFIG_SPL_TEXT_BASE            0x40200800
 379 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
 380 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 381
 382 /*
 383  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 384  * older x-loader implementations. And move the BSS area so that it
 385  * doesn't overlap with TEXT_BASE.
 386  */
 387 #define CONFIG_SYS_TEXT_BASE            0x80008000
 388 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 389 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 390
 391 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 392 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 393
 394 #endif /* __CONFIG_H */