include/configs/cpu9260.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * (C) Copyright 2009
   8  * Eric Benard <eric@eukrea.com>
   9  *
  10  * Configuration settings for the Eukrea CPU9260 board.
  11  *
  12  * See file CREDITS for list of people who contributed to this
  13  * project.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License as
  17  * published by the Free Software Foundation; either version 2 of
  18  * the License, or (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28  * MA 02111-1307 USA
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /* to be removed once maemory-map.h is fixed */
  35 #define AT91_BASE_SYS   0xffffe800
  36 #define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
  37
  38 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000
  39 #define CONFIG_SYS_HZ           1000
  40 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768
  41
  42 #if defined(CONFIG_CPU9G20)
  43 #define CONFIG_AT91SAM9G20
  44 #elif defined(CONFIG_CPU9260)
  45 #define CONFIG_AT91SAM9260
  46 #else
  47 #error "Unknown board"
  48 #endif
  49
  50 #include <asm/arch/hardware.h>
  51
  52 #define CONFIG_AT91FAMILY
  53 #define CONFIG_ARCH_CPU_INIT
  54 #define CONFIG_DISPLAY_CPUINFO
  55 #define CONFIG_BOARD_EARLY_INIT_F
  56
  57 #define CONFIG_CMDLINE_TAG
  58 #define CONFIG_SETUP_MEMORY_TAGS
  59 #define CONFIG_INITRD_TAG
  60
  61 #if defined(CONFIG_NANDBOOT)
  62 #define CONFIG_SKIP_LOWLEVEL_INIT
  63 #define CONFIG_SYS_TEXT_BASE           0x23f00000
  64 #else
  65 #define CONFIG_SYS_TEXT_BASE           0x00000000
  66 #endif
  67
  68 /* clocks */
  69 #if defined(CONFIG_CPU9G20)
  70 #define MASTER_PLL_DIV          0x01
  71 #define MASTER_PLL_MUL          0x2B
  72 #elif defined(CONFIG_CPU9260)
  73 #define MASTER_PLL_DIV          0x09
  74 #define MASTER_PLL_MUL          0x61
  75 #endif
  76
  77 /* CKGR_MOR - enable main osc. */
  78 #define CONFIG_SYS_MOR_VAL                                              \
  79                 (AT91_PMC_MOSCEN |                                      \
  80                  (255 << 8))            /* Main Oscillator Start-up Time */
  81 #if defined(CONFIG_CPU9G20)
  82 #define CONFIG_SYS_PLLAR_VAL                                            \
  83                 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
  84                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  85 #elif defined(CONFIG_CPU9260)
  86 #define CONFIG_SYS_PLLAR_VAL                                            \
  87                 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
  88                  AT91_PMC_OUT |                                         \
  89                  ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
  90 #endif
  91
  92 #if defined(CONFIG_CPU9G20)
  93 #define CONFIG_SYS_MCKR1_VAL            \
  94                 (AT91_PMC_CSS_PLLA |    \
  95                  AT91_PMC_PRES_1 |      \
  96                  AT91SAM9_PMC_MDIV_6 |  \
  97                  AT91_PMC_PDIV_2)
  98 #define CONFIG_SYS_MCKR2_VAL            \
  99                 CONFIG_SYS_MCKR1_VAL
 100 #elif defined(CONFIG_CPU9260)
 101 #define CONFIG_SYS_MCKR1_VAL            \
 102                 (AT91_PMC_CSS_SLOW |    \
 103                  AT91_PMC_PRES_1 |      \
 104                  AT91SAM9_PMC_MDIV_2 |  \
 105                  AT91_PMC_PDIV_1)
 106 #define CONFIG_SYS_MCKR2_VAL            \
 107                 (AT91_PMC_CSS_PLLA |    \
 108                  AT91_PMC_PRES_1 |      \
 109                  AT91SAM9_PMC_MDIV_2 |  \
 110                  AT91_PMC_PDIV_1)
 111 #endif
 112
 113 /* define PDC[31:16] as DATA[31:16] */
 114 #define CONFIG_SYS_PIOC_PDR_VAL1        0xFFFF0000
 115 /* no pull-up for D[31:16] */
 116 #define CONFIG_SYS_PIOC_PPUDR_VAL       0xFFFF0000
 117
 118 /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
 119 #define CONFIG_SYS_MATRIX_EBICSA_VAL            \
 120                 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
 121                 AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
 122
 123 /* SDRAM */
 124 /* SDRAMC_MR Mode register */
 125 #define CONFIG_SYS_SDRC_MR_VAL1         AT91_SDRAMC_MODE_NORMAL
 126 /* SDRAMC_TR - Refresh Timer register */
 127 #define CONFIG_SYS_SDRC_TR_VAL1         0x287
 128 /* SDRAMC_CR - Configuration register*/
 129 #if defined(CONFIG_CPU9G20)
 130 #define CONFIG_SYS_SDRC_CR_VAL_64MB                                     \
 131                 (AT91_SDRAMC_NC_9 |                                     \
 132                  AT91_SDRAMC_NR_13 |                                    \
 133                  AT91_SDRAMC_NB_4 |                                     \
 134                  AT91_SDRAMC_CAS_2 |                                    \
 135                  AT91_SDRAMC_DBW_32 |                                   \
 136                  (2 <<  8) |    /* Write Recovery Delay */              \
 137                  (9 << 12) |    /* Row Cycle Delay */                   \
 138                  (3 << 16) |    /* Row Precharge Delay */               \
 139                  (3 << 20) |    /* Row to Column Delay */               \
 140                  (6 << 24) |    /* Active to Precharge Delay */         \
 141                  (10 << 28))    /* Exit Self Refresh to Active Delay */
 142
 143 #define CONFIG_SYS_SDRC_CR_VAL_128MB                                    \
 144                 (AT91_SDRAMC_NC_10 |                                    \
 145                  AT91_SDRAMC_NR_13 |                                    \
 146                  AT91_SDRAMC_NB_4 |                                     \
 147                  AT91_SDRAMC_CAS_2 |                                    \
 148                  AT91_SDRAMC_DBW_32 |                                   \
 149                  (2 <<  8) |    /* Write Recovery Delay */              \
 150                  (9 << 12) |    /* Row Cycle Delay */                   \
 151                  (3 << 16) |    /* Row Precharge Delay */               \
 152                  (3 << 20) |    /* Row to Column Delay */               \
 153                  (6 << 24) |    /* Active to Precharge Delay */         \
 154                  (10 << 28))    /* Exit Self Refresh to Active Delay */
 155 #elif defined(CONFIG_CPU9260)
 156 #define CONFIG_SYS_SDRC_CR_VAL_64MB                                     \
 157                 (AT91_SDRAMC_NC_9 |                                     \
 158                  AT91_SDRAMC_NR_13 |                                    \
 159                  AT91_SDRAMC_NB_4 |                                     \
 160                  AT91_SDRAMC_CAS_2 |                                    \
 161                  AT91_SDRAMC_DBW_32 |                                   \
 162                  (2 <<  8) |    /* Write Recovery Delay */              \
 163                  (7 << 12) |    /* Row Cycle Delay */                   \
 164                  (2 << 16) |    /* Row Precharge Delay */               \
 165                  (2 << 20) |    /* Row to Column Delay */               \
 166                  (5 << 24) |    /* Active to Precharge Delay */         \
 167                  (8 << 28))     /* Exit Self Refresh to Active Delay */
 168
 169 #define CONFIG_SYS_SDRC_CR_VAL_128MB                                    \
 170                 (AT91_SDRAMC_NC_10 |                                    \
 171                  AT91_SDRAMC_NR_13 |                                    \
 172                  AT91_SDRAMC_NB_4 |                                     \
 173                  AT91_SDRAMC_CAS_2 |                                    \
 174                  AT91_SDRAMC_DBW_32 |                                   \
 175                  (2 <<  8) |    /* Write Recovery Delay */              \
 176                  (7 << 12) |    /* Row Cycle Delay */                   \
 177                  (2 << 16) |    /* Row Precharge Delay */               \
 178                  (2 << 20) |    /* Row to Column Delay */               \
 179                  (5 << 24) |    /* Active to Precharge Delay */         \
 180                  (8 << 28))     /* Exit Self Refresh to Active Delay */
 181 #endif
 182
 183 /* Memory Device Register -> SDRAM */
 184 #define CONFIG_SYS_SDRC_MDR_VAL         AT91_SDRAMC_MD_SDRAM
 185 #define CONFIG_SYS_SDRC_MR_VAL2         AT91_SDRAMC_MODE_PRECHARGE
 186 #define CONFIG_SYS_SDRAM_VAL1           0               /* SDRAM_BASE */
 187 #define CONFIG_SYS_SDRC_MR_VAL3         AT91_SDRAMC_MODE_REFRESH
 188 #define CONFIG_SYS_SDRAM_VAL2           0               /* SDRAM_BASE */
 189 #define CONFIG_SYS_SDRAM_VAL3           0               /* SDRAM_BASE */
 190 #define CONFIG_SYS_SDRAM_VAL4           0               /* SDRAM_BASE */
 191 #define CONFIG_SYS_SDRAM_VAL5           0               /* SDRAM_BASE */
 192 #define CONFIG_SYS_SDRAM_VAL6           0               /* SDRAM_BASE */
 193 #define CONFIG_SYS_SDRAM_VAL7           0               /* SDRAM_BASE */
 194 #define CONFIG_SYS_SDRAM_VAL8           0               /* SDRAM_BASE */
 195 #define CONFIG_SYS_SDRAM_VAL9           0               /* SDRAM_BASE */
 196 #define CONFIG_SYS_SDRC_MR_VAL4         AT91_SDRAMC_MODE_LMR
 197 #define CONFIG_SYS_SDRAM_VAL10          0               /* SDRAM_BASE */
 198 #define CONFIG_SYS_SDRC_MR_VAL5         AT91_SDRAMC_MODE_NORMAL
 199 #define CONFIG_SYS_SDRAM_VAL11          0               /* SDRAM_BASE */
 200 #define CONFIG_SYS_SDRC_TR_VAL2         1200            /* SDRAM_TR */
 201 #define CONFIG_SYS_SDRAM_VAL12          0               /* SDRAM_BASE */
 202
 203 /* setup SMC0, CS0 (NOR Flash) - 16-bit */
 204 #if defined(CONFIG_CPU9G20)
 205 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 206                 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |     \
 207                  AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
 208 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 209                 (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) |     \
 210                  AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
 211 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 212                 (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
 213 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 214                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 215                  AT91_SMC_MODE_DBW_16 |                         \
 216                  AT91_SMC_MODE_TDF |                            \
 217                  AT91_SMC_MODE_TDF_CYCLE(3))
 218 #elif defined(CONFIG_CPU9260)
 219 #define CONFIG_SYS_SMC0_SETUP0_VAL                                      \
 220                 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |     \
 221                  AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
 222 #define CONFIG_SYS_SMC0_PULSE0_VAL                                      \
 223                 (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) |     \
 224                  AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
 225 #define CONFIG_SYS_SMC0_CYCLE0_VAL      \
 226                 (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
 227 #define CONFIG_SYS_SMC0_MODE0_VAL                               \
 228                 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |  \
 229                  AT91_SMC_MODE_DBW_16 |                         \
 230                  AT91_SMC_MODE_TDF |                            \
 231                  AT91_SMC_MODE_TDF_CYCLE(2))
 232 #endif
 233
 234 /* user reset enable */
 235 #define CONFIG_SYS_RSTC_RMR_VAL                 \
 236                 (AT91_RSTC_KEY |                \
 237                 AT91_RSTC_CR_PROCRST |          \
 238                 AT91_RSTC_MR_ERSTL(1) | \
 239                 AT91_RSTC_MR_ERSTL(2))
 240
 241 /* Disable Watchdog */
 242 #define CONFIG_SYS_WDTC_WDMR_VAL                                \
 243                 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
 244                  AT91_WDT_MR_WDV(0xfff) |                       \
 245                  AT91_WDT_MR_WDDIS |                            \
 246                  AT91_WDT_MR_WDD(0xfff))
 247
 248 /*
 249  * Hardware drivers
 250  */
 251 #define CONFIG_AT91SAM9_WATCHDOG
 252 #define CONFIG_AT91_GPIO
 253 #define CONFIG_ATMEL_USART
 254 #define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 255 #define CONFIG_USART_ID         ATMEL_ID_SYS
 256
 257 #define CONFIG_BOOTDELAY        3
 258
 259 /*
 260  * BOOTP options
 261  */
 262 #define CONFIG_BOOTP_BOOTFILESIZE
 263 #define CONFIG_BOOTP_BOOTPATH
 264 #define CONFIG_BOOTP_GATEWAY
 265 #define CONFIG_BOOTP_HOSTNAME
 266
 267 /*
 268  * Command line configuration.
 269  */
 270 #include <config_cmd_default.h>
 271 #undef CONFIG_CMD_BDI
 272 #undef CONFIG_CMD_IMI
 273 #undef CONFIG_CMD_FPGA
 274 #undef CONFIG_CMD_LOADS
 275 #undef CONFIG_CMD_IMLS
 276
 277 #define CONFIG_CMD_PING
 278 #define CONFIG_CMD_DHCP
 279 #define CONFIG_CMD_NAND
 280 #define CONFIG_CMD_USB
 281 #define CONFIG_CMD_FAT
 282 #define CONFIG_CMD_MII
 283
 284 /* SDRAM */
 285 #define CONFIG_NR_DRAM_BANKS    1
 286 #define CONFIG_SYS_SDRAM_BASE           0x20000000
 287 #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
 288 #define CONFIG_SYS_SDRAM_SIZE           (128 * 1024 * 1024)
 289 #define CONFIG_SYS_SDRC_CR_VAL  CONFIG_SYS_SDRC_CR_VAL_128MB
 290 #else
 291 #define CONFIG_SYS_SDRAM_SIZE           (64 * 1024 * 1024)
 292 #define CONFIG_SYS_SDRC_CR_VAL  CONFIG_SYS_SDRC_CR_VAL_64MB
 293 #endif
 294
 295 /* NAND flash */
 296 #define CONFIG_NAND_ATMEL
 297 #define CONFIG_SYS_MAX_NAND_DEVICE              1
 298 #define CONFIG_SYS_NAND_BASE                    0x40000000
 299 #define CONFIG_SYS_NAND_DBW_8                   1
 300 #define CONFIG_SYS_NAND_READY_PIN               AT91_PIO_PORTC, 13
 301 #define CONFIG_SYS_NAND_ENABLE_PIN              AT91_PIO_PORTC, 14
 302 #define CONFIG_SYS_NAND_MASK_ALE                (1 << 21)
 303 #define CONFIG_SYS_NAND_MASK_CLE                (1 << 22)
 304
 305 /* NOR flash */
 306 #if defined(CONFIG_NANDBOOT)
 307 #define CONFIG_SYS_NO_FLASH
 308 #else
 309 #define CONFIG_SYS_FLASH_CFI
 310 #define CONFIG_FLASH_CFI_DRIVER
 311 #define PHYS_FLASH_1                            0x10000000
 312 #define PHYS_FLASH_2                            0x12000000
 313 #define CONFIG_SYS_FLASH_BANKS_LIST             \
 314                 { PHYS_FLASH_1, PHYS_FLASH_2 }
 315 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 316 #define CONFIG_SYS_MAX_FLASH_SECT               (255+4)
 317 #define CONFIG_SYS_MAX_FLASH_BANKS              2
 318 #define CONFIG_SYS_FLASH_CFI_WIDTH              FLASH_CFI_16BIT
 319 #define CONFIG_SYS_FLASH_EMPTY_INFO
 320 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 321 #define CONFIG_SYS_FLASH_PROTECTION
 322 #define CONFIG_SYS_MONITOR_BASE                 PHYS_FLASH_1
 323 #endif
 324
 325 /* Ethernet */
 326 #define CONFIG_MACB
 327 #define CONFIG_RMII
 328 #define CONFIG_NET_RETRY_COUNT                  20
 329 #define CONFIG_MACB_SEARCH_PHY
 330
 331 /* LEDS */
 332 /* Status LED */
 333 #define CONFIG_STATUS_LED
 334 #define CONFIG_BOARD_SPECIFIC_LED
 335 #define STATUS_LED_RED                          0
 336 #define STATUS_LED_GREEN                        1
 337 #define STATUS_LED_YELLOW                       2
 338 #define STATUS_LED_BLUE                         3
 339 /* Red */
 340 #define STATUS_LED_BIT                          STATUS_LED_RED
 341 #define STATUS_LED_STATE                        STATUS_LED_OFF
 342 #define STATUS_LED_PERIOD                       (CONFIG_SYS_HZ / 2)
 343 /* Green */
 344 #define STATUS_LED_BIT1                         STATUS_LED_GREEN
 345 #define STATUS_LED_STATE1                       STATUS_LED_OFF
 346 #define STATUS_LED_PERIOD1                      (CONFIG_SYS_HZ / 2)
 347 /* Yellow */
 348 #define STATUS_LED_BIT2                         STATUS_LED_YELLOW
 349 #define STATUS_LED_STATE2                       STATUS_LED_OFF
 350 #define STATUS_LED_PERIOD2                      (CONFIG_SYS_HZ / 2)
 351 /* Blue */
 352 #define STATUS_LED_BIT3                         STATUS_LED_BLUE
 353 #define STATUS_LED_STATE3                       STATUS_LED_ON
 354 #define STATUS_LED_PERIOD3                      (CONFIG_SYS_HZ / 2)
 355 /* Optional value */
 356 #define STATUS_LED_BOOT                         STATUS_LED_BIT
 357
 358 #define CONFIG_RED_LED                          AT91_PIO_PORTC, 11
 359 #define CONFIG_GREEN_LED                        AT91_PIO_PORTC, 12
 360 #define CONFIG_YELLOW_LED                       AT91_PIO_PORTC, 7
 361 #define CONFIG_BLUE_LED                         AT91_PIO_PORTC, 9
 362
 363 /* USB */
 364 #define CONFIG_USB_ATMEL
 365 #define CONFIG_USB_OHCI_NEW
 366 #define CONFIG_DOS_PARTITION
 367 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 368 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
 369 #if defined(CONFIG_CPU9G20)
 370 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9g20"
 371 #elif defined(CONFIG_CPU9260)
 372 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9260"
 373 #endif
 374 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 375 #define CONFIG_USB_STORAGE
 376
 377 #define CONFIG_SYS_LOAD_ADDR                    0x21000000
 378 #define CONFIG_LOADADDR                         CONFIG_SYS_LOAD_ADDR
 379
 380 #define CONFIG_SYS_MEMTEST_START                CONFIG_SYS_SDRAM_BASE
 381 #define CONFIG_SYS_MEMTEST_END                  \
 382         (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
 383
 384 #if defined(CONFIG_NANDBOOT)
 385 #define CONFIG_SYS_USE_NANDFLASH
 386 #undef CONFIG_SYS_USE_FLASH
 387 #else
 388 #define CONFIG_SYS_USE_FLASH
 389 #undef CONFIG_SYS_USE_NANDFLASH
 390 #endif
 391
 392 #if defined(CONFIG_CPU9G20)
 393 #define CONFIG_SYS_BASEDIR      "cpu9G20"
 394 #elif defined(CONFIG_CPU9260)
 395 #define CONFIG_SYS_BASEDIR      "cpu9260"
 396 #endif
 397
 398 #if defined(CONFIG_SYS_USE_FLASH)
 399 #define CONFIG_ENV_IS_IN_FLASH
 400 #define CONFIG_ENV_OFFSET               0x40000
 401 #define CONFIG_ENV_SECT_SIZE            0x20000
 402 #define CONFIG_ENV_SIZE                 0x20000
 403 #define CONFIG_ENV_OVERWRITE
 404
 405 #define CONFIG_BOOTCOMMAND              "run flashboot"
 406
 407 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=atmel_nand"
 408 #define MTDPARTS_DEFAULT                \
 409         "mtdparts=physmap-flash.0:"     \
 410                 "256k(u-boot)ro,"       \
 411                 "128k(u-boot-env)ro,"   \
 412                 "1792k(kernel),"        \
 413                 "-(rootfs);"            \
 414         "atmel_nand:-(nand)"
 415
 416 #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
 417
 418 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 419         "mtdids=" MTDIDS_DEFAULT "\0"                           \
 420         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
 421         "partition=nand0,0\0"                                   \
 422         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 423         "ramboot=tftpboot 0x22000000 $(basedir)/uImage;"        \
 424                 "run ramargs;bootm 22000000\0"                  \
 425         "flashboot=run ramargs;bootm 0x10060000\0"              \
 426         "basedir=" CONFIG_SYS_BASEDIR "\0"                      \
 427         "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
 428                 "off 0x10000000 0x1003ffff;erase 0x10000000 "   \
 429                 "0x1003ffff;cp.b 0x24000000 0x10000000 "        \
 430                 "$(filesize)\0" \
 431         "updtui=tftp 0x24000000 $(basedir)/uImage;protect off"  \
 432                 " 0x10060000 0x1021ffff;erase 0x10060000 "      \
 433                 "0x1021ffff;cp.b 0x24000000 0x10060000 "        \
 434                 "$(filesize)\0" \
 435         "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; "     \
 436                 "protect off 0x10220000 0x13ffffff;erase "      \
 437                 "0x10220000 0x13ffffff;cp.b 0x24000000 "        \
 438                 "0x10220000 $(filesize)\0" \
 439         ""
 440 #elif defined(CONFIG_NANDBOOT)
 441 #define CONFIG_ENV_IS_IN_NAND
 442 #define CONFIG_ENV_OFFSET               0x60000
 443 #define CONFIG_ENV_OFFSET_REDUND        0x80000
 444 #define CONFIG_ENV_SECT_SIZE            0x20000
 445 #define CONFIG_ENV_SIZE                 0x20000
 446 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 447 #define CONFIG_ENV_OVERWRITE
 448
 449 #define CONFIG_BOOTCOMMAND              "run flashboot"
 450
 451 #define MTDIDS_DEFAULT          "nand0=atmel_nand"
 452 #define MTDPARTS_DEFAULT                \
 453         "mtdparts=atmel_nand:"          \
 454                 "128k(bootstrap)ro,"    \
 455                 "256k(u-boot)ro,"       \
 456                 "128k(u-boot-env)ro,"   \
 457                 "128k(u-boot-env2)ro,"  \
 458                 "2M(kernel),"   \
 459                 "-(rootfs)"
 460
 461 #define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs "      \
 462         "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
 463
 464 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 465         "mtdids=" MTDIDS_DEFAULT "\0"                           \
 466         "mtdparts=" MTDPARTS_DEFAULT "\0"                       \
 467         "partition=nand0,5\0"                                   \
 468         "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"     \
 469         "ramboot=tftpboot 0x22000000 $(basedir)/uImage;"        \
 470                 "run ramargs;bootm 22000000\0"                  \
 471         "flashboot=run ramargs; nand read 0x22000000 0xA0000 "  \
 472                 "0x200000; bootm 0x22000000\0"                  \
 473         "basedir=" CONFIG_SYS_BASEDIR "\0"                      \
 474         "u-boot=u-boot-eukrea-cpu9260.bin\0"                    \
 475         "kernel=uImage-eukrea-cpu9260.bin\0"                    \
 476         "rootfs=image-eukrea-cpu9260.ubi\0"                     \
 477         "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; "        \
 478                 "nand erase 20000 40000; "                      \
 479                 "nand write ${loadaddr} 20000 40000\0"          \
 480         "updtui=tftp ${loadaddr} $(basedir)/${kernel}; "        \
 481                 "nand erase a0000 200000; "                     \
 482                 "nand write ${loadaddr} a0000 200000\0"         \
 483         "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; "       \
 484                 "nand erase  2a0000 fd60000; "                  \
 485                 "nand write ${loadaddr} 2a0000 ${filesize}\0"
 486 #endif
 487
 488 #define CONFIG_BAUDRATE                 115200
 489
 490 #if defined(CONFIG_CPU9G20)
 491 #define CONFIG_SYS_PROMPT               "CPU9G20=> "
 492 #elif defined(CONFIG_CPU9260)
 493 #define CONFIG_SYS_PROMPT               "CPU9260=> "
 494 #endif
 495 #define CONFIG_SYS_CBSIZE               256
 496 #define CONFIG_SYS_MAXARGS              16
 497 #define CONFIG_SYS_PBSIZE               \
 498                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 499 #define CONFIG_SYS_LONGHELP
 500 #define CONFIG_CMDLINE_EDITING
 501 #define CONFIG_SILENT_CONSOLE
 502 #define CONFIG_NETCONSOLE
 503
 504 /*
 505  * Size of malloc() pool
 506  */
 507 #define CONFIG_SYS_MALLOC_LEN           \
 508                 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
 509
 510 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
 511                                 GENERATED_GBL_DATA_SIZE)
 512
 513 #endif