include/configs/eb_cpu5282.h

   1 /*
   2  * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
   3  *
   4  * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef _CONFIG_EB_CPU5282_H_
  10 #define _CONFIG_EB_CPU5282_H_
  11
  12 #undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
  13
  14 /*----------------------------------------------------------------------*
  15  * High Level Configuration Options (easy to change)                    *
  16  *----------------------------------------------------------------------*/
  17
  18 #define CONFIG_MCF52x2                  /* define processor family */
  19 #define CONFIG_M5282                    /* define processor type */
  20
  21 #define CONFIG_MISC_INIT_R
  22
  23 #define CONFIG_MCFUART
  24 #define CONFIG_SYS_UART_PORT            (0)
  25 #define CONFIG_BAUDRATE                 115200
  26
  27 #undef  CONFIG_MONITOR_IS_IN_RAM                /* starts uboot direct */
  28
  29 #define CONFIG_BOOTCOMMAND "printenv"
  30
  31 /*----------------------------------------------------------------------*
  32  * Options                                                              *
  33  *----------------------------------------------------------------------*/
  34
  35 #define CONFIG_BOOT_RETRY_TIME  -1
  36 #define CONFIG_RESET_TO_RETRY
  37 #define CONFIG_SPLASH_SCREEN
  38
  39 #define CONFIG_HW_WATCHDOG
  40
  41 #define CONFIG_STATUS_LED
  42 #define CONFIG_BOARD_SPECIFIC_LED
  43 #define STATUS_LED_ACTIVE               0
  44 #define STATUS_LED_BIT                  0x0008  /* Timer7 GPIO */
  45 #define STATUS_LED_BOOT                 0
  46 #define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
  47 #define STATUS_LED_STATE                STATUS_LED_OFF
  48
  49 /*----------------------------------------------------------------------*
  50  * Configuration for environment                                        *
  51  * Environment is in the second sector of the first 256k of flash       *
  52  *----------------------------------------------------------------------*/
  53
  54 #define CONFIG_ENV_ADDR         0xFF040000
  55 #define CONFIG_ENV_SECT_SIZE    0x00020000
  56 #define CONFIG_ENV_IS_IN_FLASH  1
  57
  58 /*
  59  * BOOTP options
  60  */
  61 #define CONFIG_BOOTP_BOOTFILESIZE
  62 #define CONFIG_BOOTP_BOOTPATH
  63 #define CONFIG_BOOTP_GATEWAY
  64 #define CONFIG_BOOTP_HOSTNAME
  65
  66 /*
  67  * Command line configuration.
  68  */
  69 #define CONFIG_CMDLINE_EDITING
  70 #include <config_cmd_default.h>
  71
  72 #undef CONFIG_CMD_LOADB
  73 #define CONFIG_CMD_DATE
  74 #define CONFIG_CMD_DHCP
  75 #define CONFIG_CMD_I2C
  76 #define CONFIG_CMD_LED
  77 #define CONFIG_CMD_MII
  78 #define CONFIG_CMD_NET
  79
  80 #define CONFIG_MCFTMR
  81
  82 #define CONFIG_BOOTDELAY        5
  83 #define CONFIG_SYS_PROMPT       "\nEB+CPU5282> "
  84 #define CONFIG_SYS_LONGHELP     1
  85
  86 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size      */
  87 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  88 #define CONFIG_SYS_MAXARGS      16      /* max number of command args   */
  89 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  90
  91 #define CONFIG_SYS_LOAD_ADDR            0x20000
  92
  93 #define CONFIG_SYS_MEMTEST_START        0x100000
  94 #define CONFIG_SYS_MEMTEST_END          0x400000
  95 /*#define CONFIG_SYS_DRAM_TEST          1 */
  96 #undef CONFIG_SYS_DRAM_TEST
  97
  98 /*----------------------------------------------------------------------*
  99  * Clock and PLL Configuration                                          *
 100  *----------------------------------------------------------------------*/
 101 #define CONFIG_SYS_HZ                   1000
 102 #define CONFIG_SYS_CLK                  80000000      /* 8MHz * 8 */
 103
 104 /* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
 105
 106 #define CONFIG_SYS_MFD          0x02    /* PLL Multiplication Factor Devider */
 107 #define CONFIG_SYS_RFD          0x00    /* PLL Reduce Frecuency Devider */
 108
 109 /*----------------------------------------------------------------------*
 110  * Network                                                              *
 111  *----------------------------------------------------------------------*/
 112
 113 #define CONFIG_MCFFEC
 114 #define CONFIG_MII                      1
 115 #define CONFIG_MII_INIT                 1
 116 #define CONFIG_SYS_DISCOVER_PHY
 117 #define CONFIG_SYS_RX_ETH_BUFFER        8
 118 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 119
 120 #define CONFIG_SYS_FEC0_PINMUX          0
 121 #define CONFIG_SYS_FEC0_MIIBASE         CONFIG_SYS_FEC0_IOBASE
 122 #define MCFFEC_TOUT_LOOP                50000
 123
 124 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 125
 126 /*-------------------------------------------------------------------------
 127  * Low Level Configuration Settings
 128  * (address mappings, register initial values, etc.)
 129  * You should know what you are doing if you make changes here.
 130  *-----------------------------------------------------------------------*/
 131
 132 #define CONFIG_SYS_MBAR                 0x40000000
 133
 134 /*-----------------------------------------------------------------------
 135  * Definitions for initial stack pointer and data area (in DPRAM)
 136  *-----------------------------------------------------------------------*/
 137
 138 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 139 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 140 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 141         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 142 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 143
 144 /*-----------------------------------------------------------------------
 145  * Start addresses for the final memory configuration
 146  * (Set up by the startup code)
 147  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 148  */
 149 #define CONFIG_SYS_SDRAM_BASE0          0x00000000
 150 #define CONFIG_SYS_SDRAM_SIZE0          16      /* SDRAM size in MB */
 151
 152 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_SDRAM_BASE0
 153 #define CONFIG_SYS_SDRAM_SIZE           CONFIG_SYS_SDRAM_SIZE0
 154
 155 #define CONFIG_SYS_MONITOR_LEN          0x20000
 156 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)
 157 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 158
 159 /*
 160  * For booting Linux, the board info and command line data
 161  * have to be in the first 8 MB of memory, since this is
 162  * the maximum mapped by the Linux kernel during initialization ??
 163  */
 164 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20) /* Initial Memory map for Linux */
 165
 166 /*-----------------------------------------------------------------------
 167  * FLASH organization
 168  */
 169 #define CONFIG_FLASH_SHOW_PROGRESS      45
 170
 171 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 172 #define CONFIG_SYS_INT_FLASH_BASE       0xF0000000
 173 #define CONFIG_SYS_INT_FLASH_ENABLE     0x21
 174
 175 #define CONFIG_SYS_MAX_FLASH_SECT       128
 176 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 177 #define CONFIG_SYS_FLASH_ERASE_TOUT     10000000
 178 #define CONFIG_SYS_FLASH_PROTECTION
 179
 180 #define CONFIG_SYS_FLASH_CFI
 181 #define CONFIG_FLASH_CFI_DRIVER
 182 #define CONFIG_SYS_FLASH_SIZE           16*1024*1024
 183 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 184
 185 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 186
 187 /*-----------------------------------------------------------------------
 188  * Cache Configuration
 189  */
 190 #define CONFIG_SYS_CACHELINE_SIZE       16
 191
 192 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 193                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 194 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 195                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 196 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV + CF_CACR_DCM)
 197 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 198                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 199                                          CF_ACR_EN | CF_ACR_SM_ALL)
 200 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 201                                          CF_CACR_CEIB | CF_CACR_DBWE | \
 202                                          CF_CACR_EUSP)
 203
 204 /*-----------------------------------------------------------------------
 205  * Memory bank definitions
 206  */
 207
 208 #define CONFIG_SYS_CS0_BASE             0xFF000000
 209 #define CONFIG_SYS_CS0_CTRL             0x00001980
 210 #define CONFIG_SYS_CS0_MASK             0x00FF0001
 211
 212 #define CONFIG_SYS_CS2_BASE             0xE0000000
 213 #define CONFIG_SYS_CS2_CTRL             0x00001980
 214 #define CONFIG_SYS_CS2_MASK             0x000F0001
 215
 216 #define CONFIG_SYS_CS3_BASE             0xE0100000
 217 #define CONFIG_SYS_CS3_CTRL             0x00001980
 218 #define CONFIG_SYS_CS3_MASK             0x000F0001
 219
 220 /*-----------------------------------------------------------------------
 221  * Port configuration
 222  */
 223 #define CONFIG_SYS_PACNT                0x0000000       /* Port A D[31:24] */
 224 #define CONFIG_SYS_PADDR                0x0000000
 225 #define CONFIG_SYS_PADAT                0x0000000
 226
 227 #define CONFIG_SYS_PBCNT                0x0000000       /* Port B D[23:16] */
 228 #define CONFIG_SYS_PBDDR                0x0000000
 229 #define CONFIG_SYS_PBDAT                0x0000000
 230
 231 #define CONFIG_SYS_PCCNT                0x0000000       /* Port C D[15:08] */
 232 #define CONFIG_SYS_PCDDR                0x0000000
 233 #define CONFIG_SYS_PCDAT                0x0000000
 234
 235 #define CONFIG_SYS_PDCNT                0x0000000       /* Port D D[07:00] */
 236 #define CONFIG_SYS_PCDDR                0x0000000
 237 #define CONFIG_SYS_PCDAT                0x0000000
 238
 239 #define CONFIG_SYS_PASPAR               0x0F0F
 240 #define CONFIG_SYS_PEHLPAR              0xC0
 241 #define CONFIG_SYS_PUAPAR               0x0F
 242 #define CONFIG_SYS_DDRUA                0x05
 243 #define CONFIG_SYS_PJPAR                0xFF
 244
 245 /*-----------------------------------------------------------------------
 246  * I2C
 247  */
 248
 249 #define CONFIG_SYS_I2C
 250 #define CONFIG_SYS_I2C_FSL
 251
 252 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
 253 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
 254
 255 #define CONFIG_SYS_FSL_I2C_SPEED        100000
 256 #define CONFIG_SYS_FSL_I2C_SLAVE        0
 257
 258 #ifdef CONFIG_CMD_DATE
 259 #define CONFIG_RTC_DS1338
 260 #define CONFIG_I2C_RTC_ADDR             0x68
 261 #endif
 262
 263 /*-----------------------------------------------------------------------
 264  * VIDEO configuration
 265  */
 266
 267 #define CONFIG_VIDEO
 268
 269 #ifdef CONFIG_VIDEO
 270 #define CONFIG_VIDEO_VCXK                       1
 271
 272 #define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       2
 273 #define CONFIG_SYS_VCXK_DOUBLEBUFFERED          1
 274 #define CONFIG_SYS_VCXK_BASE                    CONFIG_SYS_CS2_BASE
 275
 276 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        MCFGPTB_GPTPORT
 277 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         MCFGPTB_GPTDDR
 278 #define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         0x0001
 279
 280 #define CONFIG_SYS_VCXK_ENABLE_PORT             MCFGPTB_GPTPORT
 281 #define CONFIG_SYS_VCXK_ENABLE_DDR              MCFGPTB_GPTDDR
 282 #define CONFIG_SYS_VCXK_ENABLE_PIN              0x0002
 283
 284 #define CONFIG_SYS_VCXK_REQUEST_PORT            MCFGPTB_GPTPORT
 285 #define CONFIG_SYS_VCXK_REQUEST_DDR             MCFGPTB_GPTDDR
 286 #define CONFIG_SYS_VCXK_REQUEST_PIN             0x0004
 287
 288 #define CONFIG_SYS_VCXK_INVERT_PORT             MCFGPIO_PORTE
 289 #define CONFIG_SYS_VCXK_INVERT_DDR              MCFGPIO_DDRE
 290 #define CONFIG_SYS_VCXK_INVERT_PIN              MCFGPIO_PORT2
 291
 292 #endif /* CONFIG_VIDEO */
 293 #endif  /* _CONFIG_M5282EVB_H */
 294 /*---------------------------------------------------------------------*/