include/configs/enbw_cmc.h

   1 /*
   2  * (C) Copyright 2011
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * Based on:
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  *
   8  * Based on davinci_dvevm.h. Original Copyrights follow:
   9  *
  10  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * Board
  20  */
  21 #define CONFIG_DRIVER_TI_EMAC
  22 #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
  23 #define CONFIG_USE_NAND
  24
  25 /*
  26  * SoC Configuration
  27  */
  28 #define CONFIG_SOC_DA8XX                /* TI DA8xx SoC */
  29 #define CONFIG_SOC_DA850                /* TI DA850 SoC */
  30 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
  31 #define CONFIG_SYS_CLK_FREQ             clk_get(DAVINCI_ARM_CLKID)
  32 #define CONFIG_SYS_OSCIN_FREQ           24000000
  33 #define CONFIG_SYS_TIMERBASE            DAVINCI_TIMER0_BASE
  34 #define CONFIG_SYS_HZ_CLOCK             clk_get(DAVINCI_AUXCLK_CLKID)
  35 #define CONFIG_DA850_LOWLEVEL
  36 #define CONFIG_ARCH_CPU_INIT
  37 #define CONFIG_SYS_DA850_PLL_INIT
  38 #define CONFIG_SYS_DA850_DDR_INIT
  39 #define CONFIG_DA8XX_GPIO
  40 #define CONFIG_HOSTNAME         enbw_cmc
  41
  42 #define MACH_TYPE_ENBW_CMC      3585
  43 #define CONFIG_MACH_TYPE        MACH_TYPE_ENBW_CMC
  44
  45 /*
  46  * Memory Info
  47  */
  48 #define CONFIG_SYS_MALLOC_LEN   (0x10000 + 1*1024*1024) /* malloc() len */
  49 #define PHYS_SDRAM_1            DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
  50 #define PHYS_SDRAM_1_SIZE       (64 << 20) /* SDRAM size 64MB */
  51 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
  52
  53 /* memtest start addr */
  54 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + 0x2000000)
  55
  56 /* memtest will be run on 16MB */
  57 #define CONFIG_SYS_MEMTEST_END  (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
  58
  59 #define CONFIG_NR_DRAM_BANKS    1 /* we have 1 bank of DRAM */
  60
  61 /*
  62  * Serial Driver info
  63  */
  64 #define CONFIG_SYS_NS16550
  65 #define CONFIG_SYS_NS16550_SERIAL
  66 #define CONFIG_SYS_NS16550_REG_SIZE     -4      /* NS16550 register size */
  67 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
  68 #define CONFIG_SYS_NS16550_CLK  clk_get(DAVINCI_UART2_CLKID)
  69 #define CONFIG_CONS_INDEX       1               /* use UART0 for console */
  70 #define CONFIG_BAUDRATE         115200          /* Default baud rate */
  71
  72 /*
  73  * I2C Configuration
  74  */
  75 #define CONFIG_SYS_I2C
  76 #define CONFIG_SYS_I2C_DAVINCI
  77 #define CONFIG_SYS_DAVINCI_I2C_SPEED            80000
  78 #define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
  79 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
  80 #define CONFIG_CMD_I2C
  81
  82 #define CONFIG_CMD_DTT
  83 #define CONFIG_DTT_LM75
  84 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
  85 #define CONFIG_SYS_DTT_MAX_TEMP 70
  86 #define CONFIG_SYS_DTT_LOW_TEMP -30
  87 #define CONFIG_SYS_DTT_HYSTERESIS       3
  88
  89 /*
  90  * SPI Configuration
  91  */
  92 #define CONFIG_DAVINCI_SPI
  93 #define CONFIG_SYS_SPI_BASE             DAVINCI_SPI1_BASE
  94 #define CONFIG_SYS_SPI_CLK              clk_get(DAVINCI_SPI1_CLKID)
  95 #define CONFIG_CMD_SPI
  96
  97 /*
  98  * Flash & Environment
  99  */
 100 #ifdef CONFIG_USE_NAND
 101 #define CONFIG_NAND_DAVINCI
 102 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 103 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
 104 #define CONFIG_SYS_NAND_PAGE_2K
 105 #define CONFIG_SYS_NAND_CS              3
 106 #define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 107 #define CONFIG_SYS_NAND_MASK_CLE                0x10
 108 #define CONFIG_SYS_NAND_MASK_ALE                0x8
 109 #undef CONFIG_SYS_NAND_HW_ECC
 110 #define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
 111
 112 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0,nand0=davinci_nand.1"
 113 #define MTDPARTS_DEFAULT                        \
 114         "mtdparts="                             \
 115                 "physmap-flash.0:"              \
 116                         "512k(U-Boot),"         \
 117                         "64k(env1),"            \
 118                         "64k(env2),"            \
 119                         "-(rest);"              \
 120                 "davinci_nand.1:"               \
 121                         "128k(dtb),"            \
 122                         "3m(kernel),"           \
 123                         "4m(rootfs),"           \
 124                         "-(userfs)"
 125
 126
 127 #define CONFIG_CMD_MTDPARTS
 128
 129 #endif
 130
 131 /*
 132  * Network & Ethernet Configuration
 133  */
 134 #ifdef CONFIG_DRIVER_TI_EMAC
 135 #define CONFIG_MII
 136 #define CONFIG_BOOTP_DNS
 137 #define CONFIG_BOOTP_DNS2
 138 #define CONFIG_BOOTP_SEND_HOSTNAME
 139 #define CONFIG_NET_RETRY_COUNT  10
 140 #endif
 141
 142 /*
 143  * Flash configuration
 144  */
 145 #define CONFIG_SYS_FLASH_CFI
 146 #define CONFIG_FLASH_CFI_DRIVER
 147 #define CONFIG_FLASH_CFI_MTD
 148 #define CONFIG_SYS_FLASH_BASE           0x60000000
 149 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 150 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 151 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 152 #define CONFIG_SYS_MAX_FLASH_SECT       128
 153 #define CONFIG_FLASH_16BIT              /* Flash is 16-bit */
 154
 155 #define CONFIG_ENV_IS_IN_FLASH
 156 #define CONFIG_SYS_MONITOR_LEN  0x80000
 157 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + \
 158                                         CONFIG_SYS_MONITOR_LEN)
 159 #define CONFIG_ENV_SECT_SIZE    (64 << 10)
 160 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
 161 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + \
 162                                         CONFIG_ENV_SECT_SIZE)
 163 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 164 #undef CONFIG_ENV_IS_IN_NAND
 165 #define CONFIG_DEFAULT_SETTINGS_ADDR    (CONFIG_ENV_ADDR_REDUND + \
 166                                                 CONFIG_ENV_SECT_SIZE)
 167
 168 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 169         "u-boot_addr_r=c0000000\0"                                      \
 170         "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"          \
 171         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 172         "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
 173                 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"    \
 174                 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)     \
 175                 " ${filesize};"                                         \
 176                 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
 177         "netdev=eth0\0"                                                 \
 178         "rootpath=/opt/eldk-arm/arm\0"                                  \
 179         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 180                 "nfsroot=${serverip}:${rootpath}\0"                     \
 181         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 182         "addip=setenv bootargs ${bootargs} "                            \
 183                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 184                 ":${hostname}:${netdev}:off panic=1\0"                  \
 185         "kernel_addr_r=c0700000\0"                                      \
 186         "fdt_addr_r=c0600000\0"                                         \
 187         "ramdisk_addr_r=c0b00000\0"                                     \
 188         "fdt_file=" __stringify(CONFIG_HOSTNAME) "/"                    \
 189                 __stringify(CONFIG_HOSTNAME) ".dtb\0"                   \
 190         "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0"        \
 191         "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0"    \
 192         "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0"      \
 193         "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0"                  \
 194         "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0"            \
 195         "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0"                     \
 196         "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0"     \
 197         "addcon=setenv bootargs ${bootargs} console=ttyS2,"             \
 198                 "${baudrate}n8\0"                                       \
 199         "net_nfs=run load_fdt load_kernel; "                            \
 200                 "run nfsargs addip addcon addmtd addmisc;"              \
 201                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 202         "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
 203                 "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"    \
 204         "bootcmd=run net_nfs\0"                                         \
 205         "machid=e01\0"                                                  \
 206         "key_cmd_0=echo key:   0\0"                                     \
 207         "key_cmd_1=echo key:   1\0"                                     \
 208         "key_cmd_2=echo key:   2\0"                                     \
 209         "key_cmd_3=echo key:   3\0"                                     \
 210         "key_magic_0=0\0"                                               \
 211         "key_magic_1=1\0"                                               \
 212         "key_magic_2=2\0"                                               \
 213         "key_magic_3=3\0"                                               \
 214         "magic_keys=0123\0"                                             \
 215         "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0"            \
 216         "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"              \
 217         "addmisc=setenv bootargs ${bootargs}\0"                         \
 218         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 219         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 220         "logversion=2\0"                                                \
 221         "\0"
 222
 223 /*
 224  * U-Boot general configuration
 225  */
 226 #define CONFIG_BOOTFILE         "uImage" /* Boot file name */
 227 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 228 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 229 #define CONFIG_SYS_MAXARGS      16 /* max number of command args */
 230 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
 231 #define CONFIG_SYS_LOAD_ADDR    (PHYS_SDRAM_1 + 0x700000)
 232 #define CONFIG_VERSION_VARIABLE
 233 #define CONFIG_AUTO_COMPLETE
 234 #define CONFIG_SYS_HUSH_PARSER
 235 #define CONFIG_CMDLINE_EDITING
 236 #define CONFIG_SYS_LONGHELP
 237 #define CONFIG_CRC32_VERIFY
 238 #define CONFIG_MX_CYCLIC
 239 #define CONFIG_BOOTDELAY        3
 240 #define CONFIG_HWCONFIG
 241 #define CONFIG_SHOW_BOOT_PROGRESS
 242 #define CONFIG_BOARD_LATE_INIT
 243
 244 /*
 245  * U-Boot commands
 246  */
 247 #define CONFIG_CMD_ENV
 248 #define CONFIG_CMD_ASKENV
 249 #define CONFIG_CMD_DHCP
 250 #define CONFIG_CMD_DIAG
 251 #define CONFIG_CMD_MII
 252 #define CONFIG_CMD_PING
 253 #define CONFIG_CMD_SAVES
 254 #define CONFIG_CMD_CACHE
 255
 256 #ifdef CONFIG_CMD_BDI
 257 #define CONFIG_CLOCKS
 258 #endif
 259
 260 #ifndef CONFIG_DRIVER_TI_EMAC
 261 #undef CONFIG_CMD_DHCP
 262 #undef CONFIG_CMD_MII
 263 #undef CONFIG_CMD_PING
 264 #endif
 265
 266 #ifdef CONFIG_USE_NAND
 267 #define CONFIG_CMD_NAND
 268
 269 #define CONFIG_CMD_MTDPARTS
 270 #define CONFIG_MTD_DEVICE
 271 #define CONFIG_MTD_PARTITIONS
 272 #define CONFIG_LZO
 273 #define CONFIG_RBTREE
 274 #define CONFIG_CMD_UBI
 275 #define CONFIG_CMD_UBIFS
 276 #endif
 277
 278 #if !defined(CONFIG_USE_NAND) && \
 279         !defined(CONFIG_USE_NOR) && \
 280         !defined(CONFIG_USE_SPIFLASH)
 281 #define CONFIG_ENV_IS_NOWHERE
 282 #define CONFIG_SYS_NO_FLASH
 283 #define CONFIG_ENV_SIZE         (16 << 10)
 284 #undef CONFIG_CMD_ENV
 285 #endif
 286
 287 #define CONFIG_SYS_TEXT_BASE            0x60000000
 288 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 289 #define CONFIG_SYS_SDRAM_BASE           0xc0000000
 290 #define CONFIG_SYS_INIT_SP_ADDR         (0x8001ff00)
 291
 292 #define CONFIG_VERSION_VARIABLE
 293 #define CONFIG_ENV_OVERWRITE
 294
 295 #define CONFIG_PREBOOT  "echo;" \
 296         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 297         "echo"
 298 #define CONFIG_MISC_INIT_R
 299
 300 #define CONFIG_CMC_RESET_PIN    0x04000000
 301 #define CONFIG_CMC_RESET_TIMEOUT        3
 302
 303 #define CONFIG_HW_WATCHDOG
 304 #define CONFIG_SYS_WDTTIMERBASE         DAVINCI_TIMER1_BASE
 305 #define CONFIG_SYS_WDT_PERIOD_LOW       0x0c000000
 306 #define CONFIG_SYS_WDT_PERIOD_HIGH      0x0
 307
 308 #define CONFIG_CMD_DATE
 309 #define CONFIG_RTC_DAVINCI
 310
 311 /* SD/MMC */
 312 #define CONFIG_MMC
 313 #define CONFIG_GENERIC_MMC
 314 #define CONFIG_DAVINCI_MMC
 315 #define CONFIG_MMC_MBLOCK
 316 #define CONFIG_DOS_PARTITION
 317 #define CONFIG_CMD_FAT
 318 #define CONFIG_CMD_MMC
 319
 320 /* GPIO */
 321 #define CONFIG_ENBW_CMC_BOARD_TYPE      57
 322 #define CONFIG_ENBW_CMC_HW_ID_BIT0      39
 323 #define CONFIG_ENBW_CMC_HW_ID_BIT1      38
 324 #define CONFIG_ENBW_CMC_HW_ID_BIT2      35
 325
 326 /* FDT support */
 327 #define CONFIG_OF_LIBFDT
 328
 329 /* LowLevel Init */
 330 /* PLL */
 331 #define CONFIG_SYS_DV_CLKMODE           0
 332 #define CONFIG_SYS_DA850_PLL0_POSTDIV   0
 333 #define CONFIG_SYS_DA850_PLL0_PLLDIV1   0x8000
 334 #define CONFIG_SYS_DA850_PLL0_PLLDIV2   0x8001
 335 #define CONFIG_SYS_DA850_PLL0_PLLDIV3   0x8002 /* 150MHz */
 336 #define CONFIG_SYS_DA850_PLL0_PLLDIV4   0x8003
 337 #define CONFIG_SYS_DA850_PLL0_PLLDIV5   0x8002
 338 #define CONFIG_SYS_DA850_PLL0_PLLDIV6   CONFIG_SYS_DA850_PLL0_PLLDIV1
 339 #define CONFIG_SYS_DA850_PLL0_PLLDIV7   0x8005
 340
 341 #define CONFIG_SYS_DA850_PLL1_POSTDIV   1
 342 #define CONFIG_SYS_DA850_PLL1_PLLDIV1   0x8000
 343 #define CONFIG_SYS_DA850_PLL1_PLLDIV2   0x8001
 344 #define CONFIG_SYS_DA850_PLL1_PLLDIV3   0x8002
 345
 346 #define CONFIG_SYS_DA850_PLL0_PLLM      18      /* PLL0 -> 456 MHz */
 347 #define CONFIG_SYS_DA850_PLL1_PLLM      24      /* PLL1 -> 300 MHz */
 348
 349 /* DDR RAM */
 350 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
 351                         DV_DDR_PHY_EXT_STRBEN   | \
 352                         (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 353
 354 #define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
 355                   (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
 356                   (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
 357                   (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
 358                   (0x1 << DV_DDR_SDCR_DDREN_SHIFT)      | \
 359                   (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT)    | \
 360                   (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)  | \
 361                   (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)  | \
 362                   (0x3 << DV_DDR_SDCR_CL_SHIFT)         | \
 363                   (0x2 << DV_DDR_SDCR_IBANK_SHIFT)              | \
 364                   (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 365
 366 #define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
 367
 368 /*
 369  * freq = 150MHz -> t = 7ns
 370  */
 371 #define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
 372                 (0x0d << DV_DDR_SDTMR1_RFC_SHIFT)       | \
 373                 (1 << DV_DDR_SDTMR1_RP_SHIFT)           | \
 374                 (1 << DV_DDR_SDTMR1_RCD_SHIFT)          | \
 375                 (1 << DV_DDR_SDTMR1_WR_SHIFT)           | \
 376                 (5 << DV_DDR_SDTMR1_RAS_SHIFT)          | \
 377                 (7 << DV_DDR_SDTMR1_RC_SHIFT)           | \
 378                 (1 << DV_DDR_SDTMR1_RRD_SHIFT)          | \
 379                 (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) |  /* Reserved */ \
 380                 ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
 381
 382 /*
 383  * freq = 150MHz -> t=7ns
 384  */
 385 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
 386         (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
 387         (8 << DV_DDR_SDTMR2_RASMAX_SHIFT)               | \
 388         (2 << DV_DDR_SDTMR2_XP_SHIFT)                   | \
 389         (0 << DV_DDR_SDTMR2_ODT_SHIFT)                  | \
 390         (15 << DV_DDR_SDTMR2_XSNR_SHIFT)                | \
 391         (27 << DV_DDR_SDTMR2_XSRD_SHIFT)                | \
 392         (0 << DV_DDR_SDTMR2_RTP_SHIFT)                  | \
 393         (2 << DV_DDR_SDTMR2_CKE_SHIFT))
 394
 395 #define CONFIG_SYS_DA850_DDR2_SDRCR     0x00000407
 396 #define CONFIG_SYS_DA850_DDR2_PBBPR     0x30
 397 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
 398                                         DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
 399                                         DAVINCI_SYSCFG_SUSPSRC_UART2 | \
 400                                         DAVINCI_SYSCFG_SUSPSRC_EMAC |\
 401                                         DAVINCI_SYSCFG_SUSPSRC_I2C)
 402
 403 #define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
 404                                 DAVINCI_ABCR_WSTROBE(6) | \
 405                                 DAVINCI_ABCR_WHOLD(1)   | \
 406                                 DAVINCI_ABCR_RSETUP(2)  | \
 407                                 DAVINCI_ABCR_RSTROBE(6) | \
 408                                 DAVINCI_ABCR_RHOLD(1)   | \
 409                                 DAVINCI_ABCR_ASIZE_16BIT)
 410
 411 #define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
 412                                 DAVINCI_ABCR_WSTROBE(2) | \
 413                                 DAVINCI_ABCR_WHOLD(1)   | \
 414                                 DAVINCI_ABCR_RSETUP(1)  | \
 415                                 DAVINCI_ABCR_RSTROBE(6) | \
 416                                 DAVINCI_ABCR_RHOLD(1)   | \
 417                                 DAVINCI_ABCR_ASIZE_8BIT)
 418
 419 /*
 420  * NOR Bootconfiguration word:
 421  * Method: Direc boot
 422  * EMIFA access mode: 16 Bit
 423  */
 424 #define CONFIG_SYS_DV_NOR_BOOT_CFG      (0x11)
 425
 426 #define CONFIG_POST     (CONFIG_SYS_POST_MEMORY)
 427 #define CONFIG_POST_EXTERNAL_WORD_FUNCS
 428 #define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
 429 #define CONFIG_LOGBUFFER
 430 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 431
 432 #define CONFIG_BOOTCOUNT_LIMIT
 433 #define CONFIG_SYS_BOOTCOUNT_ADDR       DAVINCI_RTC_BASE
 434 #define CONFIG_SYS_BOOTCOUNT_BE
 435
 436 #define CONFIG_SYS_NAND_U_BOOT_DST      0xc0080000
 437 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x60004000
 438 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x70000
 439 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 440 #endif /* __CONFIG_H */