2 * Copyright (C) 2008 Miromico AG
4 * Configuration settings for the Miromico Hammerhead AVR32 board
6 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_AT32AP7000
13 #define CONFIG_HAMMERHEAD
16 * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
17 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
18 * and the PBA bus to run at 1/4 the PLL frequency.
21 #define CONFIG_SYS_POWER_MANAGER
22 #define CONFIG_SYS_OSC0_HZ 25000000
23 #define CONFIG_SYS_PLL0_DIV 1
24 #define CONFIG_SYS_PLL0_MUL 5
25 #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
26 #define CONFIG_SYS_CLKDIV_CPU 0
27 #define CONFIG_SYS_CLKDIV_HSB 1
28 #define CONFIG_SYS_CLKDIV_PBA 2
29 #define CONFIG_SYS_CLKDIV_PBB 1
31 /* Reserve VM regions for SDRAM and NOR flash */
32 #define CONFIG_SYS_NR_VM_REGIONS 2
35 * The PLLOPT register controls the PLL like this:
39 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
41 #define CONFIG_SYS_PLL0_OPT 0x04
43 #define CONFIG_USART_BASE ATMEL_BASE_USART1
44 #define CONFIG_USART_ID 1
46 #define CONFIG_HOSTNAME hammerhead
48 /* User serviceable stuff */
49 #define CONFIG_DOS_PARTITION
51 #define CONFIG_CMDLINE_TAG
52 #define CONFIG_SETUP_MEMORY_TAGS
53 #define CONFIG_INITRD_TAG
55 #define CONFIG_STACKSIZE (2048)
57 #define CONFIG_BAUDRATE 115200
58 #define CONFIG_BOOTARGS \
59 "console=ttyS0 root=mtd1 rootfstype=jffs2"
60 #define CONFIG_BOOTCOMMAND \
63 #define CONFIG_BOOTDELAY 1
66 * After booting the board for the first time, new ethernet address
67 * should be generated and assigned to the environment variables
68 * "ethaddr". This is normally done during production.
70 #define CONFIG_OVERWRITE_ETHADDR_ONCE
75 #define CONFIG_BOOTP_SUBNETMASK
76 #define CONFIG_BOOTP_GATEWAY
79 * Command line configuration.
81 #include <config_cmd_default.h>
83 #define CONFIG_CMD_ASKENV
84 #define CONFIG_CMD_DHCP
85 #define CONFIG_CMD_EXT2
86 #define CONFIG_CMD_FAT
87 #define CONFIG_CMD_JFFS2
88 #define CONFIG_CMD_MMC
89 #undef CONFIG_CMD_FPGA
90 #undef CONFIG_CMD_SETGETDCR
92 #define CONFIG_ATMEL_USART
94 #define CONFIG_PORTMUX_PIO
95 #define CONFIG_SYS_NR_PIOS 5
96 #define CONFIG_SYS_HSDRAMC
98 #define CONFIG_GENERIC_ATMEL_MCI
99 #define CONFIG_GENERIC_MMC
101 #define CONFIG_SYS_DCACHE_LINESZ 32
102 #define CONFIG_SYS_ICACHE_LINESZ 32
104 #define CONFIG_NR_DRAM_BANKS 1
106 #define CONFIG_SYS_FLASH_CFI
107 #define CONFIG_FLASH_CFI_DRIVER
109 #define CONFIG_SYS_FLASH_BASE 0x00000000
110 #define CONFIG_SYS_FLASH_SIZE 0x800000
111 #define CONFIG_SYS_MAX_FLASH_BANKS 1
112 #define CONFIG_SYS_MAX_FLASH_SECT 135
114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
115 #define CONFIG_SYS_TEXT_BASE 0x00000000
117 #define CONFIG_SYS_INTRAM_BASE 0x24000000
118 #define CONFIG_SYS_INTRAM_SIZE 0x8000
120 #define CONFIG_SYS_SDRAM_BASE 0x10000000
122 #define CONFIG_ENV_IS_IN_FLASH
123 #define CONFIG_ENV_SIZE 65536
124 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
126 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
128 #define CONFIG_SYS_MALLOC_LEN (256*1024)
131 /* Allow 4MB for the kernel run-time image */
132 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
133 #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
135 /* Other configuration settings that shouldn't have to change all that often */
136 #define CONFIG_SYS_PROMPT "Hammerhead> "
137 #define CONFIG_SYS_CBSIZE 256
138 #define CONFIG_SYS_MAXARGS 16
139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
140 #define CONFIG_SYS_LONGHELP
142 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
143 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
145 #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
147 #endif /* __CONFIG_H */