include/configs/m28evk.h

   1 /*
   2  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   3  * on behalf of DENX Software Engineering GmbH
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20 #ifndef __M28_H__
  21 #define __M28_H__
  22
  23 #include <asm/arch/regs-base.h>
  24
  25 /*
  26  * SoC configurations
  27  */
  28 #define CONFIG_MX28                             /* i.MX28 SoC */
  29 #define CONFIG_MXS_GPIO                         /* GPIO control */
  30 #define CONFIG_SYS_HZ           1000            /* Ticks per second */
  31
  32 /*
  33  * Define M28EVK machine type by hand until it lands in mach-types
  34  */
  35 #define MACH_TYPE_M28EVK        3613
  36
  37 #define CONFIG_MACH_TYPE        MACH_TYPE_M28EVK
  38
  39 #define CONFIG_SYS_NO_FLASH
  40 #define CONFIG_SYS_ICACHE_OFF
  41 #define CONFIG_SYS_DCACHE_OFF
  42 #define CONFIG_BOARD_EARLY_INIT_F
  43 #define CONFIG_ARCH_CPU_INIT
  44 #define CONFIG_ARCH_MISC_INIT
  45
  46 /*
  47  * SPL
  48  */
  49 #define CONFIG_SPL
  50 #define CONFIG_SPL_NO_CPU_SUPPORT_CODE
  51 #define CONFIG_SPL_START_S_PATH         "arch/arm/cpu/arm926ejs/mx28"
  52 #define CONFIG_SPL_LDSCRIPT     "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
  53 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  54 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  55
  56 /*
  57  * U-Boot Commands
  58  */
  59 #include <config_cmd_default.h>
  60 #define CONFIG_DISPLAY_CPUINFO
  61 #define CONFIG_DOS_PARTITION
  62
  63 #define CONFIG_CMD_CACHE
  64 #define CONFIG_CMD_DATE
  65 #define CONFIG_CMD_DHCP
  66 #define CONFIG_CMD_EEPROM
  67 #define CONFIG_CMD_EXT2
  68 #define CONFIG_CMD_FAT
  69 #define CONFIG_CMD_GPIO
  70 #define CONFIG_CMD_I2C
  71 #define CONFIG_CMD_MII
  72 #define CONFIG_CMD_MMC
  73 #define CONFIG_CMD_NAND
  74 #define CONFIG_CMD_NET
  75 #define CONFIG_CMD_NFS
  76 #define CONFIG_CMD_PING
  77 #define CONFIG_CMD_SETEXPR
  78 #define CONFIG_CMD_SF
  79 #define CONFIG_CMD_SPI
  80 #define CONFIG_CMD_USB
  81
  82 /*
  83  * Memory configurations
  84  */
  85 #define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
  86 #define PHYS_SDRAM_1                    0x40000000      /* Base address */
  87 #define PHYS_SDRAM_1_SIZE               0x40000000      /* Max 1 GB RAM */
  88 #define CONFIG_STACKSIZE                0x00010000      /* 128 KB stack */
  89 #define CONFIG_SYS_MALLOC_LEN           0x00400000      /* 4 MB for malloc */
  90 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* Initial data */
  91 #define CONFIG_SYS_MEMTEST_START        0x40000000      /* Memtest start adr */
  92 #define CONFIG_SYS_MEMTEST_END          0x40400000      /* 4 MB RAM test */
  93 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  94 /* Point initial SP in SRAM so SPL can use it too. */
  95
  96 #define CONFIG_SYS_INIT_RAM_ADDR        0x00000000
  97 #define CONFIG_SYS_INIT_RAM_SIZE        (128 * 1024)
  98
  99 #define CONFIG_SYS_INIT_SP_OFFSET \
 100         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 101 #define CONFIG_SYS_INIT_SP_ADDR \
 102         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 103 /*
 104  * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
 105  * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
 106  * binary. In case there was more of this mess, 0x100 bytes are skipped.
 107  */
 108 #define CONFIG_SYS_TEXT_BASE            0x40000100
 109
 110 /*
 111  * U-Boot general configurations
 112  */
 113 #define CONFIG_SYS_LONGHELP
 114 #define CONFIG_SYS_PROMPT       "=> "
 115 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
 116 #define CONFIG_SYS_PBSIZE       \
 117         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 118                                                 /* Print buffer size */
 119 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
 120 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 121                                                 /* Boot argument buffer size */
 122 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
 123 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
 124 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
 125 #define CONFIG_SYS_HUSH_PARSER
 126 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 127
 128 /*
 129  * Serial Driver
 130  */
 131 #define CONFIG_PL011_SERIAL
 132 #define CONFIG_PL011_CLOCK              24000000
 133 #define CONFIG_PL01x_PORTS              { (void *)MXS_UARTDBG_BASE }
 134 #define CONFIG_CONS_INDEX               0
 135 #define CONFIG_BAUDRATE                 115200  /* Default baud rate */
 136 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 137
 138 /*
 139  * MMC Driver
 140  */
 141 #ifdef  CONFIG_CMD_MMC
 142 #define CONFIG_MMC
 143 #define CONFIG_MMC_BOUNCE_BUFFER
 144 #define CONFIG_GENERIC_MMC
 145 #define CONFIG_MXS_MMC
 146 #endif
 147
 148 /*
 149  * APBH DMA
 150  */
 151 #define CONFIG_APBH_DMA
 152
 153 /*
 154  * NAND
 155  */
 156 #define CONFIG_ENV_SIZE                 (16 * 1024)
 157 #ifdef  CONFIG_CMD_NAND
 158 #define CONFIG_NAND_MXS
 159 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 160 #define CONFIG_SYS_NAND_BASE            0x60000000
 161 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 162
 163 /* Environment is in NAND */
 164 #define CONFIG_ENV_IS_IN_NAND
 165 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 166 #define CONFIG_ENV_SECT_SIZE            (128 * 1024)
 167 #define CONFIG_ENV_RANGE                (512 * 1024)
 168 #define CONFIG_ENV_OFFSET               0x300000
 169 #define CONFIG_ENV_OFFSET_REDUND        \
 170                 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
 171
 172 #define CONFIG_CMD_UBI
 173 #define CONFIG_CMD_UBIFS
 174 #define CONFIG_CMD_MTDPARTS
 175 #define CONFIG_RBTREE
 176 #define CONFIG_LZO
 177 #define CONFIG_MTD_DEVICE
 178 #define CONFIG_MTD_PARTITIONS
 179 #define MTDIDS_DEFAULT                  "nand0=gpmi-nand.0"
 180 #define MTDPARTS_DEFAULT                        \
 181         "mtdparts=gpmi-nand.0:"                 \
 182                 "3m(bootloader)ro,"             \
 183                 "512k(environment),"            \
 184                 "512k(redundant-environment),"  \
 185                 "4m(kernel),"                   \
 186                 "-(filesystem)"
 187 #else
 188 #define CONFIG_ENV_IS_NOWHERE
 189 #endif
 190
 191 /*
 192  * Ethernet on SOC (FEC)
 193  */
 194 #ifdef  CONFIG_CMD_NET
 195 #define CONFIG_ETHPRIME                 "FEC0"
 196 #define CONFIG_FEC_MXC
 197 #define CONFIG_FEC_MXC_MULTI
 198 #define CONFIG_MII
 199 #define CONFIG_DISCOVER_PHY
 200 #define CONFIG_FEC_XCV_TYPE             RMII
 201 #endif
 202
 203 /*
 204  * I2C
 205  */
 206 #ifdef  CONFIG_CMD_I2C
 207 #define CONFIG_I2C_MXS
 208 #define CONFIG_HARD_I2C
 209 #define CONFIG_SYS_I2C_SPEED            400000
 210 #endif
 211
 212 /*
 213  * EEPROM
 214  */
 215 #ifdef  CONFIG_CMD_EEPROM
 216 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 217 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 218 #endif
 219
 220 /*
 221  * RTC
 222  */
 223 #ifdef  CONFIG_CMD_DATE
 224 /* Use the internal RTC in the MXS chip */
 225 #define CONFIG_RTC_INTERNAL
 226 #ifdef  CONFIG_RTC_INTERNAL
 227 #define CONFIG_RTC_MXS
 228 #else
 229 #define CONFIG_RTC_M41T62
 230 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 231 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 232 #endif
 233 #endif
 234
 235 /*
 236  * USB
 237  */
 238 #ifdef  CONFIG_CMD_USB
 239 #define CONFIG_USB_EHCI
 240 #define CONFIG_USB_EHCI_MXS
 241 #define CONFIG_EHCI_MXS_PORT            1
 242 #define CONFIG_EHCI_IS_TDI
 243 #define CONFIG_USB_STORAGE
 244 #endif
 245
 246 /*
 247  * SPI
 248  */
 249 #ifdef  CONFIG_CMD_SPI
 250 #define CONFIG_HARD_SPI
 251 #define CONFIG_MXS_SPI
 252 #define CONFIG_SPI_HALF_DUPLEX
 253 #define CONFIG_DEFAULT_SPI_BUS          2
 254 #define CONFIG_DEFAULT_SPI_MODE         SPI_MODE_0
 255
 256 /* SPI FLASH */
 257 #ifdef  CONFIG_CMD_SF
 258 #define CONFIG_SPI_FLASH
 259 #define CONFIG_SPI_FLASH_STMICRO
 260 #define CONFIG_SF_DEFAULT_CS            2
 261 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 262 #define CONFIG_SF_DEFAULT_SPEED         24000000
 263
 264 #define CONFIG_ENV_SPI_CS               0
 265 #define CONFIG_ENV_SPI_BUS              2
 266 #define CONFIG_ENV_SPI_MAX_HZ           24000000
 267 #define CONFIG_ENV_SPI_MODE             SPI_MODE_0
 268 #endif
 269 #endif
 270
 271 /*
 272  * Boot Linux
 273  */
 274 #define CONFIG_CMDLINE_TAG
 275 #define CONFIG_SETUP_MEMORY_TAGS
 276 #define CONFIG_BOOTDELAY        3
 277 #define CONFIG_BOOTFILE         "uImage"
 278 #define CONFIG_BOOTARGS         "console=ttyAM0,115200n8 "
 279 #define CONFIG_BOOTCOMMAND      "run bootcmd_net"
 280 #define CONFIG_LOADADDR         0x42000000
 281 #define CONFIG_SYS_LOAD_ADDR    CONFIG_LOADADDR
 282
 283 /*
 284  * Extra Environments
 285  */
 286 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 287         "update_nand_full_filename=u-boot.nand\0"                       \
 288         "update_nand_firmware_filename=u-boot.sb\0"                     \
 289         "update_nand_firmware_maxsz=0x100000\0"                         \
 290         "update_nand_stride=0x40\0"     /* MX28 datasheet ch. 12.12 */  \
 291         "update_nand_count=0x4\0"       /* MX28 datasheet ch. 12.12 */  \
 292         "update_nand_get_fcb_size="     /* Get size of FCB blocks */    \
 293                 "nand device 0 ; "                                      \
 294                 "nand info ; "                                          \
 295                 "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
 296                 "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
 297         "update_nand_full="             /* Update FCB, DBBT and FW */   \
 298                 "if tftp ${update_nand_full_filename} ; then "          \
 299                 "run update_nand_get_fcb_size ; "                       \
 300                 "nand scrub -y 0x0 ${filesize} ; "                      \
 301                 "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; "  \
 302                 "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
 303                 "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
 304                 "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
 305                 "fi\0"                                                  \
 306         "update_nand_firmware="         /* Update only firmware */      \
 307                 "if tftp ${update_nand_firmware_filename} ; then "      \
 308                 "run update_nand_get_fcb_size ; "                       \
 309                 "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
 310                 "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; "    \
 311                 "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
 312                 "nand erase ${fcb_sz} ${fw_sz} ; "                      \
 313                 "nand write ${loadaddr} ${fcb_sz} ${filesize} ; "       \
 314                 "nand write ${loadaddr} ${fw_off} ${filesize} ; "       \
 315                 "fi\0"
 316
 317 #endif /* __M28_H__ */