include/configs/pxa255_idp.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Copied from lubbock.h
  10  *
  11  * (C) Copyright 2004
  12  * BEC Systems <http://bec-systems.com>
  13  * Cliff Brake <cliff.brake@gmail.com>
  14  * Configuation settings for the Accelent/Vibren PXA255 IDP
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 #include <asm/arch/pxa-regs.h>
  39
  40 /*
  41  * If we are developing, we might want to start U-Boot from RAM
  42  * so we MUST NOT initialize critical regs like mem-timing ...
  43  */
  44 #undef CONFIG_SKIP_LOWLEVEL_INIT                        /* define for developing */
  45 #define CONFIG_SYS_TEXT_BASE    0x0
  46
  47 /*
  48  * define the following to enable debug blinks.  A debug blink function
  49  * must be defined in memsetup.S
  50  */
  51 #undef DEBUG_BLINK_ENABLE
  52 #undef DEBUG_BLINKC_ENABLE
  53
  54 /*
  55  * High Level Configuration Options
  56  * (easy to change)
  57  */
  58 #define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
  59
  60 #undef CONFIG_LCD
  61 #ifdef CONFIG_LCD
  62 #define CONFIG_SHARP_LM8V31
  63 #endif
  64
  65 #define CONFIG_MMC              1
  66 #define CONFIG_DOS_PARTITION    1
  67 #define CONFIG_BOARD_LATE_INIT
  68
  69 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  70
  71 /* we will never enable dcache, because we have to setup MMU first */
  72 #define CONFIG_SYS_DCACHE_OFF
  73
  74 /*
  75  * Size of malloc() pool
  76  */
  77 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
  78
  79 /*
  80  * PXA250 IDP memory map information
  81  */
  82
  83 #define IDP_CS5_ETH_OFFSET      0x03400000
  84
  85
  86 /*
  87  * Hardware drivers
  88  */
  89 #define CONFIG_SMC91111
  90 #define CONFIG_SMC91111_BASE    (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
  91 #define CONFIG_SMC_USE_32_BIT   1
  92 /* #define CONFIG_SMC_USE_IOFUNCS */
  93
  94 /* the following has to be set high -- suspect something is wrong with
  95  * with the tftp timeout routines. FIXME!!!
  96  */
  97 #define CONFIG_NET_RETRY_COUNT  100
  98
  99 /*
 100  * select serial console configuration
 101  */
 102 #define CONFIG_PXA_SERIAL
 103 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
 104
 105 /* allow to overwrite serial and ethaddr */
 106 #define CONFIG_ENV_OVERWRITE
 107
 108 #define CONFIG_BAUDRATE         115200
 109
 110
 111 /*
 112  * BOOTP options
 113  */
 114 #define CONFIG_BOOTP_BOOTFILESIZE
 115 #define CONFIG_BOOTP_BOOTPATH
 116 #define CONFIG_BOOTP_GATEWAY
 117 #define CONFIG_BOOTP_HOSTNAME
 118
 119
 120 /*
 121  * Command line configuration.
 122  */
 123 #include <config_cmd_default.h>
 124
 125 #define CONFIG_CMD_FAT
 126 #define CONFIG_CMD_DHCP
 127
 128 #define CONFIG_BOOTDELAY        3
 129 #define CONFIG_BOOTCOMMAND      "bootm 40000"
 130 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
 131
 132 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 133 #define CONFIG_SETUP_MEMORY_TAGS        1
 134 /* #define CONFIG_INITRD_TAG            1 */
 135
 136 /*
 137  * Current memory map for Vibren supplied Linux images:
 138  *
 139  * Flash:
 140  * 0 - 0x3ffff (size = 0x40000): bootloader
 141  * 0x40000 - 0x13ffff (size = 0x100000): kernel
 142  * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
 143  *
 144  * RAM:
 145  * 0xa0008000 - kernel is loaded
 146  * 0xa3000000 - Uboot runs (48MB into RAM)
 147  *
 148  */
 149
 150 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 151         "prog_boot_mmc="                                                \
 152                         "mw.b 0xa0000000 0xff 0x40000; "                \
 153                         "if      mmcinit && "                           \
 154                                 "fatload mmc 0 0xa0000000 u-boot.bin; " \
 155                         "then "                                         \
 156                                 "protect off 0x0 0x3ffff; "             \
 157                                 "erase 0x0 0x3ffff; "                   \
 158                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 159                                 "reset;"                                \
 160                         "fi\0"                                          \
 161         "prog_uzImage_mmc="                                             \
 162                         "mw.b 0xa0000000 0xff 0x100000; "               \
 163                         "if      mmcinit && "                           \
 164                                 "fatload mmc 0 0xa0000000 uzImage; "    \
 165                         "then "                                         \
 166                                 "protect off 0x40000 0xfffff; "         \
 167                                 "erase 0x40000 0xfffff; "               \
 168                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 169                         "fi\0"                                          \
 170         "prog_jffs_mmc="                                                \
 171                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 172                         "if      mmcinit && "                           \
 173                                 "fatload mmc 0 0xa0000000 root.jffs; "  \
 174                         "then "                                         \
 175                                 "protect off 0x140000 0x1f3ffff; "      \
 176                                 "erase 0x140000 0x1f3ffff; "            \
 177                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 178                         "fi\0"                                          \
 179         "boot_mmc="                                                     \
 180                         "if      mmcinit && "                           \
 181                                 "fatload mmc 0 0xa1000000 uzImage && "  \
 182                         "then "                                         \
 183                                 "bootm 0xa1000000; "                    \
 184                         "fi\0"                                          \
 185         "prog_boot_net="                                                \
 186                         "mw.b 0xa0000000 0xff 0x100000; "               \
 187                         "if      bootp 0xa0000000 u-boot.bin; "         \
 188                         "then "                                         \
 189                                 "protect off 0x0 0x3ffff; "             \
 190                                 "erase 0x0 0x3ffff; "                   \
 191                                 "cp.b 0xa0000000 0x0 0x40000; "         \
 192                                 "reset; "                               \
 193                         "fi\0"                                          \
 194         "prog_uzImage_net="                                             \
 195                         "mw.b 0xa0000000 0xff 0x100000; "               \
 196                         "if      bootp 0xa0000000 uzImage; "            \
 197                         "then "                                         \
 198                                 "protect off 0x40000 0xfffff; "         \
 199                                 "erase 0x40000 0xfffff; "               \
 200                                 "cp.b 0xa0000000 0x40000 0x100000; "    \
 201                         "fi\0"                                          \
 202         "prog_jffs_net="                                                \
 203                         "mw.b 0xa0000000 0xff 0x1e00000; "              \
 204                         "if      bootp 0xa0000000 root.jffs; "          \
 205                         "then "                                         \
 206                                 "protect off 0x140000 0x1f3ffff; "      \
 207                                 "erase 0x140000 0x1f3ffff; "            \
 208                                 "cp.b 0xa0000000 0x140000 0x1e00000; "  \
 209                         "fi\0"
 210
 211
 212 /*      "erase_env="                    */
 213 /*                      "protect off"   */
 214
 215
 216 #if defined(CONFIG_CMD_KGDB)
 217 #define CONFIG_KGDB_BAUDRATE    115200          /* speed to run kgdb serial port */
 218 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 219 #endif
 220
 221 /*
 222  * Miscellaneous configurable options
 223  */
 224 #define CONFIG_SYS_HUSH_PARSER          1
 225 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 226
 227 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 228 #ifdef CONFIG_SYS_HUSH_PARSER
 229 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
 230 #else
 231 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 232 #endif
 233 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 234 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 235 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 236 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 237 #define CONFIG_SYS_DEVICE_NULLDEV       1
 238
 239 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 240 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 241
 242 #define CONFIG_SYS_LOAD_ADDR            0xa0800000      /* default load address */
 243
 244 #define CONFIG_SYS_HZ                   1000
 245 #define CONFIG_SYS_CPUSPEED             0x161           /* set core clock to 400/200/100 MHz */
 246
 247 #define RTC     1                               /* enable 32KHz osc */
 248
 249                                                 /* valid baudrates */
 250 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 251
 252 #ifdef CONFIG_MMC
 253 #define CONFIG_PXA_MMC
 254 #define CONFIG_CMD_MMC
 255 #define CONFIG_SYS_MMC_BASE             0xF0000000
 256 #endif
 257
 258 /*
 259  * Stack sizes
 260  *
 261  * The stack sizes are set up in start.S using the settings below
 262  */
 263 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 264 #ifdef CONFIG_USE_IRQ
 265 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 266 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 267 #endif
 268
 269 /*
 270  * Physical Memory Map
 271  */
 272 #define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 273 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 274 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 275 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 276 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 277 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 278 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 279 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 280 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 281
 282 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 283 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 284 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 285 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 286 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 287
 288 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 289 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 290
 291 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 292
 293 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 294 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 295
 296 /*
 297  * GPIO settings
 298  */
 299
 300 #define CONFIG_SYS_GAFR0_L_VAL  0x80001005
 301 #define CONFIG_SYS_GAFR0_U_VAL  0xa5128012
 302 #define CONFIG_SYS_GAFR1_L_VAL  0x699a9558
 303 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5aa6a
 304 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 305 #define CONFIG_SYS_GAFR2_U_VAL  0x2
 306 #define CONFIG_SYS_GPCR0_VAL    0x1800400
 307 #define CONFIG_SYS_GPCR1_VAL    0x0
 308 #define CONFIG_SYS_GPCR2_VAL    0x0
 309 #define CONFIG_SYS_GPDR0_VAL    0xc1818440
 310 #define CONFIG_SYS_GPDR1_VAL    0xfcffab82
 311 #define CONFIG_SYS_GPDR2_VAL    0x1ffff
 312 #define CONFIG_SYS_GPSR0_VAL    0x8000
 313 #define CONFIG_SYS_GPSR1_VAL    0x3f0002
 314 #define CONFIG_SYS_GPSR2_VAL    0x1c000
 315
 316 #define CONFIG_SYS_PSSR_VAL             0x20
 317
 318 #define CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
 319 #define CONFIG_SYS_CKEN                 0x0
 320
 321 /*
 322  * Memory settings
 323  */
 324 #define CONFIG_SYS_MSC0_VAL             0x29DCA4D2
 325 #define CONFIG_SYS_MSC1_VAL             0x43AC494C
 326 #define CONFIG_SYS_MSC2_VAL             0x39D449D4
 327 #define CONFIG_SYS_MDCNFG_VAL           0x090009C9
 328 #define CONFIG_SYS_MDREFR_VAL           0x0085C017
 329 #define CONFIG_SYS_MDMRS_VAL            0x00220022
 330 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 331 #define CONFIG_SYS_SXCNFG_VAL           0x00000000
 332
 333 /*
 334  * PCMCIA and CF Interfaces
 335  */
 336 #define CONFIG_SYS_MECR_VAL             0x00000003
 337 #define CONFIG_SYS_MCMEM0_VAL           0x00014405
 338 #define CONFIG_SYS_MCMEM1_VAL           0x00014405
 339 #define CONFIG_SYS_MCATT0_VAL           0x00014405
 340 #define CONFIG_SYS_MCATT1_VAL           0x00014405
 341 #define CONFIG_SYS_MCIO0_VAL            0x00014405
 342 #define CONFIG_SYS_MCIO1_VAL            0x00014405
 343
 344 /*
 345  * FLASH and environment organization
 346  */
 347 #define CONFIG_SYS_FLASH_CFI
 348 #define CONFIG_FLASH_CFI_DRIVER 1
 349
 350 #define CONFIG_SYS_MONITOR_BASE 0
 351 #define CONFIG_SYS_MONITOR_LEN          PHYS_FLASH_SECT_SIZE
 352
 353 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 354 #define CONFIG_SYS_MAX_FLASH_SECT       128  /* max number of sectors on one chip    */
 355
 356 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 357
 358 /* timeout values are in ticks */
 359 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 360 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 361
 362 /* put cfg at end of flash for now */
 363 #define CONFIG_ENV_IS_IN_FLASH  1
 364  /* Addr of Environment Sector  */
 365 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
 366 #define CONFIG_ENV_SIZE         PHYS_FLASH_SECT_SIZE    /* Total Size of Environment Sector     */
 367 #define CONFIG_ENV_SECT_SIZE    (PHYS_FLASH_SECT_SIZE / 16)
 368
 369 #endif  /* __CONFIG_H */