include/configs/trats.h

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics
   3  * Heungjun Kim <riverful.kim@samsung.com>
   4  *
   5  * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_TRATS_H
  11 #define __CONFIG_TRATS_H
  12
  13 #include <configs/exynos4-common.h>
  14
  15 #define CONFIG_TRATS
  16
  17
  18 #define CONFIG_TIZEN                    /* TIZEN lib */
  19
  20 #define CONFIG_SYS_L2CACHE_OFF
  21 #ifndef CONFIG_SYS_L2CACHE_OFF
  22 #define CONFIG_SYS_L2_PL310
  23 #define CONFIG_SYS_PL310_BASE   0x10502000
  24 #endif
  25
  26 /* TRATS has 4 banks of DRAM */
  27 #define CONFIG_NR_DRAM_BANKS            4
  28 #define CONFIG_SYS_SDRAM_BASE           0x40000000
  29 #define PHYS_SDRAM_1                    CONFIG_SYS_SDRAM_BASE
  30 #define CONFIG_SYS_TEXT_BASE            0x63300000
  31 #define SDRAM_BANK_SIZE                 (256 << 20)     /* 256 MB */
  32
  33 /* memtest works on */
  34 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  35 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x5000000)
  36 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x4800000)
  37
  38 #define CONFIG_SYS_TEXT_BASE            0x63300000
  39
  40 /* select serial console configuration */
  41 #define CONFIG_SERIAL2
  42 #define CONFIG_BAUDRATE                 115200
  43
  44 /* Console configuration */
  45 #define CONFIG_SYS_CONSOLE_INFO_QUIET
  46 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  47
  48 /* MACH_TYPE_TRATS macro will be removed once added to mach-types */
  49 #define MACH_TYPE_TRATS                 3928
  50 #define CONFIG_MACH_TYPE                MACH_TYPE_TRATS
  51
  52 #define CONFIG_FIT
  53 #define CONFIG_FIT_VERBOSE
  54 #define CONFIG_BOOTARGS                 "Please use defined boot"
  55 #define CONFIG_BOOTCOMMAND              "run autoboot"
  56 #define CONFIG_DEFAULT_CONSOLE          "console=ttySAC2,115200n8\0"
  57
  58 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
  59                                         - GENERATED_GBL_DATA_SIZE)
  60
  61 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20)       /* ram console */
  62
  63 #define CONFIG_SYS_MONITOR_BASE 0x00000000
  64
  65 #define CONFIG_BOOTBLOCK                "10"
  66 #define CONFIG_ENV_COMMON_BOOT          "${console} ${meminfo}"
  67
  68 #define CONFIG_ENV_IS_IN_MMC
  69 #define CONFIG_SYS_MMC_ENV_DEV          CONFIG_MMC_DEFAULT_DEV
  70 #define CONFIG_ENV_SIZE                 4096
  71 #define CONFIG_ENV_OFFSET               ((32 - 4) << 10) /* 32KiB - 4KiB */
  72
  73 #define CONFIG_ENV_OVERWRITE
  74
  75 #define CONFIG_ENV_VARS_UBOOT_CONFIG
  76 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  77
  78 /* Tizen - partitions definitions */
  79 #define PARTS_CSA               "csa-mmc"
  80 #define PARTS_BOOT              "boot"
  81 #define PARTS_QBOOT             "qboot"
  82 #define PARTS_CSC               "csc"
  83 #define PARTS_ROOT              "platform"
  84 #define PARTS_DATA              "data"
  85 #define PARTS_UMS               "ums"
  86
  87 #define PARTS_DEFAULT \
  88         "uuid_disk=${uuid_gpt_disk};" \
  89         "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
  90         "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
  91         "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
  92         "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
  93         "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
  94         "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
  95         "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
  96
  97 #define CONFIG_DFU_ALT \
  98         "u-boot raw 0x80 0x400;" \
  99         "/uImage ext4 0 2;" \
 100         "/modem.bin ext4 0 2;" \
 101         "/exynos4210-trats.dtb ext4 0 2;" \
 102         ""PARTS_CSA" part 0 1;" \
 103         ""PARTS_BOOT" part 0 2;" \
 104         ""PARTS_QBOOT" part 0 3;" \
 105         ""PARTS_CSC" part 0 4;" \
 106         ""PARTS_ROOT" part 0 5;" \
 107         ""PARTS_DATA" part 0 6;" \
 108         ""PARTS_UMS" part 0 7;" \
 109         "params.bin raw 0x38 0x8;" \
 110         "/Image.itb ext4 0 2\0"
 111
 112 #define CONFIG_EXTRA_ENV_SETTINGS \
 113         "bootk=" \
 114                 "run loaduimage;" \
 115                 "if run loaddtb; then " \
 116                         "bootm 0x40007FC0 - ${fdtaddr};" \
 117                 "fi;" \
 118                 "bootm 0x40007FC0;\0" \
 119         "updatebackup=" \
 120                 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
 121                 "mmc dev 0 0\0" \
 122         "updatebootb=" \
 123                 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
 124         "lpj=lpj=3981312\0" \
 125         "nfsboot=" \
 126                 "setenv bootargs root=/dev/nfs rw " \
 127                 "nfsroot=${nfsroot},nolock,tcp " \
 128                 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
 129                 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
 130                 "; run bootk\0" \
 131         "ramfsboot=" \
 132                 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
 133                 "${console} ${meminfo} " \
 134                 "initrd=0x43000000,8M ramdisk=8192\0" \
 135         "mmcboot=" \
 136                 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 137                 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
 138                 "run bootk\0" \
 139         "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
 140         "boottrace=setenv opts initcall_debug; run bootcmd\0" \
 141         "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
 142         "verify=n\0" \
 143         "rootfstype=ext4\0" \
 144         "console=" CONFIG_DEFAULT_CONSOLE \
 145         "meminfo=crashkernel=32M@0x50000000\0" \
 146         "nfsroot=/nfsroot/arm\0" \
 147         "bootblock=" CONFIG_BOOTBLOCK "\0" \
 148         "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
 149         "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
 150                 "${fdtfile}\0" \
 151         "mmcdev=0\0" \
 152         "mmcbootpart=2\0" \
 153         "mmcrootpart=5\0" \
 154         "opts=always_resume=1\0" \
 155         "partitions=" PARTS_DEFAULT \
 156         "dfu_alt_info=" CONFIG_DFU_ALT \
 157         "spladdr=0x40000100\0" \
 158         "splsize=0x200\0" \
 159         "splfile=falcon.bin\0" \
 160         "spl_export=" \
 161                    "setexpr spl_imgsize ${splsize} + 8 ;" \
 162                    "setenv spl_imgsize 0x${spl_imgsize};" \
 163                    "setexpr spl_imgaddr ${spladdr} - 8 ;" \
 164                    "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
 165                    "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
 166                    "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
 167                    "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
 168                    "spl export atags 0x40007FC0;" \
 169                    "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
 170                    "mw.l ${spl_addr_tmp} ${splsize};" \
 171                    "ext4write mmc ${mmcdev}:${mmcbootpart}" \
 172                    " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
 173                    "setenv spl_imgsize;" \
 174                    "setenv spl_imgaddr;" \
 175                    "setenv spl_addr_tmp;\0" \
 176         CONFIG_EXTRA_ENV_ITB \
 177         "fdtaddr=40800000\0" \
 178
 179 /* Falcon mode definitions */
 180 #define CONFIG_CMD_SPL
 181 #define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
 182
 183 /* GPT */
 184 #define CONFIG_RANDOM_UUID
 185
 186 /* I2C */
 187 #include <asm/arch/gpio.h>
 188
 189 #define CONFIG_CMD_I2C
 190
 191 #define CONFIG_SYS_I2C
 192 #define CONFIG_SYS_I2C_S3C24X0
 193 #define CONFIG_SYS_I2C_S3C24X0_SPEED    100000
 194 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0xFE
 195 #define CONFIG_MAX_I2C_NUM              8
 196 #define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 197 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 198 #define CONFIG_SYS_I2C_SOFT_SLAVE       0x7F
 199 #define CONFIG_SOFT_I2C_READ_REPEATED_START
 200 #define CONFIG_SYS_I2C_INIT_BOARD
 201
 202 /* I2C FG */
 203 #define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
 204 #define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40
 205
 206 /* POWER */
 207 #define CONFIG_POWER
 208 #define CONFIG_POWER_I2C
 209 #define CONFIG_POWER_MAX8997
 210
 211 #define CONFIG_POWER_FG
 212 #define CONFIG_POWER_FG_MAX17042
 213 #define CONFIG_POWER_MUIC
 214 #define CONFIG_POWER_MUIC_MAX8997
 215 #define CONFIG_POWER_BATTERY
 216 #define CONFIG_POWER_BATTERY_TRATS
 217
 218 /* Security subsystem - enable hw_rand() */
 219 #define CONFIG_EXYNOS_ACE_SHA
 220 #define CONFIG_LIB_HW_RAND
 221
 222 /* Common misc for Samsung */
 223 #define CONFIG_MISC_COMMON
 224
 225 #define CONFIG_MISC_INIT_R
 226
 227 /* Download menu - Samsung common */
 228 #define CONFIG_LCD_MENU
 229 #define CONFIG_LCD_MENU_BOARD
 230
 231 /* Download menu - definitions for check keys */
 232 #ifndef __ASSEMBLY__
 233 #include <power/max8997_pmic.h>
 234
 235 #define KEY_PWR_PMIC_NAME               "MAX8997_PMIC"
 236 #define KEY_PWR_STATUS_REG              MAX8997_REG_STATUS1
 237 #define KEY_PWR_STATUS_MASK             (1 << 0)
 238 #define KEY_PWR_INTERRUPT_REG           MAX8997_REG_INT1
 239 #define KEY_PWR_INTERRUPT_MASK          (1 << 0)
 240
 241 #define KEY_VOL_UP_GPIO                 EXYNOS4_GPIO_X20
 242 #define KEY_VOL_DOWN_GPIO               EXYNOS4_GPIO_X21
 243 #endif /* __ASSEMBLY__ */
 244
 245 /* LCD console */
 246 #define LCD_BPP                 LCD_COLOR16
 247 #define CONFIG_SYS_WHITE_ON_BLACK
 248
 249 /* LCD */
 250 #define CONFIG_EXYNOS_FB
 251 #define CONFIG_LCD
 252 #define CONFIG_CMD_BMP
 253 #define CONFIG_BMP_16BPP
 254 #define CONFIG_FB_ADDR          0x52504000
 255 #define CONFIG_S6E8AX0
 256 #define CONFIG_EXYNOS_MIPI_DSIM
 257 #define CONFIG_VIDEO_BMP_GZIP
 258 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
 259
 260 #endif  /* __CONFIG_H */