include/configs/tricorder.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * (C) Copyright 2012
   8  * Corscience GmbH & Co. KG
   9  * Thomas Weber <weber@corscience.de>
  10  *
  11  * Configuration settings for the Tricorder board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /* High Level Configuration Options */
  20 #define CONFIG_OMAP                     /* in a TI OMAP core */
  21 #define CONFIG_OMAP34XX                 /* which is a 34XX */
  22 #define CONFIG_OMAP_COMMON
  23
  24 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
  25 /*
  26  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  27  * 64 bytes before this address should be set aside for u-boot.img's
  28  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  29  * other needs.
  30  */
  31 #define CONFIG_SYS_TEXT_BASE            0x80100000
  32
  33 #define CONFIG_SDRC                     /* The chip has SDRC controller */
  34
  35 #include <asm/arch/cpu.h>               /* get chip and board defs */
  36 #include <asm/arch/omap3.h>
  37
  38 /* Display CPU and Board information */
  39 #define CONFIG_DISPLAY_CPUINFO
  40 #define CONFIG_DISPLAY_BOARDINFO
  41
  42 /* Clock Defines */
  43 #define V_OSCK                          26000000 /* Clock output from T2 */
  44 #define V_SCLK                          (V_OSCK >> 1)
  45
  46 #define CONFIG_MISC_INIT_R
  47
  48 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  49 #define CONFIG_SETUP_MEMORY_TAGS
  50 #define CONFIG_INITRD_TAG
  51 #define CONFIG_REVISION_TAG
  52
  53 #define CONFIG_OF_LIBFDT
  54
  55 /* Size of malloc() pool */
  56 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  57                                                 /* Sector */
  58 #define CONFIG_SYS_MALLOC_LEN           (1024*1024)
  59
  60 /* Hardware drivers */
  61
  62 /* NS16550 Configuration */
  63 #define CONFIG_SYS_NS16550
  64 #define CONFIG_SYS_NS16550_SERIAL
  65 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  66 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  67
  68 /* select serial console configuration */
  69 #define CONFIG_CONS_INDEX               3
  70 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  71 #define CONFIG_SERIAL3                  3
  72 #define CONFIG_BAUDRATE                 115200
  73 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  74                                         115200}
  75
  76 /* MMC */
  77 #define CONFIG_GENERIC_MMC
  78 #define CONFIG_MMC
  79 #define CONFIG_OMAP_HSMMC
  80 #define CONFIG_DOS_PARTITION
  81
  82 /* I2C */
  83 #define CONFIG_HARD_I2C
  84 #define CONFIG_SYS_I2C_SPEED            100000
  85 #define CONFIG_SYS_I2C_SLAVE            1
  86 #define CONFIG_DRIVER_OMAP34XX_I2C      1
  87
  88 /* TWL4030 */
  89 #define CONFIG_TWL4030_POWER
  90 #define CONFIG_TWL4030_LED
  91
  92 /* Board NAND Info */
  93 #define CONFIG_SYS_NO_FLASH             /* no NOR flash */
  94 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
  95 #define MTDIDS_DEFAULT                  "nand0=nand"
  96 #define MTDPARTS_DEFAULT                "mtdparts=nand:" \
  97                                                 "512k(u-boot-spl)," \
  98                                                 "1920k(u-boot)," \
  99                                                 "128k(u-boot-env)," \
 100                                                 "4m(kernel)," \
 101                                                 "-(fs)"
 102
 103 #define CONFIG_NAND_OMAP_GPMC
 104 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 105                                                         /* to access nand */
 106 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 107                                                         /* to access nand at */
 108                                                         /* CS0 */
 109 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 110
 111 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 112                                                         /* devices */
 113 #define CONFIG_NAND_OMAP_BCH8
 114 #define CONFIG_BCH
 115
 116 /* commands to include */
 117 #include <config_cmd_default.h>
 118
 119 #define CONFIG_CMD_EXT2                 /* EXT2 Support */
 120 #define CONFIG_CMD_FAT                  /* FAT support */
 121 #define CONFIG_CMD_I2C                  /* I2C serial bus support */
 122 #define CONFIG_CMD_MMC                  /* MMC support */
 123 #define CONFIG_CMD_MTDPARTS             /* Enable MTD parts commands */
 124 #define CONFIG_CMD_NAND                 /* NAND support */
 125 #define CONFIG_CMD_NAND_LOCK_UNLOCK     /* nand (un)lock commands */
 126 #define CONFIG_CMD_UBI                  /* UBI commands */
 127 #define CONFIG_CMD_UBIFS                /* UBIFS commands */
 128 #define CONFIG_LZO                      /* LZO is needed for UBIFS */
 129
 130 #undef CONFIG_CMD_NET
 131 #undef CONFIG_CMD_NFS
 132 #undef CONFIG_CMD_FPGA                  /* FPGA configuration Support */
 133 #undef CONFIG_CMD_IMI                   /* iminfo */
 134 #undef CONFIG_CMD_JFFS2                 /* JFFS2 Support */
 135
 136 /* needed for ubi */
 137 #define CONFIG_RBTREE
 138 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 139 #define CONFIG_MTD_PARTITIONS
 140
 141 /* Environment information */
 142 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 143
 144 #define CONFIG_BOOTDELAY                3
 145
 146 #define CONFIG_EXTRA_ENV_SETTINGS \
 147         "loadaddr=0x82000000\0" \
 148         "console=ttyO2,115200n8\0" \
 149         "mmcdev=0\0" \
 150         "vram=12M\0" \
 151         "lcdmode=800x600\0" \
 152         "defaultdisplay=lcd\0" \
 153         "kernelopts=rw rootwait\0" \
 154         "commonargs=" \
 155                 "setenv bootargs console=${console} " \
 156                 "vram=${vram} " \
 157                 "omapfb.mode=lcd:${lcdmode} " \
 158                 "omapdss.def_disp=${defaultdisplay}\0" \
 159         "mmcargs=" \
 160                 "run commonargs; " \
 161                 "setenv bootargs ${bootargs} " \
 162                 "root=/dev/mmcblk0p2 " \
 163                 "${kernelopts}\0" \
 164         "nandargs=" \
 165                 "run commonargs; " \
 166                 "setenv bootargs ${bootargs} " \
 167                 "omapfb.mode=lcd:${lcdmode} " \
 168                 "omapdss.def_disp=${defaultdisplay} " \
 169                 "root=ubi0:root " \
 170                 "ubi.mtd=4 " \
 171                 "rootfstype=ubifs " \
 172                 "${kernelopts}\0" \
 173         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 174         "bootscript=echo Running bootscript from mmc ...; " \
 175                 "source ${loadaddr}\0" \
 176         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 177         "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
 178         "mmcboot=echo Booting from mmc ...; " \
 179                 "run mmcargs; " \
 180                 "bootm ${loadaddr}\0" \
 181         "loaduimage_ubi=mtd default; " \
 182                 "ubi part fs; " \
 183                 "ubifsmount ubi:root; " \
 184                 "ubifsload ${loadaddr} /boot/uImage\0" \
 185         "nandboot=echo Booting from nand ...; " \
 186                 "run nandargs; " \
 187                 "run loaduimage_ubi; " \
 188                 "bootm ${loadaddr}\0" \
 189         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 190                         "if run loadbootscript; then " \
 191                                 "run bootscript; " \
 192                         "else " \
 193                                 "if run loaduimage; then " \
 194                                         "run mmcboot; " \
 195                                 "else run nandboot; " \
 196                                 "fi; " \
 197                         "fi; " \
 198                 "else run nandboot; fi\0"
 199
 200
 201 #define CONFIG_BOOTCOMMAND "run autoboot"
 202
 203 /* Miscellaneous configurable options */
 204 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 205 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 206 #define CONFIG_AUTO_COMPLETE
 207 #define CONFIG_SYS_PROMPT               "OMAP3 Tricorder # "
 208 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 209 /* Print Buffer Size */
 210 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 211                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 212 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 213
 214 /* Boot Argument Buffer Size */
 215 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 216
 217 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x07000000)
 218 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 219                                         0x01000000) /* 16MB */
 220
 221 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 222
 223 /*
 224  * OMAP3 has 12 GP timers, they can be driven by the system clock
 225  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 226  * This rate is divided by a local divisor.
 227  */
 228 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 229 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 230 #define CONFIG_SYS_HZ                   1000
 231
 232 /*  Physical Memory Map  */
 233 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
 234 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 235 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 236
 237 /* NAND and environment organization  */
 238 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 239
 240 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 241
 242 #define CONFIG_ENV_IS_IN_NAND           1
 243 #define CONFIG_ENV_OFFSET               0x260000 /* environment starts here */
 244
 245 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 246 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 247 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 248 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 249                                                 CONFIG_SYS_INIT_RAM_SIZE - \
 250                                                 GENERATED_GBL_DATA_SIZE)
 251
 252 /* SRAM config */
 253 #define CONFIG_SYS_SRAM_START           0x40200000
 254 #define CONFIG_SYS_SRAM_SIZE            0x10000
 255
 256 /* Defines for SPL */
 257 #define CONFIG_SPL
 258 #define CONFIG_SPL_FRAMEWORK
 259 #define CONFIG_SPL_NAND_SIMPLE
 260
 261 #define CONFIG_SPL_BOARD_INIT
 262 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 263 #define CONFIG_SPL_LIBDISK_SUPPORT
 264 #define CONFIG_SPL_I2C_SUPPORT
 265 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 266 #define CONFIG_SPL_SERIAL_SUPPORT
 267 #define CONFIG_SPL_POWER_SUPPORT
 268 #define CONFIG_SPL_NAND_SUPPORT
 269 #define CONFIG_SPL_NAND_BASE
 270 #define CONFIG_SPL_NAND_DRIVERS
 271 #define CONFIG_SPL_NAND_ECC
 272 #define CONFIG_SPL_MMC_SUPPORT
 273 #define CONFIG_SPL_FAT_SUPPORT
 274 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 275 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
 276 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 277 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 278
 279 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 280 #define CONFIG_SPL_MAX_SIZE             (55 * 1024)     /* 7 KB for stack */
 281 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 282
 283 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 284 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 285
 286 /* NAND boot config */
 287 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 288 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 289 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 290 #define CONFIG_SYS_NAND_OOBSIZE         64
 291 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 292 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 293 #define CONFIG_SYS_NAND_ECCPOS          {12, 13, 14, 15, 16, 17, 18, 19, 20,\
 294                         21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
 295                         34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\
 296                         47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\
 297                         60, 61, 62, 63}
 298
 299 #define CONFIG_SYS_NAND_ECCSIZE         512
 300 #define CONFIG_SYS_NAND_ECCBYTES        13
 301
 302 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 303
 304 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 305 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x200000
 306
 307 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 308 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 309
 310 #endif /* __CONFIG_H */