include/configs/tricorder.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * (C) Copyright 2012
   8  * Corscience GmbH & Co. KG
   9  * Thomas Weber <weber@corscience.de>
  10  *
  11  * Configuration settings for the Tricorder board.
  12  *
  13  * See file CREDITS for list of people who contributed to this
  14  * project.
  15  *
  16  * This program is free software; you can redistribute it and/or
  17  * modify it under the terms of the GNU General Public License as
  18  * published by the Free Software Foundation; either version 2 of
  19  * the License, or (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29  * MA 02111-1307 USA
  30  */
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_OMAP                     /* in a TI OMAP core */
  37 #define CONFIG_OMAP34XX                 /* which is a 34XX */
  38
  39 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
  40 /*
  41  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  42  * 64 bytes before this address should be set aside for u-boot.img's
  43  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  44  * other needs.
  45  */
  46 #define CONFIG_SYS_TEXT_BASE            0x80100000
  47
  48 #define CONFIG_SDRC                     /* The chip has SDRC controller */
  49
  50 #include <asm/arch/cpu.h>               /* get chip and board defs */
  51 #include <asm/arch/omap3.h>
  52
  53 /* Display CPU and Board information */
  54 #define CONFIG_DISPLAY_CPUINFO
  55 #define CONFIG_DISPLAY_BOARDINFO
  56
  57 /* Clock Defines */
  58 #define V_OSCK                          26000000 /* Clock output from T2 */
  59 #define V_SCLK                          (V_OSCK >> 1)
  60
  61 #undef CONFIG_USE_IRQ                   /* no support for IRQs */
  62 #define CONFIG_MISC_INIT_R
  63
  64 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  65 #define CONFIG_SETUP_MEMORY_TAGS
  66 #define CONFIG_INITRD_TAG
  67 #define CONFIG_REVISION_TAG
  68
  69 #define CONFIG_OF_LIBFDT
  70
  71 /* Size of malloc() pool */
  72 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  73                                                 /* Sector */
  74 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (512 << 10))
  75
  76 /* Hardware drivers */
  77
  78 /* NS16550 Configuration */
  79 #define CONFIG_SYS_NS16550
  80 #define CONFIG_SYS_NS16550_SERIAL
  81 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  82 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  83
  84 /* select serial console configuration */
  85 #define CONFIG_CONS_INDEX               3
  86 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  87 #define CONFIG_SERIAL3                  3
  88 #define CONFIG_BAUDRATE                 115200
  89 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  90                                         115200}
  91
  92 /* MMC */
  93 #define CONFIG_GENERIC_MMC
  94 #define CONFIG_MMC
  95 #define CONFIG_OMAP_HSMMC
  96 #define CONFIG_DOS_PARTITION
  97
  98 /* I2C */
  99 #define CONFIG_HARD_I2C
 100 #define CONFIG_SYS_I2C_SPEED            100000
 101 #define CONFIG_SYS_I2C_SLAVE            1
 102 #define CONFIG_SYS_I2C_BUS              0
 103 #define CONFIG_SYS_I2C_BUS_SELECT       1
 104 #define CONFIG_DRIVER_OMAP34XX_I2C      1
 105
 106 /* TWL4030 */
 107 #define CONFIG_TWL4030_POWER
 108 #define CONFIG_TWL4030_LED
 109
 110 /* Board NAND Info */
 111 #define CONFIG_SYS_NO_FLASH             /* no NOR flash */
 112 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 113 #define MTDIDS_DEFAULT                  "nand0=nand"
 114 #define MTDPARTS_DEFAULT                "mtdparts=nand:" \
 115                                                 "512k(u-boot-spl)," \
 116                                                 "1920k(u-boot)," \
 117                                                 "128k(u-boot-env)," \
 118                                                 "4m(kernel)," \
 119                                                 "-(fs)"
 120
 121 #define CONFIG_NAND_OMAP_GPMC
 122 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 123                                                         /* to access nand */
 124 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 125                                                         /* to access nand at */
 126                                                         /* CS0 */
 127 #define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 128
 129 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 130                                                         /* devices */
 131
 132 /* commands to include */
 133 #include <config_cmd_default.h>
 134
 135 #define CONFIG_CMD_EXT2                 /* EXT2 Support */
 136 #define CONFIG_CMD_FAT                  /* FAT support */
 137 #define CONFIG_CMD_I2C                  /* I2C serial bus support */
 138 #define CONFIG_CMD_MMC                  /* MMC support */
 139 #define CONFIG_CMD_MTDPARTS             /* Enable MTD parts commands */
 140 #define CONFIG_CMD_NAND                 /* NAND support */
 141 #define CONFIG_CMD_NAND_LOCK_UNLOCK     /* nand (un)lock commands */
 142 #define CONFIG_CMD_UBI                  /* UBIFS commands */
 143
 144 #undef CONFIG_CMD_NET
 145 #undef CONFIG_CMD_NFS
 146 #undef CONFIG_CMD_FPGA                  /* FPGA configuration Support */
 147 #undef CONFIG_CMD_IMI                   /* iminfo */
 148 #undef CONFIG_CMD_JFFS2                 /* JFFS2 Support */
 149
 150 /* needed for ubi */
 151 #define CONFIG_RBTREE
 152 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 153 #define CONFIG_MTD_PARTITIONS
 154
 155 /* Environment information */
 156 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 157
 158 #define CONFIG_BOOTDELAY                3
 159
 160 #define CONFIG_EXTRA_ENV_SETTINGS \
 161         "loadaddr=0x82000000\0" \
 162         "console=ttyO2,115200n8\0" \
 163         "mmcdev=0\0" \
 164         "vram=12M\0" \
 165         "lcdmode=800x600\0" \
 166         "defaultdisplay=lcd\0" \
 167         "kernelopts=rw rootwait\0" \
 168         "commonargs=" \
 169                 "setenv bootargs console=${console} " \
 170                 "vram=${vram} " \
 171                 "omapfb.mode=lcd:${lcdmode} " \
 172                 "omapdss.def_disp=${defaultdisplay}\0" \
 173         "mmcargs=" \
 174                 "run commonargs; " \
 175                 "setenv bootargs ${bootargs} " \
 176                 "root=/dev/mmcblk0p2 " \
 177                 "${kernelopts}\0" \
 178         "nandargs=" \
 179                 "run commonargs; " \
 180                 "setenv bootargs ${bootargs} " \
 181                 "omapfb.mode=lcd:${lcdmode} " \
 182                 "omapdss.def_disp=${defaultdisplay} " \
 183                 "root=ubi0:rootfs " \
 184                 "rootfstype=ubifs " \
 185                 "${kernelopts}\0" \
 186         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 187         "bootscript=echo Running bootscript from mmc ...; " \
 188                 "source ${loadaddr}\0" \
 189         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 190         "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
 191         "mmcboot=echo Booting from mmc ...; " \
 192                 "run mmcargs; " \
 193                 "bootm ${loadaddr}\0" \
 194         "nandboot=echo Booting from nand ...; " \
 195                 "run nandargs; " \
 196                 "nand read ${loadaddr} 280000 400000; " \
 197                 "bootm ${loadaddr}\0" \
 198         "autoboot=if mmc rescan ${mmcdev}; then " \
 199                         "if run loadbootscript; then " \
 200                                 "run bootscript; " \
 201                         "else " \
 202                                 "if run loaduimage; then " \
 203                                         "run mmcboot; " \
 204                                 "else run nandboot; " \
 205                                 "fi; " \
 206                         "fi; " \
 207                 "else run nandboot; fi\0"
 208
 209
 210 #define CONFIG_BOOTCOMMAND "run autoboot"
 211
 212 /* Miscellaneous configurable options */
 213 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 214 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 215 #define CONFIG_AUTO_COMPLETE
 216 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 217 #define CONFIG_SYS_PROMPT               "OMAP3 Tricorder # "
 218 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 219 /* Print Buffer Size */
 220 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 221                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 222 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 223
 224 /* Boot Argument Buffer Size */
 225 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 226
 227 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x07000000)
 228 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 229                                         0x01000000) /* 16MB */
 230
 231 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 232
 233 /*
 234  * OMAP3 has 12 GP timers, they can be driven by the system clock
 235  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 236  * This rate is divided by a local divisor.
 237  */
 238 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 239 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 240 #define CONFIG_SYS_HZ                   1000
 241
 242 /* The stack sizes are set up in start.S using the settings below */
 243 #define CONFIG_STACKSIZE                (128 << 10) /* regular stack 128 KiB */
 244
 245 /*  Physical Memory Map  */
 246 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
 247 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 248 #define PHYS_SDRAM_1_SIZE               (128 << 20)     /* at least 128 MiB */
 249 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 250
 251 /* NAND and environment organization  */
 252 #define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 253
 254 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 255
 256 #define CONFIG_ENV_IS_IN_NAND           1
 257 #define CONFIG_ENV_OFFSET               0x260000 /* environment starts here */
 258
 259 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 260 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 261 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 262 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 263                                                 CONFIG_SYS_INIT_RAM_SIZE - \
 264                                                 GENERATED_GBL_DATA_SIZE)
 265
 266 /* SRAM config */
 267 #define CONFIG_SYS_SRAM_START           0x40200000
 268 #define CONFIG_SYS_SRAM_SIZE            0x10000
 269
 270 /* Defines for SPL */
 271 #define CONFIG_SPL
 272 #define CONFIG_SPL_NAND_SIMPLE
 273
 274 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 275 #define CONFIG_SPL_LIBDISK_SUPPORT
 276 #define CONFIG_SPL_I2C_SUPPORT
 277 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 278 #define CONFIG_SPL_SERIAL_SUPPORT
 279 #define CONFIG_SPL_POWER_SUPPORT
 280 #define CONFIG_SPL_NAND_SUPPORT
 281 #define CONFIG_SPL_MMC_SUPPORT
 282 #define CONFIG_SPL_FAT_SUPPORT
 283 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 284 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
 285 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 286 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 287
 288 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 289 #define CONFIG_SPL_MAX_SIZE             0xB400  /* 45 K */
 290 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 291
 292 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 293 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 294
 295 /* NAND boot config */
 296 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 297 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 298 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 299 #define CONFIG_SYS_NAND_OOBSIZE         64
 300 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 301 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 302 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 303                                                 10, 11, 12, 13}
 304
 305 #define CONFIG_SYS_NAND_ECCSIZE         512
 306 #define CONFIG_SYS_NAND_ECCBYTES        3
 307
 308 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 309
 310 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 311 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x200000
 312
 313 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 314 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 315
 316 #endif /* __CONFIG_H */