2 * Copyright (C) 2012 <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0
11 #define CONFIG_MX28 /* must be defined before including regs-base.h */
13 #include <asm/sizes.h>
14 #include <asm/arch/regs-base.h>
17 * Ka-Ro TX28 board - SoC configuration
19 #define CONFIG_MXS_GPIO /* GPIO control */
20 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
21 #define PHYS_SDRAM_1_SIZE CONFIG_SDRAM_SIZE
23 #define TX28_MOD_SUFFIX "1"
25 #define CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
26 #define TX28_MOD_SUFFIX "0"
29 #ifndef CONFIG_SPL_BUILD
30 #define CONFIG_SKIP_LOWLEVEL_INIT
31 #define CONFIG_SHOW_ACTIVITY
32 #define CONFIG_ARCH_CPU_INIT
33 #define CONFIG_ARCH_MISC_INIT /* init vector table after relocation */
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
36 #define CONFIG_BOARD_LATE_INIT
37 #define CONFIG_BOARD_EARLY_INIT_F
39 /* LCD Logo and Splash screen support */
42 #define CONFIG_SPLASH_SCREEN
43 #define CONFIG_SPLASH_SCREEN_ALIGN
44 #define CONFIG_VIDEO_MXS
45 #define CONFIG_LCD_LOGO
46 #define LCD_BPP LCD_COLOR24
47 #define CONFIG_CMD_BMP
48 #define CONFIG_VIDEO_BMP_RLE8
49 #endif /* CONFIG_LCD */
50 #endif /* CONFIG_SPL_BUILD */
53 * Memory configuration options
55 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */
56 #define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */
57 #define CONFIG_STACKSIZE SZ_64K
58 #define CONFIG_SYS_MALLOC_LEN SZ_4M
59 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* Memtest start address */
60 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M)
63 * U-Boot general configurations
65 #define CONFIG_SYS_LONGHELP
66 #define CONFIG_SYS_PROMPT "TX28 U-Boot > "
67 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
68 #define CONFIG_SYS_PBSIZE \
69 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
70 /* Print buffer size */
71 #define CONFIG_SYS_MAXARGS 256 /* Max number of command args */
72 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
73 /* Boot argument buffer size */
74 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
75 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
76 #define CONFIG_CMDLINE_EDITING /* Command history etc */
78 #define CONFIG_SYS_64BIT_VSPRINTF
79 #define CONFIG_SYS_NO_FLASH
82 * Flattened Device Tree (FDT) support
84 #define CONFIG_OF_LIBFDT
85 #ifdef CONFIG_OF_LIBFDT
86 #define CONFIG_FDT_FIXUP_PARTITIONS
87 #define CONFIG_OF_BOARD_SETUP
88 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
94 #define xstr(s) str(s)
96 #define __pfx(x, s) (x##s)
97 #define _pfx(x, s) __pfx(x, s)
99 #define CONFIG_CMDLINE_TAG
100 #define CONFIG_SETUP_MEMORY_TAGS
101 #define CONFIG_BOOTDELAY 3
102 #define CONFIG_ZERO_BOOTDELAY_CHECK
103 #define CONFIG_SYS_AUTOLOAD "no"
104 #define CONFIG_BOOTFILE "uImage"
105 #define CONFIG_BOOTARGS "console=ttyAMA0,115200 ro debug panic=1"
106 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
107 #define CONFIG_LOADADDR 43000000
108 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
109 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
114 #ifdef CONFIG_ENV_IS_NOWHERE
115 #define CONFIG_EXTRA_ENV_SETTINGS \
119 "fdtaddr=11000000\0" \
120 "mtdids=" MTDIDS_DEFAULT "\0" \
121 "mtdparts=" MTDPARTS_DEFAULT "\0"
123 #define CONFIG_EXTRA_ENV_SETTINGS \
125 "baseboard=stk5-v3\0" \
126 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
127 " root=/dev/mmcblk0p3 rootwait\0" \
128 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
129 " root=/dev/mtdblock3 rootfstype=jffs2\0" \
130 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
131 " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0" \
132 "bootcmd_mmc=set autostart no;run bootargs_mmc" \
133 ";fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
134 "bootcmd_nand=set autostart no;run bootargs_nand" \
135 ";nboot linux;run bootm_cmd\0" \
136 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp" \
138 "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \
139 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
140 " ${append_bootargs}\0" \
141 "fdtaddr=41000000\0" \
142 "fdtsave=fdt resize;nand erase.part dtb" \
143 ";nand write ${fdtaddr} dtb ${fdtsize}\0" \
144 "mtdids=" MTDIDS_DEFAULT "\0" \
145 "mtdparts=" MTDPARTS_DEFAULT "\0" \
146 "nfsroot=/tftpboot/rootfs\0" \
147 "otg_mode=device\0" \
148 "touchpanel=tsc2007\0" \
150 #endif /* CONFIG_ENV_IS_NOWHERE */
152 #define MTD_NAME "gpmi-nand"
153 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
158 #include <config_cmd_default.h>
159 #define CONFIG_CMD_CACHE
160 #define CONFIG_CMD_MMC
161 #define CONFIG_CMD_NAND
162 #define CONFIG_CMD_MTDPARTS
163 #define CONFIG_CMD_BOOTCE
164 #define CONFIG_CMD_TIME
165 #define CONFIG_CMD_MEMTEST
170 #define CONFIG_PL011_SERIAL
171 #define CONFIG_PL011_CLOCK 24000000
172 #define CONFIG_PL01x_PORTS { \
173 (void *)MXS_UARTDBG_BASE, \
175 #define CONFIG_CONS_INDEX 0 /* do not change! */
176 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
177 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
178 #define CONFIG_SYS_CONSOLE_INFO_QUIET
183 #define CONFIG_FEC_MXC
184 #ifdef CONFIG_FEC_MXC
185 /* This is required for the FEC driver to work with cache enabled */
186 #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
187 #define CONFIG_SYS_CACHELINE_SIZE 32
189 #ifndef CONFIG_TX28_S
190 #define CONFIG_FEC_MXC_MULTI
192 #define IMX_FEC_BASE MXS_ENET0_BASE
193 #define CONFIG_FEC_MXC_PHYADDR 0x00
196 #define CONFIG_PHY_SMSC
197 #define CONFIG_PHYLIB
199 #define CONFIG_FEC_XCV_TYPE RMII
200 #define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
201 #define CONFIG_NET_MULTI
202 #define CONFIG_CMD_MII
203 #define CONFIG_CMD_DHCP
204 #define CONFIG_CMD_PING
205 /* Add for working with "strict" DHCP server */
206 #define CONFIG_BOOTP_SUBNETMASK
207 #define CONFIG_BOOTP_GATEWAY
208 #define CONFIG_BOOTP_DNS
209 #define CONFIG_BOOTP_RANDOM_ID
212 #ifndef CONFIG_ENV_IS_NOWHERE
213 /* define one of the following options:
214 #define CONFIG_ENV_IS_IN_NAND
215 #define CONFIG_ENV_IS_IN_MMC
217 #define CONFIG_ENV_IS_IN_NAND
219 #define CONFIG_ENV_OVERWRITE
224 #ifdef CONFIG_CMD_NAND
225 #define CONFIG_MTD_DEVICE
226 #define CONFIG_NAND_MXS
227 #define CONFIG_APBH_DMA
228 #define CONFIG_APBH_DMA_BURST
229 #define CONFIG_APBH_DMA_BURST8
230 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
231 #define CONFIG_CMD_NAND_TRIMFFS
232 #define CONFIG_SYS_MXS_DMA_CHANNEL 4
233 #define CONFIG_SYS_MAX_FLASH_SECT 1024
234 #define CONFIG_SYS_MAX_FLASH_BANKS 1
235 #define CONFIG_SYS_NAND_MAX_CHIPS 1
236 #define CONFIG_SYS_MAX_NAND_DEVICE 1
237 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
238 #define CONFIG_SYS_NAND_USE_FLASH_BBT
239 #define CONFIG_SYS_NAND_BASE 0x00000000
240 #define CONFIG_CMD_ROMUPDATE
242 #undef CONFIG_ENV_IS_IN_NAND
243 #endif /* CONFIG_CMD_NAND */
245 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
246 #define CONFIG_ENV_SIZE SZ_128K
247 #define CONFIG_ENV_RANGE 0x60000
248 #ifdef CONFIG_ENV_OFFSET_REDUND
249 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
251 xstr(CONFIG_ENV_RANGE) \
253 #define CONFIG_SYS_USERFS_PART_STR "89216k(userfs)"
255 #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_ENV_RANGE) \
257 #define CONFIG_SYS_USERFS_PART_STR "89600k(userfs)"
258 #endif /* CONFIG_ENV_OFFSET_REDUND */
263 #ifdef CONFIG_CMD_MMC
265 #define CONFIG_GENERIC_MMC
266 #define CONFIG_MXS_MMC
267 #define CONFIG_BOUNCE_BUFFER
269 #define CONFIG_DOS_PARTITION
270 #define CONFIG_CMD_FAT
271 #define CONFIG_FAT_WRITE
272 #define CONFIG_CMD_EXT2
275 * Environments on MMC
277 #ifdef CONFIG_ENV_IS_IN_MMC
278 #define CONFIG_SYS_MMC_ENV_DEV 0
279 #undef CONFIG_ENV_OFFSET
280 #undef CONFIG_ENV_SIZE
281 /* Associated with the MMC layout defined in mmcops.c */
282 #define CONFIG_ENV_OFFSET SZ_1K
283 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
284 #define CONFIG_DYNAMIC_MMC_DEVNO
285 #endif /* CONFIG_ENV_IS_IN_MMC */
287 #undef CONFIG_ENV_IS_IN_MMC
288 #endif /* CONFIG_CMD_MMC */
290 #ifdef CONFIG_ENV_IS_NOWHERE
291 #undef CONFIG_ENV_SIZE
292 #define CONFIG_ENV_SIZE SZ_4K
295 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
296 "1m@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) "(u-boot)," \
297 CONFIG_SYS_ENV_PART_STR \
298 "6m(linux),32m(rootfs)," \
299 CONFIG_SYS_USERFS_PART_STR ",512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro"
301 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
302 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
303 GENERATED_GBL_DATA_SIZE)
305 /* Defines for SPL */
307 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
308 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
309 #define CONFIG_SPL_LIBCOMMON_SUPPORT
310 #define CONFIG_SPL_LIBGENERIC_SUPPORT
311 #define CONFIG_SPL_SERIAL_SUPPORT
312 #define CONFIG_SPL_GPIO_SUPPORT
313 #define CONFIG_SYS_SPL_VDDD_VAL 1500
314 #define CONFIG_SYS_SPL_BATT_BO_LEVEL 2800
315 #define CONFIG_SYS_SPL_VDDMEM_VAL 0 /* VDDMEM is not utilized on TX28 */
317 #endif /* __CONFIGS_TX28_H */