include/configs/tx48.h

   1 /*
   2  * tx48.h
   3  *
   4  * Copyright (C) 2012-2014 Lothar Waßmann <LW@KARO-electronics.de>
   5  *
   6  * based on: am335x_evm
   7  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * SPDX-License-Identifier:      GPL-2.0
  10  *
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #define CONFIG_AM33XX                   /* must be set before including omap.h */
  17
  18 #include <asm/sizes.h>
  19 #include <asm/arch/omap.h>
  20
  21 /*
  22  * Ka-Ro TX48 board - SoC configuration
  23  */
  24 #define CONFIG_OMAP
  25 #define CONFIG_AM33XX_GPIO
  26 #define CONFIG_SYS_HZ                   1000    /* Ticks per second */
  27
  28 #ifndef CONFIG_SPL_BUILD
  29 #define CONFIG_SKIP_LOWLEVEL_INIT
  30 #define CONFIG_SHOW_ACTIVITY
  31 #define CONFIG_DISPLAY_CPUINFO
  32 #define CONFIG_DISPLAY_BOARDINFO
  33 #define CONFIG_BOARD_LATE_INIT
  34
  35 /* LCD Logo and Splash screen support */
  36 #define CONFIG_LCD
  37 #ifdef CONFIG_LCD
  38 #define CONFIG_SPLASH_SCREEN
  39 #define CONFIG_SPLASH_SCREEN_ALIGN
  40 #define CONFIG_VIDEO_DA8XX
  41 #define DAVINCI_LCD_CNTL_BASE           0x4830e000
  42 #define CONFIG_LCD_LOGO
  43 #define LCD_BPP                         LCD_COLOR24
  44 #define CONFIG_CMD_BMP
  45 #define CONFIG_VIDEO_BMP_RLE8
  46 #endif /* CONFIG_LCD */
  47 #endif /* CONFIG_SPL_BUILD */
  48
  49 /* Clock Defines */
  50 #define V_OSCK                          24000000  /* Clock output from T2 */
  51 #define V_SCLK                          V_OSCK
  52
  53 /*
  54  * Memory configuration options
  55  */
  56 #define CONFIG_SYS_SDRAM_DDR3
  57 #define CONFIG_NR_DRAM_BANKS            1               /*  1 bank of SDRAM */
  58 #define PHYS_SDRAM_1                    0x80000000      /* SDRAM Bank #1 */
  59 #define CONFIG_MAX_RAM_BANK_SIZE        SZ_1G
  60
  61 #define CONFIG_STACKSIZE                SZ_64K
  62 #define CONFIG_SYS_MALLOC_LEN           SZ_4M
  63
  64 #define CONFIG_SYS_MEMTEST_START        (PHYS_SDRAM_1 + SZ_64M)
  65 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + SZ_8M)
  66
  67 #define CONFIG_SYS_CACHELINE_SIZE       64
  68
  69 /*
  70  * U-Boot general configurations
  71  */
  72 #define CONFIG_SYS_LONGHELP
  73 #define CONFIG_SYS_PROMPT               "TX48 U-Boot > "
  74 #define CONFIG_SYS_CBSIZE               2048    /* Console I/O buffer size */
  75 #define CONFIG_SYS_PBSIZE \
  76         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  77                                                 /* Print buffer size */
  78 #define CONFIG_SYS_MAXARGS              64      /* Max number of command args */
  79 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
  80                                                 /* Boot argument buffer size */
  81 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
  82 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  83 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  84
  85 #define CONFIG_SYS_64BIT_VSPRINTF
  86 #define CONFIG_SYS_NO_FLASH
  87
  88 /*
  89  * Flattened Device Tree (FDT) support
  90 */
  91 #define CONFIG_OF_LIBFDT
  92 #define CONFIG_OF_BOARD_SETUP
  93 #define CONFIG_SYS_FDT_ADDR             (PHYS_SDRAM_1 + SZ_16M)
  94
  95 /*
  96  * Boot Linux
  97  */
  98 #define xstr(s)                         str(s)
  99 #define str(s)                          #s
 100 #define __pfx(x, s)                     (x##s)
 101 #define _pfx(x, s)                      __pfx(x, s)
 102
 103 #define CONFIG_CMDLINE_TAG
 104 #define CONFIG_SETUP_MEMORY_TAGS
 105 #define CONFIG_BOOTDELAY                3
 106 #define CONFIG_ZERO_BOOTDELAY_CHECK
 107 #define CONFIG_SYS_AUTOLOAD             "no"
 108 #define CONFIG_BOOTFILE                 "uImage"
 109 #define CONFIG_BOOTARGS                 "init=/linuxrc console=ttyO0,115200 ro debug panic=1"
 110 #define CONFIG_BOOTCOMMAND              "run bootcmd_nand"
 111 #define CONFIG_LOADADDR                 83000000
 112 #define CONFIG_SYS_LOAD_ADDR            _pfx(0x, CONFIG_LOADADDR)
 113 #define CONFIG_U_BOOT_IMG_SIZE          SZ_1M
 114 #define CONFIG_HW_WATCHDOG
 115
 116 /*
 117  * Extra Environment Settings
 118  */
 119 #define CONFIG_SYS_CPU_CLK_STR          xstr(CONFIG_SYS_MPU_CLK)
 120 #ifdef CONFIG_OF_LIBFDT
 121 #define TX48_BOOTM_CMD                                                  \
 122         "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0"
 123 #define TX48_MTDPARTS_CMD ""
 124 #else
 125 #define TX48_BOOTM_CMD                                                  \
 126         "bootm_cmd=bootm\0"
 127 #define TX48_MTDPARTS_CMD " ${mtdparts}"
 128 #endif
 129
 130 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 131         "autostart=no\0"                                                \
 132         "baseboard=stk5-v3\0"                                           \
 133         "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}"    \
 134         " root=/dev/mmcblk0p2 rootwait\0"                               \
 135         "bootargs_nand=run default_bootargs;set bootargs ${bootargs}"   \
 136         " root=/dev/mtdblock4 rootfstype=jffs2\0"                       \
 137         "nfsroot=/tftpboot/rootfs\0"                                    \
 138         "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}"    \
 139         " root=/dev/nfs ip=dhcp nfsroot=${nfs_server}:${nfsroot},nolock\0"\
 140         "bootcmd_mmc=set autostart no;run bootargs_mmc;"                \
 141         " fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0"             \
 142         "bootcmd_nand=set autostart no;run bootargs_nand;"              \
 143         " nboot linux;run bootm_cmd\0"                                  \
 144         "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;"           \
 145         " run bootm_cmd\0"                                              \
 146         TX48_BOOTM_CMD                                                  \
 147         "cpu_clk=" CONFIG_SYS_CPU_CLK_STR "\0"                          \
 148         "default_bootargs=set bootargs " CONFIG_BOOTARGS                \
 149         TX48_MTDPARTS_CMD                                               \
 150         " ${append_bootargs}\0"                 \
 151         "fdtaddr=81000000\0"                                            \
 152         "fdtsave=nand erase.part dtb;nand write ${fdtaddr} dtb ${fdtsize}\0" \
 153         "mtdids=" MTDIDS_DEFAULT "\0"                                   \
 154         "mtdparts=" MTDPARTS_DEFAULT "\0"                               \
 155         "nfsroot=/tftpboot/rootfs\0"                                    \
 156         "otg_mode=device\0"                                             \
 157         "touchpanel=tsc2007\0"                                          \
 158         "video_mode=VGA\0"
 159
 160 #define MTD_NAME                        "omap2-nand.0"
 161 #define MTDIDS_DEFAULT                  "nand0=" MTD_NAME
 162 #define CONFIG_FDT_FIXUP_PARTITIONS
 163
 164 /*
 165  * U-Boot Commands
 166  */
 167 #include <config_cmd_default.h>
 168 #define CONFIG_CMD_CACHE
 169 #define CONFIG_CMD_MMC
 170 #define CONFIG_CMD_NAND
 171 #define CONFIG_CMD_MTDPARTS
 172 #define CONFIG_CMD_BOOTCE
 173 #define CONFIG_CMD_TIME
 174 #define CONFIG_CMD_MEMTEST
 175
 176 /*
 177  * Serial Driver
 178  */
 179 #define CONFIG_SYS_NS16550
 180 #define CONFIG_SYS_NS16550_SERIAL
 181 #define CONFIG_SYS_NS16550_MEM32
 182 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
 183 #define CONFIG_SYS_NS16550_CLK          48000000
 184 #define CONFIG_SYS_NS16550_COM1         0x44e09000      /* UART0 */
 185 #define CONFIG_SYS_NS16550_COM2         0x48022000      /* UART1 */
 186 #define CONFIG_SYS_NS16550_COM6         0x481aa000      /* UART5 */
 187
 188 #define CONFIG_SYS_NS16550_COM3         0x481aa000      /* UART2 */
 189 #define CONFIG_SYS_NS16550_COM4         0x481aa000      /* UART3 */
 190 #define CONFIG_SYS_NS16550_COM5         0x481aa000      /* UART4 */
 191 #define CONFIG_CONS_INDEX               1               /* one based! */
 192 #define CONFIG_BAUDRATE                 115200          /* Default baud rate */
 193 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, }
 194 #define CONFIG_SYS_CONSOLE_INFO_QUIET
 195
 196 /*
 197  * Ethernet Driver
 198  */
 199 #ifdef CONFIG_CMD_NET
 200 #define CONFIG_DRIVER_TI_CPSW
 201 #define CONFIG_NET_MULTI
 202 #define CONFIG_PHY_GIGE
 203 #define CONFIG_PHY_SMSC
 204 #define CONFIG_PHYLIB
 205 #define CONFIG_MII
 206 #define CONFIG_CMD_MII
 207 #define CONFIG_CMD_DHCP
 208 #define CONFIG_CMD_PING
 209 /* Add for working with "strict" DHCP server */
 210 #define CONFIG_BOOTP_SUBNETMASK
 211 #define CONFIG_BOOTP_GATEWAY
 212 #define CONFIG_BOOTP_DNS
 213 #define CONFIG_BOOTP_DNS2
 214 #endif
 215
 216 /*
 217  * NAND flash driver
 218  */
 219 #ifdef CONFIG_CMD_NAND
 220 #define CONFIG_MTD_DEVICE
 221 #define CONFIG_ENV_IS_IN_NAND
 222 #define CONFIG_NAND_OMAP_GPMC
 223 #ifndef CONFIG_SPL_BUILD
 224 #define CONFIG_SYS_GPMC_PREFETCH_ENABLE
 225 #endif
 226 #define GPMC_NAND_ECC_LP_x8_LAYOUT
 227 #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL  GPMC_NAND_HW_ECC_LAYOUT
 228 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 229 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 230 #define CONFIG_SYS_NAND_OOBSIZE         64
 231 #define CONFIG_SYS_NAND_ECCSIZE         512
 232 #define CONFIG_SYS_NAND_ECCBYTES        14
 233 #define CONFIG_CMD_NAND_TRIMFFS
 234 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 235 #define CONFIG_SYS_NAND_MAXBAD          20 /* Max. number of bad blocks guaranteed by manufacturer */
 236 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 237 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 238 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 239 #ifdef CONFIG_ENV_IS_IN_NAND
 240 #define CONFIG_ENV_OVERWRITE
 241 #define CONFIG_ENV_OFFSET               (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
 242 #define CONFIG_ENV_SIZE                 SZ_128K
 243 #define CONFIG_ENV_RANGE                0x60000
 244 #endif /* CONFIG_ENV_IS_IN_NAND */
 245 #define CONFIG_SYS_NAND_BASE            0x00100000
 246 #define CONFIG_SYS_NAND_SIZE            SZ_128M
 247 #define NAND_BASE                       CONFIG_SYS_NAND_BASE
 248 #endif /* CONFIG_CMD_NAND */
 249
 250 /*
 251  * MMC Driver
 252  */
 253 #ifdef CONFIG_CMD_MMC
 254 #ifndef CONFIG_ENV_IS_IN_NAND
 255 #define CONFIG_ENV_IS_IN_MMC
 256 #endif
 257 #define CONFIG_MMC
 258 #define CONFIG_GENERIC_MMC
 259 #define CONFIG_OMAP_HSMMC
 260 #define CONFIG_OMAP_MMC_DEV_1
 261
 262 #define CONFIG_DOS_PARTITION
 263 #define CONFIG_CMD_FAT
 264 #define CONFIG_CMD_EXT2
 265
 266 /*
 267  * Environments on MMC
 268  */
 269 #ifdef CONFIG_ENV_IS_IN_MMC
 270 #define CONFIG_SYS_MMC_ENV_DEV          0
 271 #define CONFIG_ENV_OVERWRITE
 272 /* Associated with the MMC layout defined in mmcops.c */
 273 #define CONFIG_ENV_OFFSET               SZ_1K
 274 #define CONFIG_ENV_SIZE                 (SZ_128K - CONFIG_ENV_OFFSET)
 275 #define CONFIG_DYNAMIC_MMC_DEVNO
 276 #endif /* CONFIG_ENV_IS_IN_MMC */
 277 #endif /* CONFIG_CMD_MMC */
 278
 279 #ifdef CONFIG_ENV_OFFSET_REDUND
 280 #define MTDPARTS_DEFAULT                "mtdparts=" MTD_NAME ":"        \
 281         "128k(u-boot-spl),"                                             \
 282         "1m(u-boot),"                                                   \
 283         xstr(CONFIG_ENV_RANGE)                                          \
 284         "(env),"                                                        \
 285         xstr(CONFIG_ENV_RANGE)                                          \
 286         "(env2),4m(linux),16m(rootfs),107904k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
 287 #else
 288 #define MTDPARTS_DEFAULT                "mtdparts=" MTD_NAME ":"        \
 289         "128k(u-boot-spl),"                                             \
 290         "1m(u-boot),"                                                   \
 291         xstr(CONFIG_ENV_RANGE)                                          \
 292         "(env),4m(linux),16m(rootfs),108288k(userfs),256k(dtb),512k@0x7f80000(bbt)ro"
 293 #endif
 294
 295 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 296 #define SRAM0_SIZE                      SZ_64K
 297 #define OCMC_SRAM_BASE                  0x40300000
 298 #define CONFIG_SPL_STACK                (OCMC_SRAM_BASE + 0xb800)
 299 #define CONFIG_SYS_INIT_SP_ADDR         (PHYS_SDRAM_1 + SZ_32K)
 300
 301  /* Platform/Board specific defs */
 302 #define CONFIG_SYS_TIMERBASE            0x48040000      /* Use Timer2 */
 303 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 304
 305 /* Defines for SPL */
 306 #define CONFIG_SPL
 307 #define CONFIG_SPL_FRAMEWORK
 308 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
 309 #define CONFIG_SPL_GPIO_SUPPORT
 310 #ifdef CONFIG_NAND_OMAP_GPMC
 311 #define CONFIG_SPL_NAND_SUPPORT
 312 #define CONFIG_SPL_NAND_DRIVERS
 313 #define CONFIG_SPL_NAND_BASE
 314 #define CONFIG_SPL_NAND_ECC
 315 #define CONFIG_SPL_NAND_AM33XX_BCH
 316 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 317 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE /   \
 318                                         CONFIG_SYS_NAND_PAGE_SIZE)
 319 #define CONFIG_SYS_NAND_BLOCK_SIZE      SZ_128K
 320 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 321 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 322                                          10, 11, 12, 13, 14, 15, 16, 17, \
 323                                          18, 19, 20, 21, 22, 23, 24, 25, \
 324                                          26, 27, 28, 29, 30, 31, 32, 33, \
 325                                          34, 35, 36, 37, 38, 39, 40, 41, \
 326                                          42, 43, 44, 45, 46, 47, 48, 49, \
 327                                          50, 51, 52, 53, 54, 55, 56, 57, }
 328 #endif
 329
 330 #define CONFIG_SPL_BSS_START_ADDR       PHYS_SDRAM_1
 331 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_512K
 332
 333 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 334
 335 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 336 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 337 #define CONFIG_SPL_SERIAL_SUPPORT
 338 #define CONFIG_SPL_YMODEM_SUPPORT
 339 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 340
 341 /*
 342  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 343  * 64 bytes before this address should be set aside for u-boot.img's
 344  * header. That is 0x800FFFC0--0x80100000 should not be used for any
 345  * other needs.
 346  */
 347 #define CONFIG_SYS_SPL_MALLOC_START     (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
 348 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_1M
 349
 350 #endif  /* __CONFIG_H */