4 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef __CONFIGS_TX48_H
20 #define __CONFIGS_TX48_H
22 #include <asm/sizes.h>
25 * Ka-Ro TX48 board - SoC configuration
28 #define CONFIG_AM33XX_GPIO
29 #define CONFIG_SYS_HZ 1000 /* Ticks per second */
31 #ifndef CONFIG_SPL_BUILD
32 #define CONFIG_SKIP_LOWLEVEL_INIT
33 #define CONFIG_SHOW_ACTIVITY
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
36 #define CONFIG_BOARD_LATE_INIT
38 /* LCD Logo and Splash screen support */
41 #define CONFIG_SPLASH_SCREEN
42 #define CONFIG_SPLASH_SCREEN_ALIGN
43 #define CONFIG_VIDEO_DA8XX
44 #define DAVINCI_LCD_CNTL_BASE 0x4830e000
45 #define CONFIG_LCD_LOGO
46 #define LCD_BPP LCD_COLOR24
47 #define CONFIG_CMD_BMP
48 #define CONFIG_VIDEO_BMP_RLE8
49 #endif /* CONFIG_LCD */
50 #endif /* CONFIG_SPL_BUILD */
53 #define V_OSCK 24000000 /* Clock output from T2 */
57 * Memory configuration options
59 #define CONFIG_SYS_SDRAM_DDR3
60 #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of SDRAM */
61 #define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
62 #define CONFIG_MAX_RAM_BANK_SIZE SZ_1G
64 #define CONFIG_STACKSIZE SZ_64K
65 #define CONFIG_SYS_MALLOC_LEN SZ_4M
67 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_64M)
68 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_8M)
69 #define CONFIG_SYS_SDRAM_CLK 266
71 #define CONFIG_SYS_CACHELINE_SIZE 64
74 * U-Boot general configurations
76 #define CONFIG_SYS_LONGHELP
77 #define CONFIG_SYS_PROMPT "TX48 U-Boot > "
78 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */
79 #define CONFIG_SYS_PBSIZE \
80 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
81 /* Print buffer size */
82 #define CONFIG_SYS_MAXARGS 64 /* Max number of command args */
83 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
84 /* Boot argument buffer size */
85 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */
86 #define CONFIG_AUTO_COMPLETE /* Command auto complete */
87 #define CONFIG_CMDLINE_EDITING /* Command history etc */
89 #define CONFIG_SYS_64BIT_VSPRINTF
90 #define CONFIG_SYS_NO_FLASH
93 * Flattened Device Tree (FDT) support
95 #ifdef CONFIG_OF_LIBFDT /* set via cmdline parameter thru boards.cfg */
96 #define CONFIG_FDT_FIXUP_PARTITIONS
97 #define CONFIG_OF_EMBED
98 #define CONFIG_OF_BOARD_SETUP
99 #define CONFIG_DEFAULT_DEVICE_TREE tx48
100 #define CONFIG_ARCH_DEVICE_TREE am33xx
101 #define CONFIG_MACH_TYPE (-1)
102 #define CONFIG_SYS_FDT_ADDR (PHYS_SDRAM_1 + SZ_16M)
104 #ifndef MACH_TYPE_TIAM335EVM
105 #define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
107 #define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
113 #define xstr(s) str(s)
115 #define __pfx(x, s) (x##s)
116 #define _pfx(x, s) __pfx(x, s)
118 #define CONFIG_CMDLINE_TAG
119 #define CONFIG_SETUP_MEMORY_TAGS
120 #define CONFIG_BOOTDELAY 3
121 #define CONFIG_ZERO_BOOTDELAY_CHECK
122 #define CONFIG_SYS_AUTOLOAD "no"
123 #define CONFIG_BOOTFILE "uImage"
124 #define CONFIG_BOOTARGS "console=ttyO0,115200 ro debug panic=1"
125 #define CONFIG_BOOTCOMMAND "run bootcmd_nand"
126 #define CONFIG_LOADADDR 83000000
127 #define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR)
128 #define CONFIG_U_BOOT_IMG_SIZE SZ_1M
130 #define CONFIG_HW_WATCHDOG
136 #ifdef CONFIG_OF_LIBFDT
137 #define TX48_BOOTM_CMD \
138 "bootm_cmd=fdt boardsetup;bootm ${loadaddr} - ${fdtaddr}\0"
139 #define TX48_MTDPARTS_CMD ""
141 #define TX48_BOOTM_CMD \
143 #define TX48_MTDPARTS_CMD "${mtdparts} "
146 #define CONFIG_EXTRA_ENV_SETTINGS \
148 "baseboard=stk5-v3\0" \
149 "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \
150 " root=/dev/mmcblk0p2 rootwait\0" \
151 "bootargs_nand=run default_bootargs;set bootargs ${bootargs}" \
152 " root=/dev/mtdblock4 rootfstype=jffs2\0" \
153 "nfsroot=/tftpboot/rootfs\0" \
154 "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \
155 " root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},nolock\0"\
156 "bootcmd_mmc=set autostart no;run bootargs_mmc;" \
157 " fatload mmc 0 ${loadaddr} uImage;run bootm_cmd\0" \
158 "bootcmd_nand=set autostart no;run bootargs_nand;" \
159 " nboot linux;run bootm_cmd\0" \
160 "bootcmd_net=set autostart no;run bootargs_nfs;dhcp;" \
163 "default_bootargs=set bootargs " CONFIG_BOOTARGS \
165 " video=${video_mode} ${append_bootargs}\0" \
167 "fdtaddr=81000000\0" \
168 "mtdids=" MTDIDS_DEFAULT "\0" \
169 "mtdparts=" MTDPARTS_DEFAULT "\0" \
170 "otg_mode=device\0" \
171 "touchpanel=tsc2007\0" \
172 "video_mode=640x480MR-24@60\0"
174 #define MTD_NAME "omap2-nand.0"
175 #define MTDIDS_DEFAULT "nand0=" MTD_NAME
180 #include <config_cmd_default.h>
181 #define CONFIG_CMD_CACHE
182 #define CONFIG_CMD_MMC
183 #define CONFIG_CMD_NAND
184 #define CONFIG_CMD_MTDPARTS
185 #define CONFIG_CMD_BOOTCE
186 #define CONFIG_CMD_TIME
191 #define CONFIG_SYS_NS16550
192 #define CONFIG_SYS_NS16550_SERIAL
193 #define CONFIG_SYS_NS16550_MEM32
194 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
195 #define CONFIG_SYS_NS16550_CLK 48000000
196 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
197 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
198 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
200 #define CONFIG_SYS_NS16550_COM3 0x481aa000 /* UART2 */
201 #define CONFIG_SYS_NS16550_COM4 0x481aa000 /* UART3 */
202 #define CONFIG_SYS_NS16550_COM5 0x481aa000 /* UART4 */
203 #define CONFIG_CONS_INDEX 1 /* one based! */
204 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
205 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, }
206 #define CONFIG_SYS_CONSOLE_INFO_QUIET
211 #ifdef CONFIG_CMD_NET
212 #define CONFIG_DRIVER_TI_CPSW
213 #define CONFIG_NET_MULTI
214 #define CONFIG_PHY_GIGE
215 #define CONFIG_PHY_SMSC
216 #define CONFIG_PHYLIB
218 #define CONFIG_CMD_MII
219 #define CONFIG_CMD_DHCP
220 #define CONFIG_CMD_PING
221 /* Add for working with "strict" DHCP server */
222 #define CONFIG_BOOTP_SUBNETMASK
223 #define CONFIG_BOOTP_GATEWAY
224 #define CONFIG_BOOTP_DNS
225 #define CONFIG_BOOTP_DNS2
231 #ifdef CONFIG_CMD_NAND
232 #define CONFIG_MTD_DEVICE
233 #define CONFIG_ENV_IS_IN_NAND
234 #define CONFIG_NAND_AM33XX
235 #define GPMC_NAND_ECC_LP_x8_LAYOUT
236 #define GPMC_NAND_HW_ECC_LAYOUT_KERNEL GPMC_NAND_HW_ECC_LAYOUT
237 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
238 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
239 #define CONFIG_SYS_NAND_OOBSIZE 64
240 #define CONFIG_SYS_NAND_ECCSIZE 512
241 #define CONFIG_SYS_NAND_ECCBYTES 14
242 #define CONFIG_CMD_NAND_TRIMFFS
243 #define CONFIG_SYS_NAND_MAX_CHIPS 1
244 #define CONFIG_SYS_NAND_MAXBAD 20 /* Max. number of bad blocks guaranteed by manufacturer */
245 #define CONFIG_SYS_MAX_NAND_DEVICE 1
246 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
247 #define CONFIG_SYS_NAND_USE_FLASH_BBT
248 #ifdef CONFIG_ENV_IS_IN_NAND
249 #define CONFIG_ENV_OVERWRITE
250 #define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
251 #define CONFIG_ENV_SIZE SZ_128K
252 #define CONFIG_ENV_RANGE 0x60000
253 #endif /* CONFIG_ENV_IS_IN_NAND */
254 #define CONFIG_SYS_NAND_BASE 0x08000000 /* must be defined but value is irrelevant */
255 #define NAND_BASE CONFIG_SYS_NAND_BASE
256 #endif /* CONFIG_CMD_NAND */
261 #ifdef CONFIG_CMD_MMC
262 #ifndef CONFIG_ENV_IS_IN_NAND
263 #define CONFIG_ENV_IS_IN_MMC
266 #define CONFIG_GENERIC_MMC
267 #define CONFIG_OMAP_HSMMC
268 #define CONFIG_OMAP_MMC_DEV_1
270 #define CONFIG_DOS_PARTITION
271 #define CONFIG_CMD_FAT
272 #define CONFIG_CMD_EXT2
275 * Environments on MMC
277 #ifdef CONFIG_ENV_IS_IN_MMC
278 #define CONFIG_SYS_MMC_ENV_DEV 0
279 #define CONFIG_ENV_OVERWRITE
280 /* Associated with the MMC layout defined in mmcops.c */
281 #define CONFIG_ENV_OFFSET SZ_1K
282 #define CONFIG_ENV_SIZE (SZ_128K - CONFIG_ENV_OFFSET)
283 #define CONFIG_DYNAMIC_MMC_DEVNO
284 #endif /* CONFIG_ENV_IS_IN_MMC */
285 #endif /* CONFIG_CMD_MMC */
287 #ifdef CONFIG_ENV_OFFSET_REDUND
288 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
289 "128k(u-boot-spl)," \
291 xstr(CONFIG_ENV_RANGE) \
293 xstr(CONFIG_ENV_RANGE) \
294 "(env2),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
296 #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \
297 "128k(u-boot-spl)," \
299 xstr(CONFIG_ENV_RANGE) \
300 "(env),4m(linux),16m(rootfs),256k(dtb),-(userfs)"
303 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
304 #define SRAM0_SIZE SZ_64K
305 #define CONFIG_SYS_INIT_SP_ADDR 0x4030B7FC
306 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
308 /* Platform/Board specific defs */
309 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
310 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
312 /* Defines for SPL */
314 #define CONFIG_SPL_FRAMEWORK
315 #define CONFIG_SPL_BOARD_INIT
316 #define CONFIG_SPL_MAX_SIZE (46 * SZ_1K)
317 #define CONFIG_SPL_GPIO_SUPPORT
318 #ifdef CONFIG_NAND_OMAP_GPMC
319 #define CONFIG_SPL_NAND_AM33XX_BCH
320 #define CONFIG_SPL_NAND_SUPPORT
321 #define CONFIG_SPL_NAND_SIMPLE
322 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
323 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
324 CONFIG_SYS_NAND_PAGE_SIZE)
325 #define CONFIG_SYS_NAND_BLOCK_SIZE SZ_128K
326 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
327 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
328 10, 11, 12, 13, 14, 15, 16, 17, \
329 18, 19, 20, 21, 22, 23, 24, 25, \
330 26, 27, 28, 29, 30, 31, 32, 33, \
331 34, 35, 36, 37, 38, 39, 40, 41, \
332 42, 43, 44, 45, 46, 47, 48, 49, \
333 50, 51, 52, 53, 54, 55, 56, 57, }
336 #define CONFIG_SPL_BSS_START_ADDR PHYS_SDRAM_1
337 #define CONFIG_SPL_BSS_MAX_SIZE SZ_512K
339 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
341 #define CONFIG_SPL_LIBCOMMON_SUPPORT
342 #define CONFIG_SPL_LIBGENERIC_SUPPORT
343 #define CONFIG_SPL_SERIAL_SUPPORT
344 #define CONFIG_SPL_YMODEM_SUPPORT
345 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
348 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
349 * 64 bytes before this address should be set aside for u-boot.img's
350 * header. That is 0x800FFFC0--0x80100000 should not be used for any
353 #define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K)
354 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M
356 #endif /* __CONFIGS_TX48_H */