include/configs/vpac270.h

   1 /*
   2  * Voipac PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Board Configuration Options
  14  */
  15 #define CONFIG_CPU_PXA27X               1       /* Marvell PXA270 CPU */
  16 #define CONFIG_VPAC270          1       /* Voipac PXA270 board */
  17 #define CONFIG_SYS_TEXT_BASE    0xa0000000
  18
  19 #ifdef  CONFIG_ONENAND
  20 #define CONFIG_SPL_ONENAND_SUPPORT
  21 #define CONFIG_SPL_ONENAND_LOAD_ADDR    0x2000
  22 #define CONFIG_SPL_ONENAND_LOAD_SIZE    \
  23         (512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
  24 #define CONFIG_SPL_TEXT_BASE    0x5c000000
  25 #define CONFIG_SPL_LDSCRIPT     "board/vpac270/u-boot-spl.lds"
  26 #endif
  27
  28 /*
  29  * Environment settings
  30  */
  31 #define CONFIG_ENV_OVERWRITE
  32 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
  33 #define CONFIG_ARCH_CPU_INIT
  34 #define CONFIG_BOOTCOMMAND                                              \
  35         "if mmc init && fatload mmc 0 0xa4000000 uImage; then "         \
  36                 "bootm 0xa4000000; "                                    \
  37         "fi; "                                                          \
  38         "if usb reset && fatload usb 0 0xa4000000 uImage; then "        \
  39                 "bootm 0xa4000000; "                                    \
  40         "fi; "                                                          \
  41         "if ide reset && fatload ide 0 0xa4000000 uImage; then "        \
  42                 "bootm 0xa4000000; "                                    \
  43         "fi; "                                                          \
  44         "bootm 0x60000;"
  45
  46 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  47         "update_onenand="                                               \
  48                 "onenand erase 0x0 0x80000 ; "                          \
  49                 "onenand write 0xa0000000 0x0 0x80000"
  50
  51 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
  52 #define CONFIG_TIMESTAMP
  53 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  54 #define CONFIG_CMDLINE_TAG
  55 #define CONFIG_SETUP_MEMORY_TAGS
  56 #define CONFIG_LZMA                     /* LZMA compression support */
  57 #define CONFIG_OF_LIBFDT
  58
  59 /*
  60  * Serial Console Configuration
  61  */
  62 #define CONFIG_PXA_SERIAL
  63 #define CONFIG_FFUART                   1
  64 #define CONFIG_CONS_INDEX               3
  65 #define CONFIG_BAUDRATE                 115200
  66
  67 /*
  68  * Bootloader Components Configuration
  69  */
  70 #include <config_cmd_default.h>
  71
  72 #define CONFIG_CMD_ENV
  73 #undef  CONFIG_CMD_IMLS
  74 #define CONFIG_CMD_MMC
  75 #define CONFIG_CMD_USB
  76 #undef  CONFIG_LCD
  77 #define CONFIG_CMD_IDE
  78
  79 #ifdef  CONFIG_ONENAND
  80 #undef  CONFIG_CMD_FLASH
  81 #define CONFIG_CMD_ONENAND
  82 #else
  83 #define CONFIG_CMD_FLASH
  84 #undef  CONFIG_CMD_ONENAND
  85 #endif
  86
  87 /*
  88  * Networking Configuration
  89  *  chip on the Voipac PXA270 board
  90  */
  91 #ifdef  CONFIG_CMD_NET
  92 #define CONFIG_CMD_PING
  93 #define CONFIG_CMD_DHCP
  94
  95 #define CONFIG_DRIVER_DM9000            1
  96 #define CONFIG_DM9000_BASE              0x08000300      /* CS2 */
  97 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  98 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  99 #define CONFIG_NET_RETRY_COUNT          10
 100
 101 #define CONFIG_BOOTP_BOOTFILESIZE
 102 #define CONFIG_BOOTP_BOOTPATH
 103 #define CONFIG_BOOTP_GATEWAY
 104 #define CONFIG_BOOTP_HOSTNAME
 105 #endif
 106
 107 /*
 108  * MMC Card Configuration
 109  */
 110 #ifdef  CONFIG_CMD_MMC
 111 #define CONFIG_MMC
 112 #define CONFIG_GENERIC_MMC
 113 #define CONFIG_PXA_MMC_GENERIC
 114 #define CONFIG_SYS_MMC_BASE             0xF0000000
 115 #define CONFIG_CMD_FAT
 116 #define CONFIG_CMD_EXT2
 117 #define CONFIG_DOS_PARTITION
 118 #endif
 119
 120 /*
 121  * KGDB
 122  */
 123 #ifdef  CONFIG_CMD_KGDB
 124 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
 125 #endif
 126
 127 /*
 128  * HUSH Shell Configuration
 129  */
 130 #define CONFIG_SYS_HUSH_PARSER          1
 131
 132 #define CONFIG_SYS_LONGHELP
 133 #ifdef  CONFIG_SYS_HUSH_PARSER
 134 #define CONFIG_SYS_PROMPT               "$ "
 135 #else
 136 #endif
 137 #define CONFIG_SYS_CBSIZE               256
 138 #define CONFIG_SYS_PBSIZE               \
 139         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 140 #define CONFIG_SYS_MAXARGS              16
 141 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 142 #define CONFIG_SYS_DEVICE_NULLDEV       1
 143 #define CONFIG_CMDLINE_EDITING          1
 144 #define CONFIG_AUTO_COMPLETE            1
 145
 146 /*
 147  * Clock Configuration
 148  */
 149 #define CONFIG_SYS_CPUSPEED             0x190           /* 312MHz */
 150
 151
 152 /*
 153  * DRAM Map
 154  */
 155 #define CONFIG_NR_DRAM_BANKS            2               /* 2 banks of DRAM */
 156 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 157 #define PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
 158
 159 #ifdef  CONFIG_RAM_256M
 160 #define PHYS_SDRAM_2                    0x80000000      /* SDRAM Bank #2 */
 161 #define PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
 162 #endif
 163
 164 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 165 #ifdef  CONFIG_RAM_256M
 166 #define CONFIG_SYS_DRAM_SIZE            0x10000000      /* 256 MB DRAM */
 167 #else
 168 #define CONFIG_SYS_DRAM_SIZE            0x08000000      /* 128 MB DRAM */
 169 #endif
 170
 171 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 172 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 173
 174 #define CONFIG_SYS_LOAD_ADDR            PHYS_SDRAM_1
 175 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 176 #define CONFIG_SYS_INIT_SP_ADDR         0x5c010000
 177
 178 /*
 179  * NOR FLASH
 180  */
 181 #define CONFIG_SYS_MONITOR_BASE         0x0
 182 #define CONFIG_SYS_MONITOR_LEN          0x80000
 183 #define CONFIG_ENV_ADDR                 \
 184                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 185 #define CONFIG_ENV_SIZE                 0x20000
 186 #define CONFIG_ENV_SECT_SIZE            0x20000
 187
 188 #if     defined(CONFIG_CMD_FLASH)       /* NOR */
 189 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 190
 191 #ifdef  CONFIG_RAM_256M
 192 #define PHYS_FLASH_2                    0x02000000      /* Flash Bank #2 */
 193 #endif
 194
 195 #define CONFIG_SYS_FLASH_CFI
 196 #define CONFIG_FLASH_CFI_DRIVER         1
 197
 198 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 199 #ifdef  CONFIG_RAM_256M
 200 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 201 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2 }
 202 #else
 203 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 204 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 205 #endif
 206
 207 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ)
 208 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ)
 209
 210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 211 #define CONFIG_SYS_FLASH_PROTECTION             1
 212
 213 #define CONFIG_ENV_IS_IN_FLASH          1
 214
 215 #elif   defined(CONFIG_CMD_ONENAND)     /* OneNAND */
 216 #define CONFIG_SYS_NO_FLASH
 217 #define CONFIG_SYS_ONENAND_BASE         0x00000000
 218
 219 #define CONFIG_ENV_IS_IN_ONENAND        1
 220
 221 #else   /* No flash */
 222 #define CONFIG_SYS_NO_FLASH
 223 #define CONFIG_ENV_IS_NOWHERE
 224 #endif
 225
 226 /*
 227  * IDE
 228  */
 229 #ifdef  CONFIG_CMD_IDE
 230 #define CONFIG_LBA48
 231 #undef  CONFIG_IDE_LED
 232 #undef  CONFIG_IDE_RESET
 233
 234 #define __io
 235
 236 #define CONFIG_SYS_IDE_MAXBUS           1
 237 #define CONFIG_SYS_IDE_MAXDEVICE        1
 238
 239 #define CONFIG_SYS_ATA_BASE_ADDR        0x0c000000
 240 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0
 241
 242 #define CONFIG_SYS_ATA_DATA_OFFSET      0x120
 243 #define CONFIG_SYS_ATA_REG_OFFSET       0x120
 244 #define CONFIG_SYS_ATA_ALT_OFFSET       0x120
 245
 246 #define CONFIG_SYS_ATA_STRIDE           2
 247 #endif
 248
 249 /*
 250  * GPIO settings
 251  */
 252 #define CONFIG_SYS_GPSR0_VAL    0x01308800
 253 #define CONFIG_SYS_GPSR1_VAL    0x00cf0000
 254 #define CONFIG_SYS_GPSR2_VAL    0x922ac000
 255 #define CONFIG_SYS_GPSR3_VAL    0x0161e800
 256
 257 #define CONFIG_SYS_GPCR0_VAL    0x00010000
 258 #define CONFIG_SYS_GPCR1_VAL    0x0
 259 #define CONFIG_SYS_GPCR2_VAL    0x0
 260 #define CONFIG_SYS_GPCR3_VAL    0x0
 261
 262 #define CONFIG_SYS_GPDR0_VAL    0xcbb18800
 263 #define CONFIG_SYS_GPDR1_VAL    0xfccfa981
 264 #define CONFIG_SYS_GPDR2_VAL    0x922affff
 265 #define CONFIG_SYS_GPDR3_VAL    0x0161e904
 266
 267 #define CONFIG_SYS_GAFR0_L_VAL  0x00100000
 268 #define CONFIG_SYS_GAFR0_U_VAL  0xa5da8510
 269 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 270 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5a0aa
 271 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 272 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a401
 273 #define CONFIG_SYS_GAFR3_L_VAL  0x54010310
 274 #define CONFIG_SYS_GAFR3_U_VAL  0x00025401
 275
 276 #define CONFIG_SYS_PSSR_VAL     0x30
 277
 278 /*
 279  * Clock settings
 280  */
 281 #define CONFIG_SYS_CKEN         0x00500240
 282 #define CONFIG_SYS_CCCR         0x02000290
 283
 284 /*
 285  * Memory settings
 286  */
 287 #define CONFIG_SYS_MSC0_VAL     0x3ffc95f9
 288 #define CONFIG_SYS_MSC1_VAL     0x02ccf974
 289 #define CONFIG_SYS_MSC2_VAL     0x00000000
 290 #ifdef  CONFIG_RAM_256M
 291 #define CONFIG_SYS_MDCNFG_VAL   0x8ad30ad3
 292 #else
 293 #define CONFIG_SYS_MDCNFG_VAL   0x88000ad3
 294 #endif
 295 #define CONFIG_SYS_MDREFR_VAL   0x201fe01e
 296 #define CONFIG_SYS_MDMRS_VAL    0x00000000
 297 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
 298 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 299
 300 /*
 301  * PCMCIA and CF Interfaces
 302  */
 303 #define CONFIG_SYS_MECR_VAL     0x00000001
 304 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
 305 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 306 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
 307 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 308 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
 309 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 310
 311 /*
 312  * LCD
 313  */
 314 #ifdef  CONFIG_LCD
 315 #define CONFIG_VOIPAC_LCD
 316 #endif
 317
 318 /*
 319  * USB
 320  */
 321 #ifdef  CONFIG_CMD_USB
 322 #define CONFIG_USB_OHCI_NEW
 323 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 324 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
 325 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 326 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
 327 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "vpac270"
 328 #define CONFIG_USB_STORAGE
 329 #endif
 330
 331 #endif  /* __CONFIG_H */