nand_spl/nand_boot.c

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 #include <common.h>
  22 #include <nand.h>
  23 #include <asm/io.h>
  24
  25 #define CONFIG_SYS_NAND_READ_DELAY \
  26         { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
  27
  28 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  29
  30 #if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
  31 /*
  32  * NAND command for small page NAND devices (512)
  33  */
  34 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  35 {
  36         struct nand_chip *this = mtd->priv;
  37         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  38
  39         if (this->dev_ready)
  40                 while (!this->dev_ready(mtd))
  41                         ;
  42         else
  43                 CONFIG_SYS_NAND_READ_DELAY;
  44
  45         /* Begin command latch cycle */
  46         this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  47         /* Set ALE and clear CLE to start address cycle */
  48         /* Column address */
  49         this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  50         this->cmd_ctrl(mtd, page_addr & 0xff, 0); /* A[16:9] */
  51         this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, 0); /* A[24:17] */
  52 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
  53         /* One more address cycle for devices > 32MiB */
  54         this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[28:25] */
  55 #endif
  56         /* Latch in address */
  57         this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  58
  59         /*
  60          * Wait a while for the data to be ready
  61          */
  62         if (this->dev_ready)
  63                 while (!this->dev_ready(mtd))
  64                         ;
  65         else
  66                 CONFIG_SYS_NAND_READ_DELAY;
  67
  68         return 0;
  69 }
  70 #else
  71 /*
  72  * NAND command for large page NAND devices (2k)
  73  */
  74 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
  75 {
  76         struct nand_chip *this = mtd->priv;
  77         int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  78
  79         if (this->dev_ready)
  80                 while (!this->dev_ready(mtd))
  81                         ;
  82         else
  83                 CONFIG_SYS_NAND_READ_DELAY;
  84
  85         /* Emulate NAND_CMD_READOOB */
  86         if (cmd == NAND_CMD_READOOB) {
  87                 offs += CONFIG_SYS_NAND_PAGE_SIZE;
  88                 cmd = NAND_CMD_READ0;
  89         }
  90
  91         /* Begin command latch cycle */
  92         this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  93         /* Set ALE and clear CLE to start address cycle */
  94         /* Column address */
  95         this->cmd_ctrl(mtd, offs & 0xff,
  96                        NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  97         this->cmd_ctrl(mtd, (offs >> 8) & 0xff, 0); /* A[11:9] */
  98         /* Row address */
  99         this->cmd_ctrl(mtd, (page_addr & 0xff), 0); /* A[19:12] */
 100         this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), 0); /* A[27:20] */
 101 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 102         /* One more address cycle for devices > 128MiB */
 103         this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[31:28] */
 104 #endif
 105         /* Latch in address */
 106         this->cmd_ctrl(mtd, NAND_CMD_READSTART,
 107                        NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 108         this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 109
 110         /*
 111          * Wait a while for the data to be ready
 112          */
 113         if (this->dev_ready)
 114                 while (!this->dev_ready(mtd))
 115                         ;
 116         else
 117                 CONFIG_SYS_NAND_READ_DELAY;
 118
 119         return 0;
 120 }
 121 #endif
 122
 123 static int nand_is_bad_block(struct mtd_info *mtd, int block)
 124 {
 125         struct nand_chip *this = mtd->priv;
 126
 127         nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 128
 129         /*
 130          * Read one byte
 131          */
 132         if (readb(this->IO_ADDR_R) != 0xff)
 133                 return 1;
 134
 135         return 0;
 136 }
 137
 138 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
 139 {
 140         struct nand_chip *this = mtd->priv;
 141         u_char *ecc_calc;
 142         u_char *ecc_code;
 143         u_char *oob_data;
 144         int i;
 145         int eccsize = CONFIG_SYS_NAND_ECCSIZE;
 146         int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
 147         int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 148         uint8_t *p = dst;
 149         int stat;
 150
 151         nand_command(mtd, block, page, 0, NAND_CMD_READ0);
 152
 153         /* No malloc available for now, just use some temporary locations
 154          * in SDRAM
 155          */
 156         ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
 157         ecc_code = ecc_calc + 0x100;
 158         oob_data = ecc_calc + 0x200;
 159
 160         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 161                 this->ecc.hwctl(mtd, NAND_ECC_READ);
 162                 this->read_buf(mtd, p, eccsize);
 163                 this->ecc.calculate(mtd, p, &ecc_calc[i]);
 164         }
 165         this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 166
 167         /* Pick the ECC bytes out of the oob data */
 168         for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
 169                 ecc_code[i] = oob_data[nand_ecc_pos[i]];
 170
 171         eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
 172         p = dst;
 173
 174         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 175                 /* No chance to do something with the possible error message
 176                  * from correct_data(). We just hope that all possible errors
 177                  * are corrected by this routine.
 178                  */
 179                 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 180         }
 181
 182         return 0;
 183 }
 184
 185 static int nand_load(struct mtd_info *mtd, unsigned int offs,
 186                      unsigned int uboot_size, uchar *dst)
 187 {
 188         unsigned int block, lastblock;
 189         unsigned int page;
 190
 191         /*
 192          * offs has to be aligned to a page address!
 193          */
 194         block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 195         lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 196         page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
 197
 198         while (block <= lastblock) {
 199                 if (!nand_is_bad_block(mtd, block)) {
 200                         /*
 201                          * Skip bad blocks
 202                          */
 203                         while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 204                                 nand_read_page(mtd, block, page, dst);
 205                                 dst += CONFIG_SYS_NAND_PAGE_SIZE;
 206                                 page++;
 207                         }
 208
 209                         page = 0;
 210                 } else {
 211                         lastblock++;
 212                 }
 213
 214                 block++;
 215         }
 216
 217         return 0;
 218 }
 219
 220 /*
 221  * The main entry for NAND booting. It's necessary that SDRAM is already
 222  * configured and available since this code loads the main U-Boot image
 223  * from NAND into SDRAM and starts it from there.
 224  */
 225 void nand_boot(void)
 226 {
 227         struct nand_chip nand_chip;
 228         nand_info_t nand_info;
 229         int ret;
 230         __attribute__((noreturn)) void (*uboot)(void);
 231
 232         /*
 233          * Init board specific nand support
 234          */
 235         nand_info.priv = &nand_chip;
 236         nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void  __iomem *)CONFIG_SYS_NAND_BASE;
 237         nand_chip.dev_ready = NULL;     /* preset to NULL */
 238         board_nand_init(&nand_chip);
 239
 240         if (nand_chip.select_chip)
 241                 nand_chip.select_chip(&nand_info, 0);
 242
 243         /*
 244          * Load U-Boot image from NAND into RAM
 245          */
 246         ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
 247                         (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
 248
 249         if (nand_chip.select_chip)
 250                 nand_chip.select_chip(&nand_info, -1);
 251
 252         /*
 253          * Jump to U-Boot image
 254          */
 255         uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 256         (*uboot)();
 257 }