#include #include #include #include #include #include #ifndef CCM_CCR #error asm-offsets not included #endif #define DEBUG_LED_BIT 20 #define LED_GPIO_BASE GPIO2_BASE_ADDR #define LED_MUX_OFFSET 0x0ec #define LED_MUX_MODE 0x15 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK #ifdef PHYS_SDRAM_2_SIZE #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) #else #define SDRAM_SIZE PHYS_SDRAM_1_SIZE #endif #define CPU_2_BE_32(l) \ ((((l) << 24) & 0xFF000000) | \ (((l) << 8) & 0x00FF0000) | \ (((l) >> 8) & 0x0000FF00) | \ (((l) >> 24) & 0x000000FF)) #define CHECK_DCD_ADDR(a) ( \ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ ((a) >= 0x020E4000 && (a) <= 0x020E7FFF) /* IOMUXC GPR */ || \ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ ((a) >= 0x021B0000 && (a) <= 0x021B3FFF) /* MMDC */ || \ ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \ ((a) >= 0x80000000 && (a) <= 0xFFFF7FFF) /* SDRAM */ || \ ((a) >= 0x020D0000 && (a) <= 0x020D3FFF) /* EPIT */) .macro mxc_dcd_item addr, val .ifne CHECK_DCD_ADDR(\addr) .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val) .else .error "Address \addr not accessible from DCD" .endif .endm #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val) #define MXC_DCD_CMD_SZ_BYTE 1 #define MXC_DCD_CMD_SZ_SHORT 2 #define MXC_DCD_CMD_SZ_WORD 4 #define MXC_DCD_CMD_FLAG_WRITE 0x0 #define MXC_DCD_CMD_FLAG_CLR 0x1 #define MXC_DCD_CMD_FLAG_SET 0x3 #define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1)) #define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1)) #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1)) #define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1)) #define MXC_DCD_START \ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \ dcd_start: .macro MXC_DCD_END 1: .ifgt . - dcd_start - 1768 .error "DCD too large!" .endif dcd_end: .section ".pad" .section ".text" .endm #define MXC_DCD_CMD_WRT(type, flags) \ 1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type)) #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ 1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \ CPU_2_BE_32(addr), CPU_2_BE_32(mask) #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ 1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \ CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) #define MXC_DCD_CMD_NOP() \ 1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) #define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000) .macro CK_VAL, name, clks, offs, max .iflt \clks - \offs .set \name, 0 .else .ifle \clks - \offs - \max .set \name, \clks - \offs .else .error "Value \clks out of range for parameter \name" .endif .endif .endm .macro NS_VAL, name, ns, offs, max .iflt \ns - \offs .set \name, 0 .else CK_VAL \name, NS_TO_CK(\ns), \offs, \max .endif .endm .macro CK_MAX, name, ck1, ck2, offs, max .ifgt \ck1 - \ck2 CK_VAL \name, \ck1, \offs, \max .else CK_VAL \name, \ck2, \offs, \max .endif .endm #define MDMISC_DDR_TYPE_DDR3 0 #define MDMISC_DDR_TYPE_LPDDR2 1 #define MDMISC_DDR_TYPE_DDR2 2 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ /* DDR3 SDRAM */ #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE #define BANK_ADDR_BITS 2 #else #define BANK_ADDR_BITS 1 #endif #define SDRAM_BURST_LENGTH 8 #define RALAT 5 #define WALAT 1 #define BI_ON 1 #define ADDR_MIRROR 0 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII or MT41K128M16JT-125 */ #if SDRAM_CLK > 666 && SDRAM_CLK <= 800 #define CL_VAL 11 #define CWL_VAL 8 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666 #define CL_VAL 9 // or 10 #define CWL_VAL 7 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533 #define CL_VAL 7 // or 8 #define CWL_VAL 6 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400 #define CL_VAL 6 #define CWL_VAL 5 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333 #define CL_VAL 5 #define CWL_VAL 5 #else #error SDRAM clock out of range: 303 .. 800 #endif /* MDCFG0 0x0c */ NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) (MT41K128M16JT: 6ns) */ CK_MAX tXPDLL, NS_TO_CK(24), 10, 1, 15 /* clks - 1 (0..15) */ NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 30ns) */ CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ /* MDCFG1 0x10 */ CK_VAL tRCD, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */ CK_VAL tRP, PS_TO_CK(13750), 1, 7 /* clks - 1 (0..7) */ /* 13.75 (NT5CB128M16FP: 12.5ns) */ NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 49ns) */ CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) (MT41K128M16JT: 3.5ns) */ CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ /* MDCFG2 0x14 */ CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ /* (Jedec Standard) */ CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) (MT41K128M16JT: 6ns) */ /* MDOR 0x30 */ CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) /* MDOTC 0x08 */ CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */ CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 2ns .. 8.5ns */ CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */ CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */ /* MDPDC 0x04 */ CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 #define PRCT 0 #define PWDT 5 #define SLOW_PD 0 #define BOTH_CS_PD 1 #define MDPDC_VAL_0 ( \ (PRCT << 28) | \ (PRCT << 24) | \ (tCKE << 16) | \ (SLOW_PD << 7) | \ (BOTH_CS_PD << 6) | \ (tCKSRX << 3) | \ (tCKSRE << 0) \ ) #define MDPDC_VAL_1 (MDPDC_VAL_0 | \ (PWDT << 12) | \ (PWDT << 8) \ ) #define ROW_ADDR_BITS 14 #define COL_ADDR_BITS 10 #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ #define DLL_DISABLE 0 .iflt tWR - 7 .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ ((tWR + 1 - 4) << 9) | \ ((((tCL + 3) - 4) & 0x7) << 4) | \ ((((tCL + 3) - 4) & 0x8) >> 1)) .else .set mr0_val, ((1 << 8) /* DLL Reset */ | \ (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ (((tWR + 1) / 2) << 9) | \ ((((tCL + 3) - 4) & 0x7) << 4) | \ ((((tCL + 3) - 4) & 0x8) >> 1)) .endif #define mr1_val ( \ ((Rtt_Nom & 1) << 2) | \ (((Rtt_Nom >> 1) & 1) << 6) | \ (((Rtt_Nom >> 2) & 1) << 9) | \ (DLL_DISABLE << 0) | \ 0) #define mr2_val ( \ (Rtt_WR << 9) /* dynamic ODT */ | \ (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \ (1 << 6) | /* ASR: Automatic Self Refresh */ \ (((tCWL + 2) - 5) << 3) | \ 0) #define mr3_val 0 #define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ (1 << 15) /* CON_REQ */ | \ (3 << 4) /* MRS command */ | \ ((cs) << 3) | \ ((mr) << 0) | \ 0) #define MDCFG0_VAL ( \ (tRFC << 24) | \ (tXS << 16) | \ (tXP << 13) | \ (tXPDLL << 9) | \ (tFAW << 4) | \ (tCL << 0)) \ #define MDCFG1_VAL ( \ (tRCD << 29) | \ (tRP << 26) | \ (tRC << 21) | \ (tRAS << 16) | \ (tRPA << 15) | \ (tWR << 9) | \ (tMRD << 5) | \ (tCWL << 0)) \ #define MDCFG2_VAL ( \ (tDLLK << 16) | \ (tRTP << 6) | \ (tWTR << 3) | \ (tRRD << 0)) #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ ((COL_ADDR_BITS - 9) << 20) | \ (BURST_LEN << 19) | \ ((CONFIG_SYS_SDRAM_BUS_WIDTH / 32) << 16) | \ ((-1) << (32 - BANK_ADDR_BITS))) #define MDMISC_WALAT(n) (((n) & 3) << 16) #define MDMISC_RALAT(n) (((n) & 7) << 6) #define CK1_GATING (2 - BANK_ADDR_BITS) #define MDMISC_VAL ((CK1_GATING << 21) | \ (ADDR_MIRROR << 19) | \ MDMISC_WALAT(WALAT) | \ (BI_ON << 12) | \ (0x3 << 9) | \ MDMISC_RALAT(RALAT) | \ (DDR_TYPE << 3)) #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) #define MDOTC_VAL ((tAOFPD << 27) | \ (tAONPD << 24) | \ (tANPD << 20) | \ (tAXPD << 16) | \ (tODTLon << 12) | \ (tODTLoff << 4)) .section ".ivt" ivt_header: .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) app_start_addr: .long _start .long 0x0 dcd_ptr: .long dcd_hdr boot_data_ptr: .word boot_data self_ptr: .word ivt_header app_code_csf: #ifdef CONFIG_SECURE_BOOT .word __csf_data #else .word 0x0 #endif .word 0x0 boot_data: .long CONFIG_SYS_TEXT_BASE image_len: .long __uboot_img_len plugin: .word 0 ivt_end: #define DCD_VERSION 0x40 #define DDR_SEL_VAL 3 /* DDR3 */ #if CONFIG_SYS_SDRAM_BUS_WIDTH == 16 #define DSE1_VAL 6 /* Drive Strength for DATA lines */ #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */ #else #define DSE1_VAL 6 /* Drive Strength for DATA lines */ #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */ #endif #define ODT_VAL 2 #define DDR_PKE_VAL 0 #define DDR_SEL_SHIFT 18 #define DDR_MODE_SHIFT 17 #define ODT_SHIFT 8 #define DSE_SHIFT 3 #define HYS_SHIFT 16 #define PKE_SHIFT 12 #define PUE_SHIFT 13 #define PUS_SHIFT 14 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) #define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */ #define DSE1_MASK (DSE1_VAL << DSE_SHIFT) #define DSE2_MASK (DSE2_VAL << DSE_SHIFT) #define ODT_MASK (ODT_VAL << ODT_SHIFT) #define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT) #define DQM_MASK (DDR_MODE_MASK | DSE2_MASK) #define SDQS_MASK DSE2_MASK #define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) #define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK) #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) #define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK) #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK) #define MMDC_MDCTL 0x021b0000 #define MMDC_MDPDC 0x021b0004 #define MMDC_MDOTC 0x021b0008 #define MMDC_MDCFG0 0x021b000c #define MMDC_MDCFG1 0x021b0010 #define MMDC_MDCFG2 0x021b0014 #define MMDC_MDMISC 0x021b0018 #define MMDC_MDSCR 0x021b001c #define MMDC_MDREF 0x021b0020 #define MMDC_MDRWD 0x021b002c #define MMDC_MDOR 0x021b0030 #define MMDC_MDASP 0x021b0040 #define MMDC_MAPSR 0x021b0404 #define MMDC_MPZQHWCTRL 0x021b0800 #define MMDC_MPWLGCR 0x021b0808 #define MMDC_MPWLDECTRL0 0x021b080c #define MMDC_MPWLDLST 0x021b0814 #define MMDC_MPODTCTRL 0x021b0818 #define MMDC_MPRDDQBY0DL 0x021b081c #define MMDC_MPRDDQBY1DL 0x021b0820 #define MMDC_MPWRDQBY0DL 0x021b082c #define MMDC_MPWRDQBY1DL 0x021b0830 #define MMDC_MPDGCTRL0 0x021b083c #define MMDC_MPDGDLST0 0x021b0844 #define MMDC_MPRDDLCTL 0x021b0848 #define MMDC_MPRDDLST 0x021b084c #define MMDC_MPWRDLCTL 0x021b0850 #define MMDC_MPWRDLST 0x021b0854 #define MMDC_MPSDCTRL 0x021b0858 #define MMDC_MPRDDLHWCTL 0x021b0860 #define MMDC_MPWRDLHWCTL 0x021b0864 #define MMDC_MPDGHWST0 0x021b087c #define MMDC_MPDGHWST1 0x021b0880 #define MMDC_MPPDCMPR2 0x021b0890 #define MMDC_MPSWDRDR0 0x021b0898 #define MMDC_MPSWDRDR1 0x021b089c #define MMDC_MPSWDRDR2 0x021b08a0 #define MMDC_MPSWDRDR3 0x021b08a4 #define MMDC_MPSWDRDR4 0x021b08a8 #define MMDC_MPSWDRDR5 0x021b08ac #define MMDC_MPSWDRDR6 0x021b08b0 #define MMDC_MPSWDRDR7 0x021b08b4 #define MMDC_MPMUR0 0x021b08b8 #define IOMUXC_GPR0 0x020e4000 #define IOMUXC_GPR1 0x020e4004 #define IOMUXC_GPR2 0x020e4008 #define IOMUXC_GPR3 0x020e400c #define IOMUXC_GPR4 0x020e4010 #define IOMUXC_GPR5 0x020e4014 #define IOMUXC_GPR10 0x020e4028 #define IOMUXC_GPR14 0x020e4048 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0 0x020e001c #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1 0x020e0020 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5 0x020e0030 #define IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6 0x020e0034 #define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA 0x020e0084 #define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA 0x020e0088 #define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK 0x020e00dc #define IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B 0x020e008c #define IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B 0x020e0090 #define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK 0x020e00fc #define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B 0x020e0178 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B 0x020e017c #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0180 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0184 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0188 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e018c #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0190 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0194 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0198 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e019c #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e01a0 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e01a4 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e01a8 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B 0x020e01ac #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e01b4 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0 0x020e02a8 #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1 0x020e02ac #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5 0x020e02bc #define IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6 0x020e02c0 #define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA 0x020e0310 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA 0x020e0314 #define IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B 0x020e0318 #define IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B 0x020e031c #define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x020e042c #define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x020e0440 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0204 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0208 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e020c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0210 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e0214 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0218 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e021c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0220 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e0224 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0228 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e022c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0230 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0234 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0238 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e023c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0244 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0248 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e024c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0250 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x020e0254 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x020e0258 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x020e025c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e0260 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e0264 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0268 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e026c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e0270 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0274 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0278 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e027c #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e0280 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e0284 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0288 #define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK 0x020e0368 #define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK 0x020e0388 #define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B 0x020e0404 #define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B 0x020e0408 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x020e040c #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x020e0410 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x020e0414 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x020e0418 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x020e041c #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x020e0420 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x020e0424 #define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x020e0428 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e0490 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0494 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0498 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e049c #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e04a0 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e04a4 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e04a8 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e04ac #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e04b0 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e04b4 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e0620 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0624 #define IOMUXC_ENET1_REF_CLK1_SELECT_INPUT 0x020e0574 #define IOMUXC_ENET2_REF_CLK2_SELECT_INPUT 0x020e057c dcd_hdr: MXC_DCD_START MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) /* setup I2C pads for PMIC */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0, 0x00000015) MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1, 0x00000015) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0, 0x0000f0b9) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1, 0x0000f0b9) /* ENET_REF_CLK */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK, 0x00000014) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK, 0x000000b1) MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK, 0x00000014) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK, 0x000000b1) MXC_DCD_ITEM(IOMUXC_ENET1_REF_CLK1_SELECT_INPUT, 2) MXC_DCD_ITEM(IOMUXC_ENET2_REF_CLK2_SELECT_INPUT, 2) /* ETN PHY nRST */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6, 0x00000015) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6, 0x000010b0) /* ETN PHY Power */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */ #define CCGR(m) (3 << ((m) * 2)) /* enable all relevant clocks... */ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) /* enable UART clock depending on selected console port */ #if CONFIG_MXC_UART_BASE == UART1_BASE MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(12)) /* UART1 */ #elif CONFIG_MXC_UART_BASE == UART2_BASE MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(14)) /* UART2 */ #elif CONFIG_MXC_UART_BASE == UART3_BASE MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* UART3 */ #elif CONFIG_MXC_UART_BASE == UART4_BASE MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(12)) /* UART4 */ #elif CONFIG_MXC_UART_BASE == UART5_BASE MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(1)) /* UART5 */ #endif MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* default: 0xcfc03f0f APBH-DMA */ // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR()) /* default: 0xfcfc0000 */ // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR()) /* default: 0x0c3ff033 */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, CCGR(2)) /* default: 0xffff3300 ENET */ #ifdef CONFIG_TX6_NAND MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(15) | CCGR(14) | CCGR(13) | CCGR(12)) /* default: 0x0000f3ff GPMI BCH */ #endif // MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR()) /* default: 0x0c3f0c3f */ #ifdef CONFIG_TX6_EMMC MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(2) | CCGR(1)) /* default: 0x00fc3003 USDHC2 USDHC1 */ #else MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */ #endif MXC_DCD_ITEM(IOMUXC_GPR1, 0x00020000) /* default: 0x0f400005 ENET1_TX_CLK output */ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(0x020c80b0, 0) MXC_DCD_ITEM(0x020c80c0, 1) MXC_DCD_ITEM(0x020c80a0, 0x0010201b) /* set video PLL to 648MHz */ /* IOMUX: */ MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000) MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET[12]_TX_CLK output */ MXC_DCD_ITEM(IOMUXC_GPR2, 0x00000000) MXC_DCD_ITEM(IOMUXC_GPR3, 0x00000fff) MXC_DCD_ITEM(IOMUXC_GPR4, 0x00000100) MXC_DCD_ITEM(IOMUXC_GPR5, 0x00000000) MXC_DCD_ITEM(IOMUXC_GPR10, 0x00000003) /* UART1 pad config */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA, 0x00000000) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA, 0x000010b0) /* UART1 TXD */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA, 0x00000000) /* UART1 RXD */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA, 0x000010b0) /* UART1 RXD */ MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B, 0x00000000) /* UART1 CTS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B, 0x000010b0) /* UART1 CTS */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B, 0x00000000) /* UART1 RTS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B, 0x000010b0) /* UART1 RTS */ MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */ #ifdef CONFIG_NAND_MXS /* NAND */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_NAND_CLE, 0x000030b0) /* NANDF_CLE: NANDF_CLE */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B, 0x00000000) /* NAND_RE_B: NANDF_RDn */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B, 0x00000000) /* NAND_WE_B: NANDF_WRn */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */ #endif /* DRAM_DQM[0..1] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK) /* DRAM_A[0..15] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK) /* DRAM_CAS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK) /* DRAM_RAS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK) /* DRAM_SDCLK0 */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK) /* DRAM_RESET */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK) /* DRAM_SDCKE[0..1] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK) /* DRAM_SDBA[0..2] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000) /* DRAM_SDODT[0..1] */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK) /* DRAM_B[0..1]DS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK) /* ADDDS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK) /* DDRMODE_CTL */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK) /* DDRPKE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK) /* DDRMODE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK) /* CTLDS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK) /* DDR_TYPE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK) /* DDRPK */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT) /* DDRHYS */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000) /* SDRAM initialization */ #define WL_DLY_DQS_VAL 7 #define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0) #define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0) /* MDMISC */ MXC_DCD_ITEM(MMDC_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDMISC, 0x00000002) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) /* ZQ calibration */ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */ MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001) MXC_DCD_ITEM(MMDC_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0)) MXC_DCD_ITEM(MMDC_MPDGCTRL0, 0x41ae012f) MXC_DCD_ITEM(MMDC_MPRDDLCTL, 0x3f3f4d4c) /* DQ RD Delay default values */ MXC_DCD_ITEM(MMDC_MPWRDLCTL, 0x3f3f3f3f) /* DQ WR Delay default values */ /* MPRDDQBY[0..7]DL */ MXC_DCD_ITEM(MMDC_MPRDDQBY0DL, 0x33333333) MXC_DCD_ITEM(MMDC_MPRDDQBY1DL, 0x33333333) /* MPRDDQBY[0..7]DL */ MXC_DCD_ITEM(MMDC_MPWRDQBY0DL, 0x33333333) MXC_DCD_ITEM(MMDC_MPWRDQBY1DL, 0x33333333) #define MPMUR_FRC_MSR (1 << 11) MXC_DCD_ITEM(MMDC_MPMUR0, MPMUR_FRC_MSR) /* MDCTL */ MXC_DCD_ITEM(MMDC_MDCTL, MDCTL_VAL) #if BANK_ADDR_BITS > 1 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (3 << 30)) #else MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDMISC, (1 << 30)) #endif MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) /* MSDSCR Conf Req */ MXC_DCD_ITEM(MMDC_MDSCR, 0x00008000) MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC_MDSCR, 0x00004000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC_MDCFG0, MDCFG0_VAL) MXC_DCD_ITEM(MMDC_MDCFG1, MDCFG1_VAL) MXC_DCD_ITEM(MMDC_MDCFG2, MDCFG2_VAL) MXC_DCD_ITEM(MMDC_MDRWD, 0x000026d2) MXC_DCD_ITEM(MMDC_MDOR, MDOR_VAL) MXC_DCD_ITEM(MMDC_MDOTC, MDOTC_VAL) MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_0) MXC_DCD_ITEM(MMDC_MDASP, PHYS_SDRAM_1_SIZE / SZ_32M + 0x3f) /* CS0 MRS: */ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val)) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val)) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) #if BANK_ADDR_BITS > 1 /* CS1 MRS: */ MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val)) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val)) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val)) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) #endif MXC_DCD_ITEM(MMDC_MDREF, 0x0000c000) /* disable refresh */ MXC_DCD_ITEM(MMDC_MDSCR, 0x00008020) /* issue one refresh cycle */ MXC_DCD_ITEM(MMDC_MPODTCTRL, 0x00022222) /* DDR3 calibration */ MXC_DCD_ITEM(MMDC_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */ MXC_DCD_ITEM(MMDC_MAPSR, 1) /* ZQ calibration */ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008010) /* precharge all */ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008040) /* MRS: ZQ calibration */ MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1390001) MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPZQHWCTRL, 0x00010000) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa1380000) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ #if BANK_ADDR_BITS > 1 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ #endif /* DRAM_SDQS[0..1] pad config */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK) /* Read delay calibration */ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPRDDLHWCTL, 0x00000013) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) /* Write delay calibration */ MXC_DCD_ITEM(MMDC_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MPWRDLHWCTL, 0x00000013) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ #if BANK_ADDR_BITS > 1 MXC_DCD_ITEM(MMDC_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */ #endif MXC_DCD_ITEM(MMDC_MPZQHWCTRL, 0xa138002b) MXC_DCD_ITEM(MMDC_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */ MXC_DCD_ITEM(MMDC_MAPSR, (16 << 8) | (0 << 0)) MXC_DCD_ITEM(MMDC_MDPDC, MDPDC_VAL_1) /* MDSCR: Normal operation */ MXC_DCD_ITEM(MMDC_MDSCR, 0x00000000) MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC_MDSCR, 0x00004000) MXC_DCD_END