Merge branch 'u-boot/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / README

diff --git a/README b/README
index f0ffaf491cd9c204b24a49aacf4d9712148cdf32..1130b4f3291628019b86aaf71183a2c6701888d0 100644 (file)
--- a/README
+++ b/README
@@ -423,16 +423,50 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
                This value denotes start offset of DSP CCSR space.
 
-               CONFIG_SYS_FSL_DDR_EMU
-               Specify emulator support for DDR. Some DDR features such as
-               deskew training are not available.
-
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
                Defines the endianess of the CPU. Implementation of those
                values is arch specific.
 
+               CONFIG_SYS_FSL_DDR
+               Freescale DDR driver in use. This type of DDR controller is
+               found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+               SoCs.
+
+               CONFIG_SYS_FSL_DDR_ADDR
+               Freescale DDR memory-mapped register base.
+
+               CONFIG_SYS_FSL_DDR_EMU
+               Specify emulator support for DDR. Some DDR features such as
+               deskew training are not available.
+
+               CONFIG_SYS_FSL_DDRC_GEN1
+               Freescale DDR1 controller.
+
+               CONFIG_SYS_FSL_DDRC_GEN2
+               Freescale DDR2 controller.
+
+               CONFIG_SYS_FSL_DDRC_GEN3
+               Freescale DDR3 controller.
+
+               CONFIG_SYS_FSL_DDRC_ARM_GEN3
+               Freescale DDR3 controller for ARM-based SoCs.
+
+               CONFIG_SYS_FSL_DDR1
+               Board config to use DDR1. It can be enabled for SoCs with
+               Freescale DDR1 or DDR2 controllers, depending on the board
+               implemetation.
+
+               CONFIG_SYS_FSL_DDR2
+               Board config to use DDR2. It can be eanbeld for SoCs with
+               Freescale DDR2 or DDR3 controllers, depending on the board
+               implementation.
+
+               CONFIG_SYS_FSL_DDR3
+               Board config to use DDR3. It can be enabled for SoCs with
+               Freescale DDR3 controllers.
+
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -1979,6 +2013,21 @@ CBFS (Coreboot Filesystem) support
                kernel). Defining CONFIG_STATUS_LED enables this
                feature in U-Boot.
 
+               Additional options:
+
+               CONFIG_GPIO_LED
+               The status LED can be connected to a GPIO pin.
+               In such cases, the gpio_led driver can be used as a
+               status LED backend implementation. Define CONFIG_GPIO_LED
+               to include the gpio_led driver in the U-Boot binary.
+
+               CONFIG_GPIO_LED_INVERTED_TABLE
+               Some GPIO connected LEDs may have inverted polarity in which
+               case the GPIO high value corresponds to LED off state and
+               GPIO low value corresponds to LED on state.
+               In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+               with a list of GPIO LEDs that have inverted polarity.
+
 - CAN Support: CONFIG_CAN_DRIVER
 
                Defining CONFIG_CAN_DRIVER enables CAN driver support
@@ -2056,6 +2105,42 @@ CBFS (Coreboot Filesystem) support
                  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
                  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 
+               - drivers/i2c/sh_i2c.c:
+                 - activate this driver with CONFIG_SYS_I2C_SH
+                 - This driver adds from 2 to 5 i2c buses
+
+                 - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+                 - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+                 - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+                 - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+                 - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+                 - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+                 - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+                 - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+                 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+                 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+                 - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+                 - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
+                 - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+
+               - drivers/i2c/omap24xx_i2c.c
+                 - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+                 - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+               - drivers/i2c/zynq_i2c.c
+                 - activate this driver with CONFIG_SYS_I2C_ZYNQ
+                 - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
+                 - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
+
                additional defines:
 
                CONFIG_SYS_NUM_I2C_BUSES
@@ -3162,7 +3247,7 @@ FIT uImage format:
 
                CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
                Set for the SPL on PPC mpc8xxx targets, support for
-               arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+               drivers/ddr/fsl/libddr.o in SPL binary.
 
                CONFIG_SPL_COMMON_INIT_DDR
                Set for common ddr init with serial presence detect in