same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
+ CONFIG_SYS_FSL_DDR_INTLV_256B
+ DDR controller interleaving on 256-byte. This is a special
+ interleaving mode, handled by Dickens for Freescale layerscape
+ SoCs with ARM core.
+
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
If this option is set, then U-Boot will prevent the environment
variable "splashimage" from being set to a problematic address
- (see README.displaying-bmps and README.arm-unaligned-accesses).
+ (see README.displaying-bmps).
This option is useful for targets where, due to alignment
restrictions, an improperly aligned BMP image will cause a data
abort. If you think you will not have problems with unaligned
its config.mk file). If you find problems enabling this option on
your board please report the problem and send patches!
-- CONFIG_SYS_SYM_OFFSETS
- This is set by architectures that use offsets for link symbols
- instead of absolute values. So bss_start is obtained using an
- offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than
- directly. You should not need to touch this setting.
-
- CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
This is set by OMAP boards for the max time that reset should
be asserted. See doc/README.omap-reset-time for details on how