ARM: tegra: fix CPU VDD comment in Tegra30 CPU init code

[karo-tx-uboot.git] / arch / arm / cpu / arm720t / tegra30 / cpu.c

diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index e16235748449c61bd54715643dd7ee9d278485c5..85a945bc7918581ae8ee722f76eabdbbc59ca84f 100644 (file)
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -60,7 +60,7 @@ static void enable_cpu_power_rail(void)
 
        /*
         * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-        * First set VDD to 1.4V, then enable the VDD regulator.
+        * First set VDD to 1.0V, then enable the VDD regulator.
         */
        tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
        tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
@@ -84,18 +84,6 @@ void t30_init_clocks(void)
        /* Set active CPU cluster to G */
        clrbits_le32(flow->cluster_control, 1 << 0);
 
-       /*
-        * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-        * at 108 MHz. This is glitch free as only the source is changed, no
-        * special precaution needed.
-        */
-       val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-               (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-       writel(val, &clkrst->crc_sclk_brst_pol);
-
        writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
        val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |