mxs: spl: replace bogus early_delay() function with standard udelay() calls

[karo-tx-uboot.git] / arch / arm / cpu / arm926ejs / cache.c

diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 4430578a81c1f7f1dd49f7f41413b50ad499dffd..e5c1a6ae6c92965e20144094a4d9af1a3fd13c9c 100644 (file)
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -2,22 +2,7 @@
  * (C) Copyright 2011
  * Ilya Yanok, EmCraft Systems
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #include <linux/types.h>
 #include <common.h>
@@ -30,7 +15,7 @@
 
 void invalidate_dcache_all(void)
 {
-       asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
+       asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
 }
 
 void flush_dcache_all(void)
@@ -40,7 +25,7 @@ void flush_dcache_all(void)
                "mrc p15, 0, r15, c7, c14, 3\n"
                "bne 0b\n"
                "mcr p15, 0, %0, c7, c10, 4\n"
-               ::"r"(0):"memory"
+                : : "r"(0) : "memory"
        );
 }
 
@@ -67,7 +52,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
                return;
 
        while (start < stop) {
-               asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
+               asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
                start += CONFIG_SYS_CACHELINE_SIZE;
        }
 }
@@ -78,16 +63,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
                return;
 
        while (start < stop) {
-               asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
+               asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
                start += CONFIG_SYS_CACHELINE_SIZE;
        }
 
-       asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
+       asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
@@ -97,25 +77,9 @@ void invalidate_dcache_all(void)
 void flush_dcache_all(void)
 {
 }
-
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long stop)
-{
-}
-
-void flush_cache(unsigned long start, unsigned long size)
-{
-}
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 /*
  * Stub implementations for l2 cache operations
  */
-void __l2_cache_disable(void)
-{
-}
-void l2_cache_disable(void)
-        __attribute__((weak, alias("__l2_cache_disable")));
+__weak void l2_cache_disable(void) {}