#include "mxs_init.h"
+#ifdef CONFIG_SYS_MXS_VDD5V_ONLY
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
+#else
+#define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
+ POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
+#endif
+#ifdef CONFIG_SYS_SPL_VDDD_VAL
+#define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
+#else
+#define VDDD_VAL 1350
+#endif
+#ifdef CONFIG_SYS_SPL_VDDIO_VAL
+#define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
+#else
+#define VDDIO_VAL 3300
+#endif
+#ifdef CONFIG_SYS_SPL_VDDA_VAL
+#define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
+#else
+#define VDDA_VAL 1800
+#endif
+#ifdef CONFIG_SYS_SPL_VDDMEM_VAL
+#define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
+#else
+#define VDDMEM_VAL 1700
+#endif
+
+#ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
+#define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
+#else
+#define VDDD_BO_VAL 150
+#endif
+#ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
+#define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
+#else
+#define VDDIO_BO_VAL 150
+#endif
+#ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
+#define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
+#else
+#define VDDA_BO_VAL 175
+#endif
+#ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
+#define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
+#else
+#define VDDMEM_BO_VAL 25
+#endif
+
+#ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
+#if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
+#error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
+#endif
+#define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
+#else
+/* Brownout default at 3V */
+#define BATT_BO_VAL ((3000 - 2400) / 40)
+#endif
+
+#ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
+static const int fixed_batt_supply = 1;
+#else
+static const int fixed_batt_supply;
+#endif
+
+static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
+
/**
* mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
*
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ debug("SPL: Switching CPU clock to 24MHz XTAL\n");
+
/* Set XTAL as CPU reference clock */
writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
&clkctrl_regs->hw_clkctrl_clkseq_set);
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
- setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
- CLKCTRL_PLL0CTRL0_POWER);
- early_delay(100);
- setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
- CLKCTRL_CLKSEQ_BYPASS_CPU);
+ debug("SPL: Switching CPU core clock source to PLL\n");
+
+ writel(CLKCTRL_PLL0CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
+ /*
+ * The PLL is documented to lock within 10 µs from setting
+ * the POWER bit.
+ */
+ udelay(15);
+
+ /*
+ * TODO: Should the PLL0 FORCE_LOCK bit be set here followed by a
+ * wait on the PLL0 LOCK bit?
+ */
+ writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
+ &clkctrl_regs->hw_clkctrl_clkseq_clr);
+}
+
+static int mxs_power_wait_rtc_stat(u32 mask)
+{
+ int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
+ u32 val;
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
+
+ while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
+ udelay(1);
+ if (timeout-- < 0)
+ break;
+ }
+ return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
}
/**
* This function ungates the RTC block and sets the AUTO_RESTART
* bit to work around a design bug on MX28EVK Rev. A .
*/
-
-static void mxs_power_set_auto_restart(void)
+static int mxs_power_set_auto_restart(int on)
{
- struct mxs_rtc_regs *rtc_regs =
- (struct mxs_rtc_regs *)MXS_RTC_BASE;
+ struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
- writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
- ;
+ debug("SPL: Setting auto-restart bit\n");
- writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
- ;
+ if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
+ return 1;
/* Do nothing if flag already set */
if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
- return;
+ return 0;
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
- ;
+ if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
+ RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
+ return 0;
- setbits_le32(&rtc_regs->hw_rtc_persistent0,
- RTC_PERSISTENT0_AUTO_RESTART);
- writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
- writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
- ;
- while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
- ;
+ if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+ return 1;
+
+ clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
+ !on * RTC_PERSISTENT0_AUTO_RESTART,
+ !!on * RTC_PERSISTENT0_AUTO_RESTART);
+ if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
+ return 1;
+
+ return 0;
}
/**
*/
static void mxs_power_set_linreg(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Set linear regulator 25mV below switching converter */
+ debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+ debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddactrl,
POWER_VDDACTRL_LINREG_OFFSET_MASK,
POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+ debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
*/
static int mxs_get_batt_volt(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = readl(&power_regs->hw_power_battmonitor);
+
volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
volt *= 8;
+
+ debug("SPL: Battery Voltage = %dmV\n", volt);
return volt;
}
*/
static int mxs_is_batt_good(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t volt = mxs_get_batt_volt();
- if ((volt >= 2400) && (volt <= 4300))
+ if ((volt >= 2400) && (volt <= 4300)) {
+ debug("SPL: Battery is good\n");
return 1;
+ }
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_clr);
- early_delay(500000);
+ udelay(500000);
volt = mxs_get_batt_volt();
- if (volt >= 3500)
+ if (volt >= 3500) {
+ debug("SPL: Battery Voltage too high\n");
return 0;
+ }
- if (volt >= 2400)
+ if (volt >= 2400) {
+ debug("SPL: Battery is good\n");
return 1;
+ }
writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
&power_regs->hw_power_charge_clr);
writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+ if (volt >= 3500) {
+ return 0;
+ }
+ if (volt >= 2400) {
+ return 1;
+ }
+ debug("SPL: Battery Voltage too low\n");
return 0;
}
*/
static void mxs_power_setup_5v_detect(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
/* Start 5V detection */
+ debug("SPL: Starting 5V input detection comparator\n");
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK,
POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
*/
static void mxs_src_power_init(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Pre-Configuring power block\n");
/* Improve efficieny and reduce transient ripple */
writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
- setbits_le32(&power_regs->hw_power_battmonitor,
+ if (!fixed_batt_supply) {
+ /* FIXME: This requires the LRADC to be set up! */
+ setbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_EN_BATADJ);
+ } else {
+ clrbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_EN_BATADJ);
+ }
/* Increase the RCSCALE level for quick DCDC response to dynamic load */
clrsetbits_le32(&power_regs->hw_power_loopctrl,
clrsetbits_le32(&power_regs->hw_power_minpwr,
POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
- /* 5V to battery handoff ... FIXME */
- setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ if (!fixed_batt_supply) {
+ /* 5V to battery handoff ... FIXME */
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl_set);
+ udelay(30);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl_clr);
+ }
}
/**
*/
static void mxs_power_init_4p2_params(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring common 4P2 regulator params\n");
/* Setup 4P2 parameters */
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_DROPOUT_CTRL_MASK,
- POWER_DCDC4P2_DROPOUT_CTRL_100MV |
- POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
+ DCDC4P2_DROPOUT_CONFIG);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
*/
static void mxs_enable_4p2_dcdc_input(int xfer)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
uint32_t prev_5v_brnout, prev_5v_droop;
+ debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
+
+ if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return;
+ }
+
prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_PWDN_5VBRNOUT;
prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
POWER_CTRL_ENIRQ_VDD5V_DROOP;
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_clr);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
- clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
-
- if (xfer && (readl(&power_regs->hw_power_5vctrl) &
- POWER_5VCTRL_ENABLE_DCDC)) {
- return;
- }
+ writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, &power_regs->hw_power_ctrl_clr);
/*
* Recording orignal values that will be modified temporarlily
* Disable mechanisms that get erroneously tripped by when setting
* the DCDC4P2 EN_DCDC
*/
- clrbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_VBUSVALID_5VDETECT |
- POWER_5VCTRL_VBUSVALID_TRSH_MASK);
+ writel(POWER_5VCTRL_VBUSVALID_5VDETECT |
+ POWER_5VCTRL_VBUSVALID_TRSH_MASK,
+ &power_regs->hw_power_5vctrl);
writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
if (xfer) {
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_DCDC_XFER);
- early_delay(20);
- clrbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_DCDC_XFER);
-
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_ENABLE_DCDC);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl);
+ udelay(20);
+ writel(POWER_5VCTRL_DCDC_XFER,
+ &power_regs->hw_power_5vctrl_clr);
+
+ writel(POWER_5VCTRL_ENABLE_DCDC,
+ &power_regs->hw_power_5vctrl_set);
} else {
- setbits_le32(&power_regs->hw_power_dcdc4p2,
- POWER_DCDC4P2_ENABLE_DCDC);
+ writel(POWER_DCDC4P2_ENABLE_DCDC,
+ &power_regs->hw_power_dcdc4p2);
}
- early_delay(25);
+ udelay(25);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
if (!pwd_bo)
- clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
+ writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_clr);
while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
writel(POWER_CTRL_VBUS_VALID_IRQ,
&power_regs->hw_power_ctrl_clr);
if (prev_5v_droop)
- clrbits_le32(&power_regs->hw_power_ctrl,
- POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
+ &power_regs->hw_power_ctrl_set);
else
- setbits_le32(&power_regs->hw_power_ctrl,
- POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
+ &power_regs->hw_power_ctrl_clr);
}
/**
*/
static void mxs_power_init_4p2_regulator(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp, tmp2;
+ debug("SPL: Enabling 4P2 regulator\n");
+
setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
* gradually to avoid large inrush current from the 5V cable which can
* cause transients/problems
*/
+ debug("SPL: Charging 4P2 capacitor\n");
mxs_enable_4p2_dcdc_input(0);
if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
POWER_DCDC4P2_ENABLE_DCDC);
writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
&power_regs->hw_power_5vctrl_set);
+
+ debug("SPL: Unable to recover from mx23 errata 5837\n");
hang();
}
* We then check the brownout status. If the brownout status is false,
* the voltage is already close to the target voltage of 4.2V so we
* can go ahead and set the 4P2 current limit to our max target limit.
- * If the brownout status is true, we need to ramp us the current limit
+ * If the brownout status is true, we need to ramp up the current limit
* so that we don't cause large inrush current issues. We step up the
* current limit until the brownout status is false or until we've
* reached our maximum defined 4p2 current limit.
*/
+ debug("SPL: Setting 4P2 brownout level\n");
clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_BO_MASK,
22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
- setbits_le32(&power_regs->hw_power_5vctrl,
- 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+ writel(0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET,
+ &power_regs->hw_power_5vctrl_set);
} else {
tmp = (readl(&power_regs->hw_power_5vctrl) &
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
POWER_STS_DCDC_4P2_BO)) {
tmp = readl(&power_regs->hw_power_5vctrl);
tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
- early_delay(100);
+ udelay(100);
writel(tmp, &power_regs->hw_power_5vctrl);
break;
} else {
tmp2 |= tmp <<
POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
writel(tmp2, &power_regs->hw_power_5vctrl);
- early_delay(100);
+ udelay(100);
}
}
}
*/
static void mxs_power_init_dcdc_4p2_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Switching DC-DC converters to 4P2\n");
if (!(readl(&power_regs->hw_power_dcdc4p2) &
POWER_DCDC4P2_ENABLE_DCDC)) {
+ debug("SPL: Already switched - aborting\n");
hang();
}
*/
static void mxs_power_enable_4p2(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t vdddctrl, vddactrl, vddioctrl;
uint32_t tmp;
+ debug("SPL: Powering up 4P2 regulator\n");
+
vdddctrl = readl(&power_regs->hw_power_vdddctrl);
vddactrl = readl(&power_regs->hw_power_vddactrl);
vddioctrl = readl(&power_regs->hw_power_vddioctrl);
mxs_power_init_dcdc_4p2_source();
writel(vdddctrl, &power_regs->hw_power_vdddctrl);
- early_delay(20);
+ udelay(20);
writel(vddactrl, &power_regs->hw_power_vddactrl);
- early_delay(20);
+ udelay(20);
writel(vddioctrl, &power_regs->hw_power_vddioctrl);
/*
if (tmp)
writel(POWER_CHARGE_ENABLE_LOAD,
&power_regs->hw_power_charge_clr);
+
+ debug("SPL: 4P2 regulator powered-up\n");
}
/**
*/
static void mxs_boot_valid_5v(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Booting from 5V supply\n");
/*
* Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
*/
static void mxs_powerdown(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("Powering Down\n");
+
writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
&power_regs->hw_power_reset);
*/
static void mxs_batt_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring power block to boot from battery\n");
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_clr);
+ writel(POWER_5VCTRL_ENABLE_DCDC,
+ &power_regs->hw_power_5vctrl_clr);
clrbits_le32(&power_regs->hw_power_dcdc4p2,
POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
/* 5V to battery handoff. */
- setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
- early_delay(30);
- clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_set);
+ udelay(30);
+ writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_clr);
writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
clrbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_DISABLE_FET);
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
+ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
- setbits_le32(&power_regs->hw_power_5vctrl,
- POWER_5VCTRL_ENABLE_DCDC);
+ writel(POWER_5VCTRL_ENABLE_DCDC, &power_regs->hw_power_5vctrl_set);
clrsetbits_le32(&power_regs->hw_power_5vctrl,
POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
*/
static void mxs_handle_5v_conflict(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
+ debug("SPL: Resolving 5V conflict\n");
+
setbits_le32(&power_regs->hw_power_vddioctrl,
POWER_VDDIOCTRL_BO_OFFSET_MASK);
if (tmp & POWER_STS_VDDIO_BO) {
/*
- * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
- * unreliable
+ * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
+ * becomes unreliable
*/
+ debug("SPL: VDDIO has a brownout\n");
mxs_powerdown();
break;
}
if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
mxs_boot_valid_5v();
break;
} else {
+ debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
mxs_powerdown();
break;
}
+ /*
+ * TODO: I can't see this being reached. We'll either
+ * powerdown or boot from a stable 5V supply.
+ */
if (tmp & POWER_STS_PSWITCH_MASK) {
+ debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
mxs_batt_boot();
break;
}
*/
static void mxs_5v_boot(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Configuring power block to boot from 5V input\n");
/*
* NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
* but their implementation always returns 1 so we omit it here.
*/
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: 5V VDD good\n");
mxs_boot_valid_5v();
return;
}
- early_delay(1000);
+ udelay(1000);
if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ debug("SPL: 5V VDD good (after delay)\n");
mxs_boot_valid_5v();
return;
}
+ debug("SPL: 5V VDD not good\n");
mxs_handle_5v_conflict();
}
+static void mxs_fixed_batt_boot(void)
+{
+ writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+
+ writel(POWER_5VCTRL_ENABLE_DCDC |
+ POWER_5VCTRL_ILIMIT_EQ_ZERO |
+ POWER_5VCTRL_PWDN_5VBRNOUT |
+ POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+ &power_regs->hw_power_5vctrl_set);
+
+ writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
+
+ clrbits_le32(&power_regs->hw_power_vdddctrl,
+ POWER_VDDDCTRL_DISABLE_FET |
+ POWER_VDDDCTRL_ENABLE_LINREG |
+ POWER_VDDDCTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddactrl,
+ POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
+ POWER_VDDACTRL_DISABLE_STEPPING);
+
+ clrbits_le32(&power_regs->hw_power_vddioctrl,
+ POWER_VDDIOCTRL_DISABLE_FET |
+ POWER_VDDIOCTRL_DISABLE_STEPPING);
+
+ /* Stop 5V detection */
+ writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
+ &power_regs->hw_power_5vctrl_clr);
+}
+
/**
* mxs_init_batt_bo() - Configure battery brownout threshold
*
*/
static void mxs_init_batt_bo(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Initialising battery brown-out level to %u.%uV\n",
+ (BATT_BO_VAL * 40 + 2400) / 1000,
+ (BATT_BO_VAL * 40 + 2400) / 100 % 10);
/* Brownout at 3V */
clrsetbits_le32(&power_regs->hw_power_battmonitor,
POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
- 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+ BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
*/
static void mxs_switch_vddd_to_dcdc_source(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Switching VDDD to DC-DC converters\n");
clrsetbits_le32(&power_regs->hw_power_vdddctrl,
POWER_VDDDCTRL_LINREG_OFFSET_MASK,
*/
static void mxs_power_configure_power_source(void)
{
- int batt_ready, batt_good;
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
struct mxs_lradc_regs *lradc_regs =
(struct mxs_lradc_regs *)MXS_LRADC_BASE;
+ debug("SPL: Configuring power source\n");
+
mxs_src_power_init();
- if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
- batt_ready = mxs_is_batt_ready();
- if (batt_ready) {
- /* 5V source detected, good battery detected. */
- mxs_batt_boot();
- } else {
- batt_good = mxs_is_batt_good();
- if (!batt_good) {
- /* 5V source detected, bad battery detected. */
- writel(LRADC_CONVERSION_AUTOMATIC,
- &lradc_regs->hw_lradc_conversion_clr);
- clrbits_le32(&power_regs->hw_power_battmonitor,
- POWER_BATTMONITOR_BATT_VAL_MASK);
+ if (!fixed_batt_supply) {
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (mxs_is_batt_ready()) {
+ /* 5V source detected, good battery detected. */
+ mxs_batt_boot();
+ } else {
+ if (!mxs_is_batt_good()) {
+ /* 5V source detected, bad battery detected. */
+ writel(LRADC_CONVERSION_AUTOMATIC,
+ &lradc_regs->hw_lradc_conversion_clr);
+ clrbits_le32(&power_regs->hw_power_battmonitor,
+ POWER_BATTMONITOR_BATT_VAL_MASK);
+ }
+ mxs_5v_boot();
}
- mxs_5v_boot();
+ } else {
+ /* 5V not detected, booting from battery. */
+ mxs_batt_boot();
}
} else {
- /* 5V not detected, booting from battery. */
- mxs_batt_boot();
+ mxs_fixed_batt_boot();
}
+ /*
+ * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
+ * from USB VBUS
+ */
mxs_power_clock2pll();
mxs_init_batt_bo();
mxs_switch_vddd_to_dcdc_source();
-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23
/* Fire up the VDDMEM LinReg now that we're all set. */
+ debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
&power_regs->hw_power_vddmemctrl);
#endif
*/
static void mxs_enable_output_rail_protection(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Enabling output rail protection\n");
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
*/
static int mxs_get_vddio_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
- if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
+ !(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
+
tmp = readl(&power_regs->hw_power_vddioctrl);
if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
}
return 0;
-
}
/**
*/
static int mxs_get_vddd_power_source_off(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t tmp;
tmp = readl(&power_regs->hw_power_vdddctrl);
return 0;
}
+static int mxs_get_vdda_power_source_off(void)
+{
+ uint32_t tmp;
+
+ tmp = readl(&power_regs->hw_power_vddactrl);
+ if (tmp & POWER_VDDACTRL_DISABLE_FET) {
+ if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
+ return 1;
+ }
+ }
+
+ if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
+ if (!(readl(&power_regs->hw_power_5vctrl) &
+ POWER_5VCTRL_ENABLE_DCDC)) {
+ return 1;
+ }
+ }
+
+ if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
+ if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
+ POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
struct mxs_vddx_cfg {
uint32_t *reg;
uint8_t step_mV;
uint16_t lowest_mV;
+ uint16_t highest_mV;
int (*powered_by_linreg)(void);
uint32_t trg_mask;
uint32_t bo_irq;
uint32_t bo_enirq;
uint32_t bo_offset_mask;
uint32_t bo_offset_offset;
+ uint16_t bo_min_mV;
+ uint16_t bo_max_mV;
};
+#define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
+
static const struct mxs_vddx_cfg mxs_vddio_cfg = {
- .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
- hw_power_vddioctrl),
-#if defined(CONFIG_MX23)
+ .reg = POWER_REG(hw_power_vddioctrl),
+#if defined(CONFIG_SOC_MX23)
.step_mV = 25,
#else
.step_mV = 50,
#endif
.lowest_mV = 2800,
+ .highest_mV = 3600,
.powered_by_linreg = mxs_get_vddio_power_source_off,
.trg_mask = POWER_VDDIOCTRL_TRG_MASK,
.bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
.bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
.bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
.bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
+ .bo_min_mV = 2700,
+ .bo_max_mV = 3475,
};
static const struct mxs_vddx_cfg mxs_vddd_cfg = {
- .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
- hw_power_vdddctrl),
+ .reg = POWER_REG(hw_power_vdddctrl),
.step_mV = 25,
.lowest_mV = 800,
+ .highest_mV = 1575,
.powered_by_linreg = mxs_get_vddd_power_source_off,
.trg_mask = POWER_VDDDCTRL_TRG_MASK,
.bo_irq = POWER_CTRL_VDDD_BO_IRQ,
.bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
.bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
.bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
+ .bo_min_mV = 800,
+ .bo_max_mV = 1475,
+};
+
+static const struct mxs_vddx_cfg mxs_vdda_cfg = {
+ .reg = POWER_REG(hw_power_vddactrl),
+ .step_mV = 25,
+ .lowest_mV = 1800,
+ .highest_mV = 3600,
+ .powered_by_linreg = mxs_get_vdda_power_source_off,
+ .trg_mask = POWER_VDDACTRL_TRG_MASK,
+ .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
+ .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
+ .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
+ .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
+ .bo_min_mV = 1400,
+ .bo_max_mV = 2175,
};
-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23
static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
- .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
- hw_power_vddmemctrl),
+ .reg = POWER_REG(hw_power_vddmemctrl),
.step_mV = 50,
- .lowest_mV = 1700,
+ .lowest_mV = 1500,
+ .highest_mV = 1700,
.powered_by_linreg = NULL,
.trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
.bo_irq = 0,
* value is also in mV.
*/
static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
- uint32_t new_target, uint32_t new_brownout)
+ uint32_t new_target, uint32_t bo_offset)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
uint32_t cur_target, diff, bo_int = 0;
- uint32_t powered_by_linreg = 0;
- int adjust_up, tmp;
+ int powered_by_linreg = 0;
+ int adjust_up;
+
+ if (new_target < cfg->lowest_mV) {
+ new_target = cfg->lowest_mV;
+ }
+ if (new_target > cfg->highest_mV) {
+ new_target = cfg->highest_mV;
+ }
+
+ if (new_target - bo_offset < cfg->bo_min_mV) {
+ bo_offset = new_target - cfg->bo_min_mV;
+ } else if (new_target - bo_offset > cfg->bo_max_mV) {
+ bo_offset = new_target - cfg->bo_max_mV;
+ }
- new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
+ bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
cur_target = readl(cfg->reg);
cur_target &= cfg->trg_mask;
if (adjust_up && cfg->bo_irq) {
if (powered_by_linreg) {
- bo_int = readl(cfg->reg);
- clrbits_le32(cfg->reg, cfg->bo_enirq);
+ bo_int = readl(&power_regs->hw_power_ctrl);
+ writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
}
setbits_le32(cfg->reg, cfg->bo_offset_mask);
}
if (powered_by_linreg ||
(readl(&power_regs->hw_power_sts) &
- POWER_STS_VDD5V_GT_VDDIO))
- early_delay(500);
- else {
- for (;;) {
- tmp = readl(&power_regs->hw_power_sts);
- if (tmp & POWER_STS_DC_OK)
- break;
+ POWER_STS_VDD5V_GT_VDDIO)) {
+ udelay(500);
+ } else {
+ while (!(readl(&power_regs->hw_power_sts) &
+ POWER_STS_DC_OK)) {
+
}
}
if (adjust_up && powered_by_linreg) {
writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
if (bo_int & cfg->bo_enirq)
- setbits_le32(cfg->reg, cfg->bo_enirq);
+ writel(cfg->bo_enirq,
+ &power_regs->hw_power_ctrl_set);
}
clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
- new_brownout << cfg->bo_offset_offset);
+ bo_offset << cfg->bo_offset_offset);
}
}
*/
static void mxs_setup_batt_detect(void)
{
+ debug("SPL: Starting battery voltage measurement logic\n");
+
mxs_lradc_init();
mxs_lradc_enable_batt_measurement();
- early_delay(10);
+ udelay(10);
}
/**
*/
static void mxs_ungate_power(void)
{
-#ifdef CONFIG_MX23
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
+#ifdef CONFIG_SOC_MX23
writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
#endif
}
+#ifdef CONFIG_CONFIG_MACH_MX28EVK
+#define auto_restart 1
+#else
+#define auto_restart 0
+#endif
+
/**
* mxs_power_init() - The power block init main function
*
* This function calls all the power block initialization functions in
* proper sequence to start the power block.
*/
+#define VDDX_VAL(v) (v) / 1000, (v) / 100 % 10
+
void mxs_power_init(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
+ debug("SPL: Initialising Power Block\n");
mxs_ungate_power();
mxs_power_clock2xtal();
- mxs_power_set_auto_restart();
+ if (mxs_power_set_auto_restart(auto_restart)) {
+ serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
+ }
mxs_power_set_linreg();
- mxs_power_setup_5v_detect();
- mxs_setup_batt_detect();
+ if (!fixed_batt_supply) {
+ mxs_power_setup_5v_detect();
+ mxs_setup_batt_detect();
+ }
mxs_power_configure_power_source();
mxs_enable_output_rail_protection();
- mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
- mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
-#ifdef CONFIG_MX23
- mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700);
+ debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
+ VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
+ mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
+ debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
+ VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
+ mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
+ debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
+ VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
+ mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
+#ifdef CONFIG_SOC_MX23
+ debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
+ VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
+ mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
+#else
+ clrbits_le32(&power_regs->hw_power_vddmemctrl,
+ POWER_VDDMEMCTRL_ENABLE_LINREG);
#endif
writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
-
- writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
-
- early_delay(1000);
+ if (!fixed_batt_supply)
+ writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ &power_regs->hw_power_5vctrl_set);
}
#ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
*/
void mxs_power_wait_pswitch(void)
{
- struct mxs_power_regs *power_regs =
- (struct mxs_power_regs *)MXS_POWER_BASE;
-
+ debug("SPL: Waiting for power switch input\n");
while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
;
}
projects / karo-tx-uboot.git / blobdiff