arm:am33xx: Make dram_init call sdram_init() in some contexts

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / board.c

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 07ab91c3eea9e5e05d694a1c310fd0f091679114..9a69b6ccfac4ff6197d8b6a214bbd8279a8fc587 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -27,18 +27,24 @@
 #include <miiphy.h>
 #include <cpsw.h>
 #include <asm/errno.h>
+#include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
 #include <asm/omap_musb.h>
+#include <asm/davinci_rtc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct gpio_bank gpio_bank_am33xx[4] = {
+static const struct gpio_bank gpio_bank_am33xx[] = {
        { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
        { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
        { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
        { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+       { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+       { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
 };
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
@@ -56,12 +62,6 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-void setup_clocks_for_console(void)
-{
-       /* Not yet implemented */
-       return;
-}
-
 /* AM33XX has two MUSB controllers which can be host or gadget */
 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
        (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
@@ -142,28 +142,36 @@ int arch_misc_init(void)
        return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
-void rtc32k_enable(void)
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+       do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+static void rtc32k_enable(void)
 {
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+       struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 
        /*
         * Unlock the RTC's registers.  For more details please see the
         * RTC_SS section of the TRM.  In order to unlock we need to
         * write these specific values (keys) in this order.
         */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
+       writel(RTC_KICK0R_WE, &rtc->kick0r);
+       writel(RTC_KICK1R_WE, &rtc->kick1r);
 
        /* Enable the RTC 32K OSC by setting bits 3 and 6. */
        writel((1 << 3) | (1 << 6), &rtc->osc);
 }
+#endif
 
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-
-void uart_soft_reset(void)
+static void uart_soft_reset(void)
 {
        struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
        u32 regval;
@@ -180,4 +188,66 @@ void uart_soft_reset(void)
        regval |= UART_SMART_IDLE_EN;
        writel(regval, &uart_base->uartsyscfg);
 }
+
+static void watchdog_disable(void)
+{
+       struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+
+       writel(0xAAAA, &wdtimer->wdtwspr);
+       while (readl(&wdtimer->wdtwwps) != 0x0)
+               ;
+       writel(0x5555, &wdtimer->wdtwspr);
+       while (readl(&wdtimer->wdtwwps) != 0x0)
+               ;
+}
+
+void s_init(void)
+{
+       /*
+        * The ROM will only have set up sufficient pinmux to allow for the
+        * first 4KiB NOR to be read, we must finish doing what we know of
+        * the NOR mux in this space in order to continue.
+        */
+#ifdef CONFIG_NOR_BOOT
+       enable_norboot_pin_mux();
+#endif
+       /*
+        * Save the boot parameters passed from romcode.
+        * We cannot delay the saving further than this,
+        * to prevent overwrites.
+        */
+#ifdef CONFIG_SPL_BUILD
+       save_omap_boot_params();
+#endif
+       watchdog_disable();
+       timer_init();
+       set_uart_mux_conf();
+       setup_clocks_for_console();
+       uart_soft_reset();
+#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
+       gd->baudrate = CONFIG_BAUDRATE;
+       serial_init();
+       gd->have_console = 1;
+#elif defined(CONFIG_SPL_BUILD)
+       gd = &gdata;
+       preloader_console_init();
 #endif
+       prcm_init();
+       set_mux_conf_regs();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
+       /* Enable RTC32K clock */
+       rtc32k_enable();
+#endif
+#ifdef CONFIG_SPL_BUILD
+       sdram_init();
+#endif
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif /* !CONFIG_SYS_DCACHE_OFF */