PLL1_CLOCK = 0,
PLL2_CLOCK,
PLL3_CLOCK,
-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53
PLL4_CLOCK,
#endif
PLL_CLOCKS,
[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53
[PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
#endif
};
}
}
-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53
void ldb_clk_enable(int ldb)
{
switch (ldb) {
{
u32 mask;
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
if (i2c_num > 1)
-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)
if (i2c_num > 2)
#endif
return -EINVAL;
clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
}
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
void enable_usb_phy1_clk(bool enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
{
/* i.MX51 has a single USB PHY clock, so do nothing here. */
}
-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)
void enable_usb_phy1_clk(bool enable)
{
unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
return ret;
}
-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51
/*
* This function returns the Frequency Pre-Multiplier clock.
*/
u32 ccsr = readl(&mxc_ccm->ccsr);
if (ccsr & MXC_CCM_CCSR_LP_APM)
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)
ret_val = get_fpm();
-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)
ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
#endif
else
u32 ret_val = 0;
u32 cbcmr = readl(&mxc_ccm->cbcmr);
u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51
u32 cbcdr = readl(&mxc_ccm->cbcdr);
if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
/* Switch back */
__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
break;
-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53
case PLL4_CLOCK:
/* Switch to pll4 bypass clock */
__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
return 0;
}
-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53
/*
* The clock for the external interface can be set to use internal clock
* if fuse bank 4, row 3, bit 2 is set.
pr_clk_val(PLL2, freq);
freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
pr_clk_val(PLL3, freq);
-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53
freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
pr_clk_val(PLL4, freq);
#endif