#error "CPU_TYPE not defined"
#endif
+#ifdef CONFIG_HW_WATCHDOG
+#define wdog_base ((void *)WDOG1_BASE_ADDR)
+#define WDOG_WCR 0x00
+#define WCR_WDE (1 << 2)
+#define WDOG_WSR 0x02
+
+void hw_watchdog_reset(void)
+{
+ if (readw(wdog_base + WDOG_WCR) & WCR_WDE) {
+ static u16 toggle = 0xaaaa;
+
+ writew(toggle, wdog_base + WDOG_WSR);
+ toggle ^= 0xffff;
+ }
+}
+#endif
+
u32 get_cpu_rev(void)
{
#ifdef CONFIG_MX51
#endif
#if defined(CONFIG_FEC_MXC)
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+static void __imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+ __attribute__((weak, alias("__imx_get_mac_from_fuse")));
+
#endif
void set_chipselect_size(int const cs_size)
writel(reg, &iomuxc_regs->gpr1);
}
+#if 1
+void cpu_cache_initialization(void)
+{
+ printf("Enabling L2 cache\n");
+ asm volatile(
+ "mrc 15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #0x2\n"
+ "mcr 15, 0, r0, c1, c0, 1\n"
+ : : : "r0", "memory"
+ );
+}
+#endif
+
#ifdef CONFIG_MX53
void boot_mode_apply(unsigned cfg_val)
{